CN106158750A - Semiconductor element and manufacture method thereof - Google Patents
Semiconductor element and manufacture method thereof Download PDFInfo
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- CN106158750A CN106158750A CN201510144098.2A CN201510144098A CN106158750A CN 106158750 A CN106158750 A CN 106158750A CN 201510144098 A CN201510144098 A CN 201510144098A CN 106158750 A CN106158750 A CN 106158750A
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- raceway groove
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses the manufacture method of a kind of semiconductor element.Stack layer is formed in substrate.Patterning stack layer, the multiple stack architectures extended along a first direction with formation, between two adjacent stack architectures, there is the raceway groove extended along a first direction, each raceway groove has multiple width portion and multiple narrow portion.Width portion is more than the narrow portion Breadth Maximum along second direction along the Breadth Maximum of second direction.Form electric charge storage layer, to cover basal surface and the sidewall in width portion and to fill up narrow portion.Form conductor layer, to fill up width portion.Another offer is a kind of by the semiconductor element made by said method.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof.
Background technology
Integrated, in order to reach high density and dynamical target, in system along with semiconductor element
During manufacturing semiconductor element, tendency forms the structure of upwards storehouse, more effectively to utilize wafer area.Cause
This, the semiconductor structure with high-aspect-ratio (high aspect ratio) frequently appears in small size unit
In part.
Manufacture the above-mentioned semiconductor structure with high-aspect-ratio, it will usually carry out etching repeatedly, with shape
Become the material layer of different pattern.But, due to size microminiaturization, cause alignment to be difficult to, etching technics
It is difficult to control or figure generation deformation after etching, even results in structural collapse, and quasiconductor may be affected
The yield of component technology.Therefore, how to reduce the number of times of etching technics, and reduce figure product after etching
Raw deformation or the phenomenon of structural collapse, for the problem of current desired research.
Summary of the invention
The present invention provides the manufacture method of a kind of semiconductor element, can reduce the number of times of etching technics, and
After reducing etching, figure produces deformation or the phenomenon of structural collapse.
The present invention provides the manufacture method of a kind of semiconductor element, and it comprises the following steps.In substrate
Form stack layer.Patterning stack layer, the multiple stack architectures extended along a first direction with formation,
Having, between two adjacent stack architectures, the raceway groove extended along a first direction, each raceway groove has phase
Multiple width portions the most alternately and multiple narrow portion, the widest portion is more than narrow along the Breadth Maximum of second direction
Portion is along the Breadth Maximum of second direction.Form electric charge storage layer, to cover basal surface and the side in width portion
Wall and fill up narrow portion.Form conductor layer, to fill up width portion.
In one embodiment of this invention, above-mentioned width portion is narrow portion edge along the Breadth Maximum of second direction
2-5 times of Breadth Maximum of second direction.
In one embodiment of this invention, the shape in above-mentioned width portion include circle, ellipse, square,
Rectangle, rhombus or a combination thereof.
In one embodiment of this invention, above-mentioned electric charge storage layer is composite bed, and composite bed includes oxidation
Nitride layer, nitride layer or a combination thereof.
In one embodiment of this invention, above-mentioned stack layer includes conductor layer, dielectric layer or a combination thereof.
In one embodiment of this invention, each width portion on above-mentioned raceway groove in second direction with adjacent
The arrangement mode in each width portion on raceway groove includes being arranged side by side, alternately arranged or a combination thereof.
The present invention provides again a kind of semiconductor element, and semiconductor element includes substrate, stack architecture, electricity
Lotus storage layer and conductor layer.Above-mentioned stack architecture, be positioned at two stack architectures adjacent in substrate it
Between there is the raceway groove extended along a first direction, each raceway groove has multiple width portions of alternateing and many
Individual narrow portion, the widest portion is more than the narrow portion maximum along second direction along the Breadth Maximum of second direction
Width.Electric charge storage layer, covers basal surface and the sidewall in width portion and fills up narrow portion.Conductor layer, fills up
Width portion.
In one embodiment of this invention, above-mentioned width portion is narrow portion edge along the Breadth Maximum of second direction
2-5 times of Breadth Maximum of second direction.
In one embodiment of this invention, the shape in above-mentioned width portion include circle, ellipse, square,
Rectangle, rhombus or a combination thereof.
In one embodiment of this invention, above-mentioned electric charge storage layer is composite bed, and composite bed includes oxidation
Nitride layer, nitride layer or a combination thereof.
In one embodiment of this invention, above-mentioned stack architecture includes conductor layer, dielectric layer or a combination thereof.
In one embodiment of this invention, each width portion on above-mentioned raceway groove in second direction with adjacent
The arrangement mode of each narrow portion on raceway groove includes being arranged side by side, alternately arranged or a combination thereof.
Based on above-mentioned, the present invention has the wide portion of different in width and the raceway groove of narrow portion by formation, in order to
Follow-up in raceway groove formed electric charge storage layer time, in width portion formation electric charge storage layer while, in narrow portion
The electric charge storage layer formed the most just can be not required to the most additionally carry out forming insulation directly as insulating barrier
The technique of layer.Thereby can reduce the program of technique, and then reduce figure generation deformation or structure after etching
The phenomenon collapsed.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and join
Close institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 E is the manufacturer according to the semiconductor element depicted in one embodiment of the invention
The top view of method.
Fig. 2 A to Fig. 2 E is the system along the semiconductor element depicted in the A-A ' line of Figure 1A to Fig. 1 E
Make the generalized section of method.
Fig. 3, Fig. 4 and Fig. 5 are according to the semiconductor element depicted in the connection with several embodiments of the present invention
Top view.
[symbol description]
10: substrate
11: stack layer
12: stack architecture
14: conductor layer
16: dielectric layer
18: hard mask layer
22: electric charge storage layer
23: groove
24: conductor layer
30: wide portion
40: narrow portion
100,200,300: semiconductor element
D1, D2, D3: direction
T: raceway groove
W1, w2, w3, w4: width
T1: thickness
A-A ': line
Detailed description of the invention
Figure 1A to Fig. 1 E is the manufacturer according to the semiconductor element depicted in one embodiment of the invention
The upper schematic diagram of method.Fig. 2 A to Fig. 2 E is along half depicted in the A-A ' line of Figure 1A to Fig. 1 E
The generalized section of the manufacture method of conductor element.Fig. 3, Fig. 4 and Fig. 5 are according to the present invention's
The top view of the semiconductor element depicted in connection with several embodiments.
Referring to Figure 1A and Fig. 2 A, first provide substrate 10.Substrate 10 can include quasiconductor
Material, insulating material, conductor material or the combination in any of above-mentioned material.The material example of substrate 10
As being selected from by Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP institute
The material that constituted of at least one material in the group of composition or any be suitable for present invention process
Physical arrangement.Substrate 10 includes single layer structure or multiple structure.Additionally, be used as insulating barrier
Upper silicon (silicon on insulator, SOI) substrate.Substrate 10 e.g. silicon or germanium silicide.
Referring to Figure 1B and Fig. 2 B, in substrate 10, form stack layer 11.Stack layer 11
E.g. include that multi-layer conductive layer 14 and multilayer dielectric layer 16 are constituted.Stack layer 11 is e.g.
By multi-layer conductive layer 14 and multilayer dielectric layer 16 with in the way of alternateing toward storehouse above substrate 10
Constitute.In one embodiment, stack layer 11 e.g. 8 layers, 16 layers, 32 layers or more layers storehouse
Constitute, but the present invention is not limited.The material of conductor layer 14 include unadulterated quasiconductor or
The polysilicon of doped quasiconductor, e.g. polysilicon or doping.The thickness example of conductor layer 14
In this way between 200 angstroms to 600 angstroms.The forming method of conductor layer 14 includes that chemical gaseous phase deposits
Method.In one embodiment, conductor layer 14 is e.g. as bit line or the wordline of semiconductor element 100.
The material of dielectric layer 16 includes that oxide, nitride, nitrogen oxides or dielectric constant are less than 4
Advanced low-k materials.The thickness of dielectric layer 16 is e.g. between 200 angstroms to 600 angstroms.It is situated between
The forming method of electric layer 16 e.g. thermal oxidation method or chemical vapour deposition technique.
Continuing referring to Figure 1B and Fig. 2 B, stack layer 11 can optionally further include formation and firmly cover
Mold layer 18.Hard mask layer 18 is e.g. positioned at the superiors of stack layer 11, but the present invention not as
Limit.Hard mask layer 18 can be single or multiple lift.The material of hard mask layer 18 e.g. silicon oxide, nitrogen
SiClx or other suitable materials.Formed hard mask layer 18 method include chemical vapour deposition technique or
Metalorganic chemical vapor deposition method (MOCVD).
Referring to Fig. 1 C and Fig. 2 C, pattern stack layer 11, to be formed along a first direction
Multiple stack architectures 12 that D1 extends.The method e.g. photoetching of patterning stack layer 11 and etching method.
Etching method e.g. dry etching method.Dry etching method can be ise, reactive ion etching
Deng.There is between adjacent two stack architectures 12 the raceway groove T that D1 extends along a first direction.Each
Bar raceway groove T has the multiple wide portion 30 and multiple narrow portion 40 replaced each other.From semiconductor element
The plane (plane that first direction D1 and second direction D2 are constituted) that the upward angle of visibility degree of 100 is seen,
The shape in wide portion 30 can be rectangle (Fig. 1 E), circular (Fig. 3), oval (Fig. 4, major axis
D1 in a first direction；Fig. 5, major axis is in second direction D2), square, rhombus or a combination thereof；Narrow
The shape in portion 40 can be rectangle (Fig. 1 E, Fig. 3-4), square, ampuliform or a combination thereof.But this
Invention is not limited.From the point of view of the plane that second direction D2 and third direction D3 are constituted, wide
The section shape of portion 30 and narrow portion 40 can be arbitrary shape, e.g. V-type, U-shaped, rhombus or its
Combination.
Wide portion 30 is more than narrow portion 40 along second direction along the Breadth Maximum w1 of second direction D2
The Breadth Maximum w2 of D2.In one embodiment, wide portion 30 is along the Breadth Maximum of second direction D2
W1 is narrow portion 40 along 2-5 times of the Breadth Maximum w2 of second direction D2.In another embodiment,
Narrow portion 40 stores along the Breadth Maximum w2 of second direction D2 less than or equal to the electric charge formed afterwards
Layer 22 is along 2 times (refer to following Fig. 2 D) of the thickness t1 of third direction D3.First direction
D1 is different from second direction D2.Third direction D3 is different from first direction D1 and and second direction
D2 is different.For example, first direction D1 and second direction D2 substantial orthogonality；First direction
D1 and third direction D3 substantial orthogonality；Second direction D2 and third direction D3 substantial orthogonality.
In one embodiment, wide portion 30 along second direction D2 Breadth Maximum w1 e.g. between
Between 300 angstroms to 1500 angstroms, narrow portion 40 is e.g. situated between along the Breadth Maximum w2 of second direction D2
Between 150 angstroms to 450 angstroms.
Refer to Fig. 1 E, Fig. 3 and Fig. 4, each wide portion 30 of raceway groove T is in second direction D2
With the arrangement mode in each wide portion 30 of adjacent another raceway groove T for being staggered.But, this
Bright it is not limited.In another embodiment, each wide portion 30 of raceway groove T is in second direction D2
Can also be to be arranged side by side with the arrangement mode in each wide portion 30 of adjacent another raceway groove T.
Referring to Fig. 1 D and Fig. 2 D, raceway groove T forms electric charge storage layer 22.Specifically
Saying, the position electric charge storage layer 22 in the wide portion of raceway groove T 30 only covers basal surface and the sidewall in wide portion 30,
And the wide portion 30 of unfilled raceway groove T；Then will at the electric charge storage layer 22 of raceway groove T narrow portion 40 in position
Raceway groove T fills up.It is to say, after forming electric charge storage layer in raceway groove T, in raceway groove T width portion
30 can leave groove 23, and follow-up conductor layer of inserting is as wordline or bit line；And raceway groove T narrow portion 40
Then because being filled up by electric charge storage layer 22, and conductor layer cannot be further filled with.Electric charge storage layer 22
E.g. dielectric layer.Electric charge storage layer 22 can be composite bed, for example, electric charge storage layer 22
E.g. include the composite bed that oxide skin(coating), nitride layer or a combination thereof are constituted.More specifically,
The material of electric charge storage layer 22 includes silicon nitride, silicon oxide or a combination thereof.In one embodiment, electricity
Lotus storage layer 22 is e.g. by oxide layer/nitration case/oxide layer (Oxide/Nitride/Oxide, ONO)
The composite bed constituted.Electric charge storage layer 22 need to be more than each along the thickness t1 of third direction D3
Narrow portion 40 is along more than 1/2 times of Breadth Maximum w2 of second direction D2, to guarantee to form electric charge
Narrow portion 40 can be filled up during storage layer 22.Electric charge storage layer 22 is along the thickness t1 of third direction D3
E.g. between 100 angstroms to 250 angstroms, but the present invention is not limited.Electric charge storage layer 22
Forming method e.g. thermal oxidation method or chemical vapour deposition technique.
Referring to Fig. 1 D, Fig. 1 E, Fig. 2 D and Fig. 2 E, form conductor layer 24, to fill up width
Portion 30.Specifically, conductor layer 24 fills up groove 23.The material of conductor layer 24 e.g. polycrystalline
Silicon, the polysilicon of doping, metal, metal alloy or a combination thereof.Metal e.g. tungsten.Metal alloy
E.g. alusil alloy.The method forming conductor layer 24 includes chemical vapour deposition technique.Implement one
In example, first sidewall in wide portion 30 can form barrier layer with bottom being formed before conductor layer 24.
The material of barrier layer e.g. includes titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.Barrier layer
Thickness is e.g. between 10 angstroms to 200 angstroms.The forming method of barrier layer e.g. chemical gaseous phase
Sedimentation.The invention is not restricted to this.In another embodiment, before forming conductor layer 24 completely,
The electric charge storage layer 22 of the bottom in wide portion 30 is processed, to form conductor layer 24 passage, but,
The present invention is not limited.Conductor layer 24 is e.g. as wordline or the bit line of memory element.One
In embodiment, conductor layer 24 is the wordline (such as channel architecture) as memory element；It is positioned at storehouse
Conductor layer 14 in structure 12 is as the bit line (such as gate structure) of memory element.Real at another
Executing in example, conductor layer 24 is the bit line as memory element；The conductor layer being positioned in stack architecture 12
14 as the wordline of memory element.The invention is not restricted to this.
In embodiments of the present invention, raceway groove T narrow portion 40 Breadth Maximum w2 is set smaller than or is equal to
2 times of the electric charge storage layer 22 thickness t1 formed afterwards so that electric charge storage layer 22 can fill up narrow
Portion 40；And conductor layer 24 can insert wide portion 30 because left by unfilled electric charge storage layer 22
Groove 23.Therefore, the electric charge storage layer 22 being positioned at narrow portion 40 can be directly as insulating barrier, with electricity
Adjacent two conductor layers 24 on sexual isolation D1 along a first direction.And it is follow-up other without carrying out again
Insulating barrier technique.It is to say, by forming the single technique of electric charge storage layer 22, can simultaneously in
The electric charge storage layer 22 that wide portion 30 is formed, and form insulating barrier in narrow portion 40.
On the other hand, be there is the multiple wide portion 30 replaced each other by each raceway groove T with many
Individual narrow portion 40, and each wide portion 30 of each raceway groove T is at second direction D2 and adjacent another
The arrangement mode in each wide portion 30 of raceway groove T be alternately arranged, be arranged side by side or a combination thereof, up to
In relatively known technology, stack architecture regardless of width portion Yu narrow portion is difficult to the effect collapsed.Specifically,
Regardless of in the stack architecture of width portion and narrow portion in known technology, between two adjacent channel stack architecture away from
Distance between the wide portion being all the present embodiment.The embodiment of the present invention then can by above-mentioned width portion and
The mode of narrow portion arrangement, increases the distance of stack architecture between adjacent two raceway grooves, and then reduces quasiconductor
The phenomenon that structure collapses.
Refer to Fig. 1 E and Fig. 2 E, the semiconductor element 100 of the embodiment of the present invention include substrate 10,
Stack architecture 12, electric charge storage layer 22 and conductor layer 24.Stack architecture 12 is positioned in substrate 10
And it has raceway groove T each other.Raceway groove T D1 along a first direction extends, and has phase each other
Multiple wide portion 30 the most alternately and multiple narrow portion 40.Electric charge storage layer 22, is filled among raceway groove T.
Electric charge storage layer 22 among the wide portion 30 of raceway groove T, unfilled wide portion 30, only cover basal surface
With sidewall, and leave groove 23；Electric charge storage layer 22 among the narrow portion 40 of raceway groove T, then will
Narrow portion 40 is filled up.Conductor layer 24, fills up groove 23.The material of conductor layer 24 and manufacture method are such as
Upper described, repeat no more in this.
The material of the insulating barrier of the semiconductor element 100 of the present invention and the material phase of electric charge storage layer 22
With.Specifically, the semiconductor element 100 of the present invention be positioned at the electric charge storage layer 22 of narrow portion 40 can
As follow-up insulating barrier, the electric charge storage layer 22 being positioned at wide portion 30 can store as follow-up electric charge
Layer.In one embodiment, when narrow portion 40 along the Breadth Maximum w2 of second direction D2 less than electric charge
When storage layer 22 is along 2 times of the thickness t1 of third direction D3, then it is positioned at narrow portion 40 and is positioned at width
The number of plies of the electric charge storage layer 22 in portion 30 can differ.
Referring to Fig. 1 E, 3 and 4, in the above-described embodiment (Fig. 1 E), the shape in wide portion 30
Shape is square.In other embodiments, unlike the embodiments above be wide portion 30 be shaped as circle
Shape (Fig. 3) or oval (Fig. 4 and Fig. 5), other structures, material, thickness and manufacture method
As it has been described above, repeat no more in this.
The embodiment of the present invention the manufacture method of semiconductor element can be applicable in dynamic randon access
Deposit (DRAM), NAND gate flash memory (NAND flash), NOR-type flash memory (NOR-flash) etc.,
But the present invention is not limited.
In sum, the embodiment of the present invention has different in width in order to separating the raceway groove of stack architecture
Width portion and narrow portion, be therefore subsequently formed electric charge storage layer can by raceway groove narrow portion fill up electric charge storage layer,
Directly as insulating barrier.Therefore, follow-up being not required to carries out other technique forming isolation structures, thereby again
The number of times of etching technics can be reduced, and then reduce figure generation deformation or the phenomenon of structural collapse after etching,
Promote electrical performance and the process yields of semiconductor element.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, Ren Hesuo
Belong to and technical field has usually intellectual, without departing from the spirit and scope of the present invention, when making
A little change and retouching, therefore protection scope of the present invention is when being defined depending on appended claims scope
Be as the criterion.
Claims (12)
1. a manufacture method for semiconductor element, including:
A stack layer is formed in a substrate；
Pattern this stack layer, to form the multiple stack architectures extended along a first direction, adjacent
Two stack architectures between have along one first direction extend a raceway groove, each raceway groove has phase
Multiple width portions the most alternately and multiple narrow portion, wherein these wide portions are along the Breadth Maximum of a second direction
More than these narrow portions along the Breadth Maximum of this second direction；
Form an electric charge storage layer, to cover basal surface and the sidewall in these width portions and to fill up these narrow portions；
And
Form a conductor layer, to fill up these width portions.
The manufacture method of semiconductor element the most according to claim 1, wherein these edges, width portion
The Breadth Maximum of this second direction is these narrow portions along 2-5 times of Breadth Maximum of this second direction.
The manufacture method of semiconductor element the most according to claim 1, wherein these width portions
Shape includes circle, ellipse, square, rectangle, rhombus or a combination thereof.
The manufacture method of semiconductor element the most according to claim 1, wherein this electric charge stores
Layer is a composite bed, and this composite bed includes oxide skin(coating), nitride layer or a combination thereof.
The manufacture method of semiconductor element the most according to claim 1, wherein this stack layer bag
Include conductor layer, dielectric layer or a combination thereof.
The manufacture method of semiconductor element the most according to claim 1, on each of which raceway groove
Each width portion at the arrangement mode bag of this second direction with each width portion on adjacent each raceway groove
Include be arranged side by side, alternately arranged or a combination thereof.
7. a semiconductor element, including:
One substrate；
Multiple stack architectures are positioned in this substrate, have along one between two adjacent stack architectures
The raceway groove that one direction extends, each raceway groove has the multiple width portions and multiple narrow portion alternateed, its
In these wide portions along a second direction Breadth Maximum more than these narrow portions along this second direction
Breadth Maximum；
One electric charge storage layer, covers basal surface and the sidewall in these width portions and fills up these narrow portions；And
One conductor layer, fills up these width portions.
Semiconductor element the most according to claim 7, wherein these width portions are along this second party
To Breadth Maximum be these narrow portions along 2-5 times of Breadth Maximum of this second direction.
Semiconductor element the most according to claim 7, wherein the shape in these width portions includes circle
Shape, ellipse, square, rectangle, rhombus or a combination thereof.
Semiconductor element the most according to claim 7, wherein this electric charge storage layer be one be combined
Layer, this composite bed includes oxide skin(coating), nitride layer or a combination thereof.
11. semiconductor elements according to claim 7, wherein these stack architectures include conductor
Layer, dielectric layer or a combination thereof.
12. semiconductor elements according to claim 7, the wherein each width portion on these raceway grooves
Arrangement mode in this second direction with each narrow portion on these adjacent raceway grooves includes being arranged side by side,
Alternately arranged or a combination thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510144098.2A CN106158750B (en) | 2015-03-30 | 2015-03-30 | Semiconductor element and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510144098.2A CN106158750B (en) | 2015-03-30 | 2015-03-30 | Semiconductor element and its manufacturing method |
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| CN106158750A true CN106158750A (en) | 2016-11-23 |
| CN106158750B CN106158750B (en) | 2018-12-07 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729305A (en) * | 2018-07-17 | 2020-01-24 | 旺宏电子股份有限公司 | Memory element and method for manufacturing the same |
| CN112017951A (en) * | 2020-08-07 | 2020-12-01 | 福建省晋华集成电路有限公司 | Method for forming pattern layout |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20090056255A (en) * | 2007-11-30 | 2009-06-03 | 주식회사 하이닉스반도체 | Semiconductor memory device and manufacturing method thereof |
| CN103137645A (en) * | 2011-11-25 | 2013-06-05 | 三星电子株式会社 | Semiconductor memory device having three-dimensionally arranged resistive memory cells |
| CN103928467A (en) * | 2013-01-11 | 2014-07-16 | 三星电子株式会社 | Three-dimensional semiconductor device |
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2015
- 2015-03-30 CN CN201510144098.2A patent/CN106158750B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090056255A (en) * | 2007-11-30 | 2009-06-03 | 주식회사 하이닉스반도체 | Semiconductor memory device and manufacturing method thereof |
| CN103137645A (en) * | 2011-11-25 | 2013-06-05 | 三星电子株式会社 | Semiconductor memory device having three-dimensionally arranged resistive memory cells |
| CN103928467A (en) * | 2013-01-11 | 2014-07-16 | 三星电子株式会社 | Three-dimensional semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729305A (en) * | 2018-07-17 | 2020-01-24 | 旺宏电子股份有限公司 | Memory element and method for manufacturing the same |
| CN112017951A (en) * | 2020-08-07 | 2020-12-01 | 福建省晋华集成电路有限公司 | Method for forming pattern layout |
| CN112017951B (en) * | 2020-08-07 | 2022-03-04 | 福建省晋华集成电路有限公司 | Method for forming pattern layout |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106158750B (en) | 2018-12-07 |
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