CN106158682A - A kind of method obtaining asymmetric unit grid stack capacitor - Google Patents

Abstract

nullThe present invention relates to technical field of manufacturing semiconductors，Particularly relate to a kind of method obtaining asymmetric unit grid stack capacitor，By provide one setting source-drain electrode characteristic dimension all with the source electrode in asymmetric MOS device to be measured or the equivalently-sized symmetrical MOS device that drains，So that Cgs and Cgd of this symmetry MOS device is all equal with Cgs or Cgd of this unsymmetric structure to be measured，And utilize the relation curve feature between Cgc and Vgs of this symmetry MOS device to obtain the grid stack capacitor value of this asymmetric device structures，I.e. obtain the value of Cgs and Cgd of this symmetry MOS device，The value of corresponding Cgs or Cgd the most just obtaining unsymmetric structure to be measured，And further with the relation curve feature between Cgc and Vgs of asymmetric MOS device to be measured and the value of Cgs or Cgd of unsymmetric structure to be measured，To obtain the grid stack capacitor value of this unsymmetric structure to be measured accurately.

Description

A kind of method obtaining asymmetric unit grid stack capacitor

Technical field

The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of acquisition asymmetric unit The method of grid stack capacitor.

Background technology

At present, due to the source configuration in asymmetric device structures (asymmetric device) It is asymmetric with drain electrode structure, its gate-source capacitance (gate to source can be caused Capacitance, is called for short Cgs) (gate to drain capacitance is called for short with gate leakage capacitance Cgd) value differs, such as LDMOS (Laterally-Diffused Metal Oxide Semiconductor, abbreviation-LDMOS) etc..

Fig. 1 is gate groove capacitance curve figure；As it is shown in figure 1, to above-mentioned symmetrical device When structure carries out capacitance measurement, although gate groove electric capacity (gate to channel can be passed through Capacitance, is called for short Cgc) and gate source voltage (gate to source voltage is called for short Vgs) Between relation curve feature obtain the grid stack capacitor value (the of this asymmetric device structures Total value of gate overlap capacitance), but owing to the value of Cgs from Cgd is different, Cause the value and the value of Cgd being difficult to obtain this asymmetric device structures Cgs accurately.

Summary of the invention

For above-mentioned technical problem, this application provides a kind of asymmetric unit grid that obtain and stack electricity The method held, described method includes:

One gate-source capacitance and the unequal asymmetric MOS device to be measured of gate leakage capacitance are provided；

Use the preparation technology identical with the source electrode of described asymmetric MOS device to be measured, preparation The source electrode of one symmetrical MOS device and drain electrode, so that the grid source electricity of this symmetry MOS device Appearance, gate leakage capacitance are all equal with the gate-source capacitance of described asymmetric MOS device to be measured；

Use the gate groove electric capacity measuring the described symmetrical MOS device of technique acquisition, and according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Calculate the described symmetrical gate-source capacitance of MOS device, gate leakage capacitance, described to be measured to obtain The gate-source capacitance of asymmetric MOS device；

Use the gate groove electric capacity measuring the technique described asymmetric MOS device to be measured of acquisition, and Gate groove electric capacity, gate-source capacitance and gate leakage capacitance according to this asymmetric MOS device to be measured it Between functional relationship, calculate the gate leakage capacitance of described asymmetric MOS device to be measured.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor In method, the gate groove electric capacity of described symmetrical MOS device and its gate-source capacitance, gate leakage capacitance it Between functional relationship include below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

Q_overlap.d=Q_overlap.s；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})];$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid Voltage between body district, W_activeRepresenting the width of active area, CGSO represents that grid is to source region Overlap capacitance in each raceway groove unit length, V_gsRepresent the voltage between grid source electrode, CGSL Represent the grid overlap capacitance to each active area unit length of source region, V_gs.overlapRepresent grid Superimposed voltage between source electrode, CKAPPAS represents source side coefficient based on overlap capacitance.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor In method, the gate groove electric capacity of described asymmetric MOS device to be measured and its gate-source capacitance, grid leak Functional relationship between electric capacity includes below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})];$

$\frac{Q_{\mathrm{overlap}.d}}{W_{\mathrm{active}}}=\mathrm{CGDO}*V_{\mathrm{gd}}+\mathrm{CGDL}[V_{\mathrm{gd}}-V_{\mathrm{gd}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAD}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gd}.\mathrm{overlap}}}{\mathrm{CKAPPAD}}})]$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid Voltage between body district, W_activeRepresenting the width of active area, CGDO represents that grid is to drain region Overlap capacitance in each raceway groove unit length, V_gdRepresent the voltage between grid leak pole, CGDL Represent the grid overlap capacitance to each active area unit length in drain region, V_gd.overlapRepresent grid Superimposed voltage between drain electrode, CKAPPAD represents drain side coefficient based on overlap capacitance.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

The breadth length ratio of the raceway groove according to described symmetrical MOS device is entered with this symmetry MOS device When row measures technique, the ratio between the temperature value of local environment determines described symmetrical MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part；

The breadth length ratio of the raceway groove according to described asymmetric MOS device to be measured is to be measured asymmetric with this When MOS device carries out measuring technique, the ratio between the temperature value of local environment determines described Letter between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of asymmetric MOS device to be measured Number relation.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

When described symmetrical MOS device is carried out measuring technique, by this symmetry MOS device Source electrode, drain electrode and substrate short circuit；

When described asymmetric MOS device to be measured carries out measuring technique, this is to be measured asymmetric The source electrode of MOS device, drain electrode and substrate short circuit.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

Use the preparation technology identical with the drain electrode of described asymmetric MOS device to be measured, preparation The source electrode of described symmetrical MOS device and drain electrode, so that the grid source of this symmetry MOS device Electric capacity, gate leakage capacitance are all equal with the gate leakage capacitance of described asymmetric MOS device to be measured；

Use the gate groove electric capacity measuring the described symmetrical MOS device of technique acquisition, and according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Obtain the described symmetrical gate-source capacitance of MOS device, gate leakage capacitance, and then obtain described to be measured The gate leakage capacitance of asymmetric MOS device；

Use the gate groove electric capacity measuring the technique described asymmetric MOS device to be measured of acquisition, and Gate groove electric capacity, gate-source capacitance and gate leakage capacitance according to this asymmetric MOS device to be measured it Between functional relationship, obtain the gate-source capacitance of described asymmetric MOS device to be measured.

Present invention also provides a kind of method obtaining asymmetric unit grid stack capacitor, described side Method includes:

One substrate is provided；

Synchronize the most at least to prepare an asymmetric MOS device to be measured and a symmetry MOS device；

Continuously form described asymmetric MOS device to be measured, described symmetrical MOS device each Grid；

Measure the gate groove electric capacity of described symmetrical MOS device, and according to this symmetry MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part, it is described right to calculate Claim the gate-source capacitance of MOS device, gate leakage capacitance, and then obtain described asymmetric MOS to be measured The gate-source capacitance of device；

Measure the gate groove electric capacity of described asymmetric MOS device to be measured, and to be measured non-according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Calculate the gate leakage capacitance of described asymmetric MOS device to be measured；

Wherein, the source doping region of described symmetrical expression MOS device, drain doping region are all and institute The source doping region stating asymmetric MOS device to be measured is formed in same example doping operation, So that the gate-source capacitance of described symmetrical expression MOS device, gate leakage capacitance are all asymmetric with described The gate-source capacitance of formula MOS device is equal.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor In method, the gate groove electric capacity of described symmetrical MOS device and its gate-source capacitance, gate leakage capacitance it Between functional relationship include below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

Q_overlap.d=Q_overlap.s；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})];$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid Voltage between body district, W_activeRepresenting the width of active area, CGSO represents that grid is to source region Overlap capacitance in each raceway groove unit length, V_gsRepresent the voltage between grid source electrode, CGSL Represent the grid overlap capacitance to each active area unit length of source region, V_gs.overlapRepresent grid Superimposed voltage between source electrode, CKAPPAS represents source side coefficient based on overlap capacitance.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor In method, the gate groove electric capacity of described asymmetric MOS device to be measured and its gate-source capacitance, grid leak Functional relationship between electric capacity includes below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})]$

$\frac{Q_{\mathrm{overlap}.d}}{W_{\mathrm{active}}}=\mathrm{CGDO}*V_{\mathrm{gd}}+\mathrm{CGDL}[V_{\mathrm{gd}}-V_{\mathrm{gd}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAD}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gd}.\mathrm{overlap}}}{\mathrm{CKAPPAD}}})]$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid Voltage between body district, W_activeRepresenting the width of active area, CGDO represents that grid is to drain region Overlap capacitance in each raceway groove unit length, V_gdRepresent the voltage between grid leak pole, CGDL Represent the grid overlap capacitance to each active area unit length in drain region, V_gd.overlapRepresent grid Superimposed voltage between drain electrode, CKAPPAD (Coefficient of bias-dependent overlap Capacitance for the drain side) represent drain side coefficient based on overlap capacitance.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

The breadth length ratio of the raceway groove according to described symmetrical MOS device is entered with this symmetry MOS device When row measures technique, the ratio between the temperature value of local environment determines described symmetrical MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part；

The breadth length ratio of the raceway groove according to described asymmetric MOS device to be measured is to be measured asymmetric with this When MOS device carries out measuring technique, the ratio between the temperature value of local environment determines described Letter between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of asymmetric MOS device to be measured Number relation.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

When described symmetrical MOS device is carried out measuring technique, by this symmetry MOS device Source electrode, drain electrode and substrate short circuit；

When described asymmetric MOS device to be measured carries out measuring technique, this is to be measured asymmetric The source electrode of MOS device, drain electrode and substrate short circuit.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

The source doping region of described symmetrical expression MOS device, drain doping region are all to be measured with described The drain doping region of asymmetric MOS device is formed in same example doping operation, so that The gate-source capacitance of described symmetrical expression MOS device, gate leakage capacitance all with described asymmetric MOS The gate leakage capacitance of device is equal；

Measure the gate groove electric capacity of described symmetrical MOS device, and according to this symmetry MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part, it is described right to calculate Claim the gate-source capacitance of MOS device, gate leakage capacitance, and then obtain described asymmetric MOS to be measured The gate leakage capacitance of device；

Measure the gate groove electric capacity of described asymmetric MOS device to be measured, and to be measured non-according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Calculate the gate-source capacitance of described asymmetric MOS device to be measured.

As a preferred embodiment, the above-mentioned side obtaining asymmetric unit grid stack capacitor Method also includes:

The source doping region of described symmetrical expression MOS device and the dopant ion of drain doping region thereof Type, concentration, area, shape all with the source dopant of described asymmetric MOS device to be measured District is identical.

In sum, owing to have employed technique scheme, the one that the application proposes obtains non- The method of symmetrical mounting grid stack capacitor, equal by the characteristic dimension providing the source-drain electrode of a setting With the source electrode in asymmetric MOS device to be measured or the equivalently-sized symmetrical MOS device that drains Part so that Cgs and Cgd of this symmetry MOS device all with this unsymmetric structure to be measured Cgs or Cgd is equal, and utilizes the relation between Cgc and Vgs of this symmetry MOS device Curvilinear characteristic obtains the grid stack capacitor value of this asymmetric device structures, i.e. obtains this symmetry The value of Cgs and Cgd of MOS device, the most just obtains unsymmetric structure to be measured The value of Cgs or Cgd, and further with Cgc and Vgs of asymmetric MOS device to be measured Between relation curve feature and the value of Cgs or Cgd of unsymmetric structure to be measured, to obtain The value of Cgd or Cgs of this unsymmetric structure to be measured, obtains this to be measured asymmetric the most accurately The grid stack capacitor value of structure.

Accompanying drawing explanation

Fig. 1 is gate groove capacitance curve figure；

Fig. 2 is the structural representation of asymmetric MOS device to be measured in the embodiment of the present application；

Fig. 3 is the structural representation of the symmetrical MOS device of preparation in the embodiment of the present application；

Fig. 4 is the gate groove capacitance curve of the symmetrical MOS device of preparation in the embodiment of the present application Figure；

Fig. 5 is the gate groove capacitance curve of asymmetric MOS device to be measured in the embodiment of the present application Figure.

Detailed description of the invention

Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is further described:

The method obtaining asymmetric unit grid stack capacitor in the present embodiment, is mainly based upon following Formula illustrates.

Gate electrode side is stacked electricity (Gate Overlap Charge) formula:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)-------------------------------formula is 1.

Source class lateral capacitance (Drain side) formula:

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})]$ --- ----------------------------------------------------------------------------------------------------------formula is 2. $V_{\mathrm{gs}.\mathrm{overlap}}=\frac{1}{2}(V_{\mathrm{gs}}+{\mathrm{\δ}}_1-\sqrt{{(V_{`\mathrm{gs}}+{\mathrm{\δ}}_1)}^2+{4\mathrm{\δ}}_1})$ -----------------------------------------------formula is 3.

Drain lateral capacitance (Drain side) formula:

$\frac{Q_{\mathrm{overlap}.d}}{W_{\mathrm{active}}}=\mathrm{CGDO}*V_{\mathrm{gd}}+\mathrm{CGDL}[V_{\mathrm{gd}}-V_{\mathrm{gd}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAD}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gd}.\mathrm{overlap}}}{\mathrm{CKAPPAD}}})]$ ----------------------------------------------------------------------------------------------------------formula is 4. $V_{\mathrm{gd}.\mathrm{overlap}}=\frac{1}{2}(V_{\mathrm{gd}}+{\mathrm{\δ}}_1-\sqrt{{(V_{`\mathrm{gd}}+{\mathrm{\δ}}_1)}^2+{4\mathrm{\δ}}_1})$ ----------------------------------------------formula is 5.

Electricity formula in symmetrical MOS device:

Q_overlap.d=Q_overlap.s-----------------------------------------------------------------------------------formula is 6.

Wherein, above-mentioned formula 1.-6. in, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked electricity of drain side, Q_overlap.sRepresent the stacked electricity of source class side, CGBO Represent grid overlap capacitance (the represents the to each raceway groove unit length in body district Gate-to-body overlap capacitance per unit channel length), L_activeIndicate The length of source region, V_gbRepresent the voltage between grid body district, W_activeRepresent the width of active area, CGSO represents the grid overlap capacitance to each raceway groove unit length of source region, V_gsRepresent grid Voltage between source electrode, CGSL represents that grid is to each active area unit length of source region Overlap capacitance, V_gs.overlapRepresenting the superimposed voltage between grid source electrode, CKAPPAS represents source side Coefficient based on overlap capacitance, CGDO represents that grid is to each raceway groove unit length in drain region Overlap capacitance, V_gdRepresenting the voltage between grid leak pole, CGDL represents every to drain region of grid Overlap capacitance in individual active area unit length, V_gd.overlapRepresent the superposition electricity between grid leak pole Pressure, CKAPPAD represents drain side coefficient based on overlap capacitance.

Preferably, above-mentioned V_gs.overlap=V_gd.overlap=0.02V.

Fig. 2 is the structural representation of asymmetric MOS device to be measured in the embodiment of the present application, as Shown in Fig. 2, first, an asymmetric MOS device to be measured is provided according to test technology demand, As in figure 2 it is shown, this asymmetric MOS device to be measured includes grid 11, and it is arranged on this grid The source electrode 12 of 11 both sides and drain electrode 13, and this source electrode 12 and drain electrode 13 are relative to grid 11 Being asymmetrical, this allows for the value of gate-source capacitance Cgs of this asymmetric MOS device to be measured Unequal with the value of its gate leakage capacitance Cgd.

Secondly, in order to accurately obtain gate-source capacitance Cgs of above-mentioned asymmetric MOS device to be measured With the value of gate leakage capacitance Cgd, then need the source electrode according to above-mentioned asymmetric MOS device to be measured 12 and/or drain electrode 13 preparation process condition and step, prepare matched symmetrical MOS Device (symmetric device)；The most just with the preparation process condition according to source electrode 12 and step Suddenly it is described in detail as a example by preparing matched symmetrical MOS device:

Fig. 3 is the structural representation of the symmetrical MOS device of preparation in the embodiment of the present application, as Shown in Fig. 3, use and prepare the identical preparation process condition of source electrode 12 and prepared by step with above-mentioned The source electrode 22 of one symmetrical MOS device and drain electrode 23 so that be positioned at the source electrode of grid 21 both sides 22 and drain electrode 23 characteristic size such as width (width), length (length), thickness Etc. (thickness) parameter and material etc. are all identical with source electrode 12, as long as i.e. making this symmetry The value of gate-source capacitance Cgs of MOS device and the value of gate leakage capacitance Cgd are all to be measured with above-mentioned The value of gate-source capacitance Cgs of asymmetric MOS device is equal, formula 6..

Afterwards, by source electrode 22 and drain electrode 23 short circuits (the i.e. source-drain electrode of this symmetry MOS device Voltage Vgd=0), use measurement device, obtain the gate groove curve of this symmetry MOS device Figure；Fig. 4 is the gate groove capacitance curve of the symmetrical MOS device of preparation in the embodiment of the present application Figure, transverse axis represents gate source voltage V_GS, the longitudinal axis represents gate groove electric capacity Cgc, according to Fig. 4 is The value of the gate groove electric capacity Cgc of this symmetry MOS device can be obtained accurately, and due to this system The value of gate-source capacitance Cgs of standby symmetrical MOS device and the value of gate leakage capacitance Cgd are equal, And then value and the grid of gate-source capacitance Cgs of this symmetrical MOS device prepared can be known accurately The value of drain capacitance Cgd.

Simultaneously as the value of gate-source capacitance Cgs of this symmetrical MOS device prepared and grid leak The value of the value of electric capacity Cgd and gate-source capacitance Cgs of asymmetric MOS device to be measured is the most equal, The most just can obtain gate-source capacitance Cgs of asymmetric MOS device to be measured accurately Value；I.e. according to formula 1., formula 2., formula 3. and formula 6., just can know above-mentioned accurately The value of gate-source capacitance Cgs of to be measured asymmetric MOS device.

Finally, by the source electrode 12 of this asymmetric MOS device to be measured with drain electrode 33 also short circuit (i.e. Source-drain voltage Vgd (gate to drain voltage)=0), to be measured asymmetric to obtain this The gate groove curve of MOS device；Fig. 5 is asymmetric MOS device to be measured in the embodiment of the present application The gate groove capacitance curve figure of part, transverse axis represents gate source voltage V_GS, the longitudinal axis represents gate groove electricity Hold Cgc, this grid ditch to asymmetric MOS device to be measured can be obtained accurately according to Fig. 5 The value of road electric capacity Cgc, and to obtain this in above-mentioned processing step to be measured asymmetric simultaneously The value of gate-source capacitance Cgs of MOS device, this makes it possible to know that this is to be measured non-right accurately Claim the value of gate leakage capacitance Cgd of MOS device, i.e. according to formula 1., formula 4., formula 5. And formula is 6., the gate leakage capacitance of above-mentioned asymmetric MOS device to be measured just can be known accurately The value of Cgd.

Further, prepare and it due to the preparation process condition as a example by drain electrode 13 and step Preparation method as a example by method and the source electrode 12 of the symmetrical MOS device of coupling extremely approximates, This just not describes in detail, specifically can be found in the content of above-mentioned record；See also Fig. 2～4 institute Show, preparing matched symmetry with the preparation process condition according to drain electrode 13 and step During MOS device, then it is to use to drain 13 identical preparation process condition and steps with above-mentioned preparation Suddenly, the source electrode 22 of the symmetrical MOS device of preparation one and drain electrode 23, it is now placed in grid 21 liang The ginsengs such as the source electrode 22 of side and the size such as width (width) of drain electrode 23, length (length) Number all with drain 13 equivalently-sized, i.e. make gate-source capacitance Cgs of this symmetry MOS device Value and gate leakage capacitance Cgd value all with the grid leak of above-mentioned to be measured asymmetric MOS device electricity The value holding Cgd is equal.

Afterwards, by source electrode 22 and drain electrode 23 short circuits (the i.e. source-drain electrode of this symmetry MOS device Voltage Vsd=0), to obtain the gate groove curve of this symmetry MOS device, and according to Fig. 4 Obtain the value of the gate groove electric capacity Cgc of this symmetry MOS device, equally this symmetry prepared The value of gate-source capacitance Cgs of MOS device and the value of gate leakage capacitance Cgd are equal, and then can be accurate The value of true gate-source capacitance Cgs knowing this symmetrical MOS device prepared and gate leakage capacitance The value of Cgd.

Then, value and the grid leak of gate-source capacitance Cgs of this symmetrical MOS device prepared are utilized The value of the value of electric capacity Cgd and the gate leakage capacitance Cgd of asymmetric MOS device to be measured is the most equal Characteristic, to obtain the value of the gate leakage capacitance Cgd of asymmetric MOS device to be measured.

Finally, by the source electrode 12 of this asymmetric MOS device to be measured with drain electrode 13 also short circuit (i.e. Source-drain voltage Vsd=0), to obtain the gate groove curve of this asymmetric MOS device to be measured； And this gate groove electric capacity to asymmetric MOS device to be measured can be obtained accurately according to Fig. 5 The value of Cgc, and utilize this asymmetric MOS device to be measured obtained in above-mentioned processing step The value of the gate leakage capacitance Cgd of part, this makes it possible to know this asymmetric MOS to be measured accurately The value of gate-source capacitance Cgs of device.

To sum up, owing to have employed technique scheme, the one that the application proposes obtains asymmetric The method of device grid stack capacitor, by provide one setting source-drain electrode characteristic dimension all with treat The source electrode in asymmetric MOS device surveyed or the equivalently-sized symmetrical MOS device that drains, So that Cgs and Cgd of this symmetry MOS device all with the Cgs of this unsymmetric structure to be measured Or Cgd is equal, and utilize the relation curve between Cgc and Vgs of this symmetry MOS device Feature obtains the grid stack capacitor value of this asymmetric device structures, i.e. obtains this symmetry MOS The value of Cgs and Cgd of device, the most just obtains the Cgs of unsymmetric structure to be measured Or between the value of Cgd, and Cgc and Vgs further with asymmetric MOS device to be measured Relation curve feature and the value of Cgs or Cgd of unsymmetric structure to be measured, treat obtaining this Survey the value of Cgd or Cgs of unsymmetric structure, obtain this unsymmetric structure to be measured the most accurately Grid stack capacitor value.

By explanation and accompanying drawing, give typical case's enforcement of the ad hoc structure of detailed description of the invention Example, based on present invention spirit, also can make other conversion.Although foregoing invention proposes existing Preferred embodiment, but, these contents be not intended as limitation.

For a person skilled in the art, after reading described above, each middle variations and modifications Will be apparent to undoubtedly.Therefore, appending claims should be regarded as and contains the true of the present invention Sincere figure and whole variations and modifications of scope.In Claims scope any and all etc. The scope of valency and content, be all considered as still belonging to the intent and scope of the invention.

Claims (13)

1. the method obtaining asymmetric unit grid stack capacitor, it is characterised in that described Method includes:

One gate-source capacitance and the unequal asymmetric MOS device to be measured of gate leakage capacitance are provided；

Use the preparation technology identical with the source electrode of described asymmetric MOS device to be measured, preparation The source electrode of one symmetrical MOS device and drain electrode, so that the grid source electricity of this symmetry MOS device Appearance, gate leakage capacitance are all equal with the gate-source capacitance of described asymmetric MOS device to be measured；

Use the gate groove electric capacity measuring the described symmetrical MOS device of technique acquisition, and according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Calculate the described symmetrical gate-source capacitance of MOS device, gate leakage capacitance, described to be measured to obtain The gate-source capacitance of asymmetric MOS device；

Use the gate groove electric capacity measuring the technique described asymmetric MOS device to be measured of acquisition, and Gate groove electric capacity, gate-source capacitance and gate leakage capacitance according to this asymmetric MOS device to be measured it Between functional relationship, calculate the gate leakage capacitance of described asymmetric MOS device to be measured.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 1, It is characterized in that, the gate groove electric capacity of described symmetrical MOS device and its gate-source capacitance, grid leak Functional relationship between electric capacity includes below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

Q_overlap.d=Q_overlap.s；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})];$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid And the voltage between body district, W_activeRepresenting the width of active area, CGSO represents that grid is to source region Each raceway groove unit length on overlap capacitance, V_gsRepresent the voltage between grid source electrode, CGSL represents the grid overlap capacitance to each active area unit length of source region, V_gs.overlap Representing the superimposed voltage between grid source electrode, CKAPPAS represents that source side is based on overlap capacitance and is Number.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 1, It is characterized in that, the gate groove electric capacity of described asymmetric MOS device to be measured and its gate-source capacitance, Functional relationship between gate leakage capacitance includes below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})]$

$\frac{Q_{\mathrm{overlap}.d}}{W_{\mathrm{active}}}=\mathrm{CGDO}*V_{\mathrm{gd}}+\mathrm{CGDL}[V_{\mathrm{gd}}-V_{\mathrm{gd}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAD}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gd}.\mathrm{overlap}}}{\mathrm{CKAPPAD}}})]$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid And the voltage between body district, W_activeRepresenting the width of active area, CGDO represents that grid is to drain region Each raceway groove unit length on overlap capacitance, V_gdRepresent the voltage between grid leak pole, CGDL represents the grid overlap capacitance to each active area unit length in drain region, V_gd.overlap Representing the superimposed voltage between grid leak pole, CKAPPAD represents that drain side is based on overlap capacitance Coefficient.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 1, It is characterized in that, described method also includes:

The breadth length ratio of the raceway groove according to described symmetrical MOS device is entered with this symmetry MOS device When row measures technique, the ratio between the temperature value of local environment determines described symmetrical MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part；

The breadth length ratio of the raceway groove according to described asymmetric MOS device to be measured is to be measured asymmetric with this When MOS device carries out measuring technique, the ratio between the temperature value of local environment determines described Letter between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of asymmetric MOS device to be measured Number relation.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 1, It is characterized in that, described method also includes:

When described symmetrical MOS device is carried out measuring technique, by this symmetry MOS device Source electrode, drain electrode and substrate short circuit；

When described asymmetric MOS device to be measured carries out measuring technique, this is to be measured asymmetric The source electrode of MOS device, drain electrode and substrate short circuit.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 1, It is characterized in that, described method also includes:

Use the preparation technology identical with the drain electrode of described asymmetric MOS device to be measured, preparation The source electrode of described symmetrical MOS device and drain electrode, so that the grid source of this symmetry MOS device Electric capacity, gate leakage capacitance are all equal with the gate leakage capacitance of described asymmetric MOS device to be measured；

Use the gate groove electric capacity measuring the described symmetrical MOS device of technique acquisition, and according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Obtain the described symmetrical gate-source capacitance of MOS device, gate leakage capacitance, and then obtain described to be measured The gate leakage capacitance of asymmetric MOS device；

Use the gate groove electric capacity measuring the technique described asymmetric MOS device to be measured of acquisition, and Gate groove electric capacity, gate-source capacitance and gate leakage capacitance according to this asymmetric MOS device to be measured it Between functional relationship, obtain the gate-source capacitance of described asymmetric MOS device to be measured.

7. the method obtaining asymmetric unit grid stack capacitor, it is characterised in that described Method includes:

One substrate is provided；

Synchronize the most at least to prepare an asymmetric MOS device to be measured and a symmetry MOS device；

Continuously form described asymmetric MOS device to be measured, described symmetrical MOS device each Grid；

Measure the gate groove electric capacity of described symmetrical MOS device, and according to this symmetry MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part, it is described right to calculate Claim the gate-source capacitance of MOS device, gate leakage capacitance, and then obtain described asymmetric MOS to be measured The gate-source capacitance of device；

Measure the gate groove electric capacity of described asymmetric MOS device to be measured, and to be measured non-according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Calculate the gate leakage capacitance of described asymmetric MOS device to be measured；

Wherein, the source doping region of described symmetrical expression MOS device, drain doping region are all and institute The source doping region stating asymmetric MOS device to be measured is formed in same example doping operation, So that the gate-source capacitance of described symmetrical expression MOS device, gate leakage capacitance are all asymmetric with described The gate-source capacitance of formula MOS device is equal.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 7, It is characterized in that, the gate groove electric capacity of described symmetrical MOS device and its gate-source capacitance, grid leak Functional relationship between electric capacity includes below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

Q_overlap.d=Q_overlap.s；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})];$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid And the voltage between body district, W_activeRepresenting the width of active area, CGSO represents that grid is to source region Each raceway groove unit length on overlap capacitance, V_gsRepresent the voltage between grid source electrode, CGSL represents the grid overlap capacitance to each active area unit length of source region, V_gs.overlap Representing the superimposed voltage between grid source electrode, CKAPPAS represents that source side is based on overlap capacitance and is Number.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 7, It is characterized in that, the gate groove electric capacity of described asymmetric MOS device to be measured and its gate-source capacitance, Functional relationship between gate leakage capacitance includes below equation:

Q_overlap.g=-(Q_overlap.d+Q_overlap.s+(CGBO*L_active)*V_gb)；

$\frac{Q_{\mathrm{overlap}.s}}{W_{\mathrm{active}}}=\mathrm{CGSO}*V_{\mathrm{gs}}+\mathrm{CGSL}[V_{\mathrm{gs}}-V_{\mathrm{gs}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAS}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gs}.\mathrm{overlap}}}{\mathrm{CKAPPAS}}})];$

$\frac{Q_{\mathrm{overlap}.d}}{W_{\mathrm{active}}}=\mathrm{CGDO}*V_{\mathrm{gd}}+\mathrm{CGDL}[V_{\mathrm{gd}}-V_{\mathrm{gd}.\mathrm{overlap}}-\frac{\mathrm{CKAPPAD}}{2}(-1+\sqrt{1-\frac{{4V}_{\mathrm{gd}.\mathrm{overlap}}}{\mathrm{CKAPPAD}}})]$

Wherein, Q_overlap.gRepresent the stacked electricity of gate electrode side, Q_overlap.dRepresent the stacked of drain side Electricity, Q_overlap.sRepresenting the stacked electricity of source class side, CGBO represents each to body district of grid Overlap capacitance in raceway groove unit length, L_activeRepresent the length of active area, V_gbRepresent grid And the voltage between body district, W_activeRepresenting the width of active area, CGDO represents that grid is to drain region Each raceway groove unit length on overlap capacitance, V_gdRepresent the voltage between grid leak pole, CGDL represents the grid overlap capacitance to each active area unit length in drain region, V_gd.overlap Representing the superimposed voltage between grid leak pole, CKAPPAD represents that drain side is based on overlap capacitance Coefficient.

The method of acquisition asymmetric unit grid stack capacitor the most according to claim 7, It is characterized in that, described method also includes:

The breadth length ratio of the raceway groove according to described symmetrical MOS device is entered with this symmetry MOS device When row measures technique, the ratio between the temperature value of local environment determines described symmetrical MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part；

The breadth length ratio of the raceway groove according to described asymmetric MOS device to be measured is to be measured asymmetric with this When MOS device carries out measuring technique, the ratio between the temperature value of local environment determines described Letter between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of asymmetric MOS device to be measured Number relation.

The method of 11. acquisition asymmetric unit grid stack capacitors according to claim 7, It is characterized in that, described method also includes:

When described symmetrical MOS device is carried out measuring technique, by this symmetry MOS device Source electrode, drain electrode and substrate short circuit；

When described asymmetric MOS device to be measured carries out measuring technique, this is to be measured asymmetric The source electrode of MOS device, drain electrode and substrate short circuit.

The method of 12. acquisition asymmetric unit grid stack capacitors according to claim 7, It is characterized in that, described method also includes:

The source doping region of described symmetrical expression MOS device, drain doping region are all to be measured with described The drain doping region of asymmetric MOS device is formed in same example doping operation, so that The gate-source capacitance of described symmetrical expression MOS device, gate leakage capacitance all with described asymmetric MOS The gate leakage capacitance of device is equal；

Measure the gate groove electric capacity of described symmetrical MOS device, and according to this symmetry MOS device Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of part, it is described right to calculate Claim the gate-source capacitance of MOS device, gate leakage capacitance, and then obtain described asymmetric MOS to be measured The gate leakage capacitance of device；

Measure the gate groove electric capacity of described asymmetric MOS device to be measured, and to be measured non-according to this Functional relationship between gate groove electric capacity, gate-source capacitance and the gate leakage capacitance of symmetrical MOS device, Calculate the gate-source capacitance of described asymmetric MOS device to be measured.

The method of 13. acquisition asymmetric unit grid stack capacitors according to claim 7, It is characterized in that, described method also includes:

The source doping region of described symmetrical expression MOS device and the dopant ion of drain doping region thereof Type, concentration, area, shape all with the source dopant of described asymmetric MOS device to be measured District is identical.