CN106158615A - A kind of ozone is passivated the method that high-k gate dielectric is improved at high k/Ge interface simultaneously - Google Patents
A kind of ozone is passivated the method that high-k gate dielectric is improved at high k/Ge interface simultaneously Download PDFInfo
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- CN106158615A CN106158615A CN201510202692.2A CN201510202692A CN106158615A CN 106158615 A CN106158615 A CN 106158615A CN 201510202692 A CN201510202692 A CN 201510202692A CN 106158615 A CN106158615 A CN 106158615A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
Abstract
The present invention provides a kind of ozone be passivated high k/Ge interface and improve the manufacture method of high-k gate dielectric, and the method comprises the following steps: provide a substrate, and wherein said substrate is Ge substrate or the wafer containing Ge film surface；The growth of described substrate alternately high-k gate dielectric is processed with ozone, forms high k/GeO over the substratex/ Ge rhythmic structure of the fence；Described high-k gate dielectric is carried out cryogenic oxygen annealing, to strengthen described high K medium quality.Ozone is utilized to be passivated high k/Ge interface and the method improving high-k gate dielectric.One layer of very thin GeO is not only obtained on Ge surfacexLayer, and then reduce EOT, improve high k/Ge interface quality, play good high k/Ge interface passivation effect.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly relate to a kind of ozone and be passivated high k/Ge interface and improvement
The manufacture method of high-k gate dielectric.
Background technology
Semiconductor technology as the core of information industry and basis, be weigh a national science technological progress and
The important symbol of overall national strength.In more than 40 year of past, silica-based integrated technology follows Moore's Law by contracting
The characteristic size of gadget improves the operating rate of device, increases integrated level and reduce cost, silica-based
The characteristic size of cmos device is narrowed down to nanoscale by micro-meter scale.But when the grid length of device reduces
To below 90nm, the thickness of gate medium (silicon dioxide) has gradually decreased to close to 1nm, and OFF state is leaked electricity
The physics limits such as increase, power dissipation density increase, mobil-ity degradation make device performance degradation, the silica-based micro-electricity of tradition
Sub-integrated technology starts to face the double challenge from physics Yu technical elements.
For in terms of material, using high mobility material to substitute traditional silicon material as backing material will be half
The important development direction of conductor integrated technology.Because hole mobility 1900cm of germanium (Ge)2/ V s and electricity
Transport factor 3900cm2/ V s is significantly higher than silicon materials, additionally, germanium (Ge) has less energy gap,
So the cut-in voltage of germanium device is less than silicon.Although germanium is the direction of future microelectronics industry development, but
Still need to overcome some obstacles when reducing the EOT and exploitation Ge-based MOSFETs of Ge-based MOS,
One layer of very thin GeO is wherein formed on the surface of Ge2Passivation layer is considered as that a kind of promising mode goes shape
Become superior high k/Ge interface.But GeO2Character is unstable, exposes and is prone to water reaction in atmosphere, this
Thermal desorption is started when external temperature is more than 400 DEG C.Traditional thermal oxide that utilizes forms GeO2, although can obtain
To excellent interface, but oxidizing temperature requires high (more than 500 DEG C), the GeO generated in addition2Thickness is thicker,
It is unfavorable for the reduction of EOT.It addition, for obtaining high-quality high k/GeOx/ Ge gate stack, not only needs excellent
Interface more, the most also should obtain high-quality gate medium.So how prepare high-quality high k/GeOx/Ge
Gate stack is most important to the development of Ge-based MOSFETs.
Summary of the invention
It is an object of the invention to provide one utilizes the high k/Ge interface of ozone passivation to improve high-k gate dielectric simultaneously
Manufacture method, by control cycle period number of times, control ozone oxidation time, regulate and control each circulating cycle
The thickness of phase deposition high-k gate dielectric, can obtain high-quality high k/Ge interface, improve gate medium matter simultaneously
Amount, reduces grid leak electricity further.It is possible not only to while obtaining superior interface control to generate GeOxThickness,
And then reduce EOT, and high-k gate dielectric quality can be improved further, thus reduce grid leakage further
Electricity, thus improve device electrology characteristic.
An embodiment according to an aspect of the present invention, it is provided that one utilizes ozone to be passivated high k/Ge interface
Improve the manufacture method of high-k gate dielectric simultaneously, including: providing a substrate, wherein said substrate is Ge
(100), the multiple wafer containing Ge film surface such as (110), (111) and silica-based epitaxial Germanium；Utilize high k
Gate medium growth processes circular round-robin manner alternately with ozone, forms height over the substrate
k/GeOx/ Ge rhythmic structure of the fence；Utilize quick anneal oven that described high-k gate dielectric is carried out cryogenic oxygen annealing,
Further enhance described high K medium quality.
Alternatively, the method also includes: select Ge substrate acetone ethanol organic washing, removes Ge substrate table
The natural oxide in face, transfers it in atomic layer deposition system cavity.
Alternatively, utilize high-k gate dielectric growth further with the circular round-robin manner that ozone processes alternately
Including:
Ge sheet after cleaning is transferred quickly in atomic layer deposition system cavity deposit a thin layer at substrate surface
High-k gate dielectric；
Post-depositional sample is carried out ozone in-situ process；
The above-mentioned two step operations of loop cycle.
Alternatively, the loop cycle number of described circular round-robin manner can be according to concrete grid medium thickness and equivalence oxygen
Compound thickness requirement regulates and controls.
Alternatively, in described circular round-robin manner, in each repetitive cycling cycle, the high K medium thickness of deposition can
Changing as requested, its excursion is 0.1nm-1.5nm.
Alternatively, the high-k gate dielectric thickness deposited in the first cycle period in described circular round-robin manner is with smelly
The time that oxygen processes can regulate and control the most accurately, thus can obtain that thickness is controlled and thickness is less than 1nm
GeOxThin film, and there is good interface passivation effect.
Alternatively, in described circular round-robin manner, in each cycle period, ozone treatment time can be according to each week
Phase deposits high K thin film thickness and changes and change, and its excursion is 1min-60min.
Alternatively, described high-k gate dielectric can be Y2O3, Al2O3, HfO2And La2O3In one,
Multi-element compounds that is multiple and that form.
Alternatively, described cryogenic oxygen annealing temperature is 350-400 DEG C, and annealing time is 1min-60min.
Alternatively, described cryogenic oxygen annealing pressure is 1 normal atmosphere.
Compared with prior art, the invention have the advantages that
Ozone is utilized to be passivated high k/Ge interface and the method improving high-k gate dielectric.Not only obtain on Ge surface
One layer of very thin GeOxLayer, and then reduce EOT, improve high k/Ge interface quality, play good height
K/Ge interface passivation effect.Simultaneously as after often walking high-k gate dielectric deposition, the high k grid of deposition are situated between
Matter carries out the ozone of certain time and processes, thus improves high-k gate dielectric quality further, reduces dielectric leakage,
Improve device electrology characteristic.Additionally, the method processes whole process all at atomic layer from dielectric deposition to ozone
Depositing system (ALD) carries out in-situ treatment.Present invention achieves Ge base MOS device obtains simultaneously excellent
Good interface and high-quality high-k gate dielectric, it is adaptable to Ge base mos capacitance, MOSFETs and other contain
The device of Ge base gate stack.The ozone that the present invention provides is passivated high k/Ge interface and improves high-k gate dielectric simultaneously
Method, have simple to operate, easy to use, avoid polluting, passivation effect and high-k gate dielectric quality are improved
The advantage such as substantially.
Accompanying drawing explanation
The detailed description that non-limiting example is made made with reference to the following drawings by reading, this
Bright other features, objects and advantages will become more apparent upon:
Fig. 1 is to be passivated high k/Ge interface according to the employing ozone of the embodiment of the present invention to improve high-k gate dielectric simultaneously
Method flow block diagram；
Fig. 2 is to be passivated high k/Ge interface according to the employing ozone of the embodiment of the present invention to improve high-k gate dielectric simultaneously
Method structural representation；
Fig. 3 is to be passivated high k/Ge interface according to the employing ozone of the embodiment of the present invention to improve high-k gate dielectric simultaneously
The mos gate laminated construction schematic diagram prepared of method.
Fig. 4 a-4d is to be passivated high k/Ge interface according to the employing ozone of the embodiment of the present invention and improve high k grid Jie
MOSFETs process flow diagram prepared by the method for matter.
In accompanying drawing, same or analogous reference represents same or analogous parts.
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, wherein
The most same or similar label represents same or similar element or has same or like function
Element.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining the present invention, and
It is not construed as limiting the claims.
Following disclosure provides many different embodiments or example for realizing the different structure of the present invention.
In order to simplify disclosure of the invention, hereinafter parts and setting to specific examples are described.Certainly,
They are the most merely illustrative, and are not intended to limit the present invention.Additionally, the present invention can be in different examples
Repeat reference numerals and/or letter in son.This repetition is for purposes of simplicity and clarity, and itself is not
The relation between various embodiment and/or setting is discussed in instruction.Additionally, the various spies that the invention provides
Fixed technique and the example of material, but those of ordinary skill in the art it can be appreciated that other techniques can
Being applied to property and/or the use of other materials.It addition, fisrt feature described below second feature it " on "
Structure can include that the first and second features are formed as the embodiment directly contacted, it is also possible to include additionally
Feature be formed at the embodiment between the first and second features, such first and second features are not likely to be
Directly contact.It should be noted that, parts illustrated in the accompanying drawings are not drawn necessarily to scale.The present invention saves
Omit the description to known assemblies and treatment technology and process to avoid being unnecessarily limiting the present invention.
Fig. 1 is that the ozone that utilizes according to the present invention is passivated high k/Ge interface and improves the manufacturer of high-k gate dielectric
The flow chart of method, Fig. 2 is that high k grid Jie is improved at the high k/Ge interface of employing ozone passivation according to the present invention simultaneously
The method structural representation of matter, Fig. 3 is that the high k/Ge interface of employing ozone passivation according to the present invention is improved simultaneously
Mos gate laminated construction schematic diagram prepared by the method for high-k gate dielectric.Below, will be in conjunction with Fig. 2 to Fig. 3
It is passivated high k/Ge interface to Fig. 1 utilizes ozone and improves the manufacture method of high-k gate dielectric and specifically retouch
State.It should be noted that the accompanying drawing of the embodiment of the present invention is merely to the purpose of signal, therefore not having must
Drawn to scale.
With reference to Fig. 1 and Fig. 2, in step S101, first provide a substrate 201.Wherein said
Substrate is that Ge (100), (110), (111) and silica-based epitaxial Germanium etc. are multiple containing Ge film surface
Wafer.
In the present embodiment, described substrate 201 be Ge substrate (such as Ge (100), (110),
(111) wafer).(such as P type substrate or N-type substrate) is required according to design known in the art,
Described substrate 201 can include various doping configuration.In other embodiments, described substrate 201 also may be used
Think the multiple wafers containing Ge film surface such as silica-based epitaxial Germanium.
Preferably, high k/GeO is being formedxBefore/Ge rhythmic structure of the fence, acetone ethanol can be selected organic clearly
Wash, remove the natural oxide of substrate surface, transfer it in atomic layer deposition system cavity.Tool
Body, first by Ge substrate 201 ultrasonic cleaning in acetone and ethanol solution, then utilize the HCl of dilution
The natural oxide on Ge substrate 201 surface is removed in rinsing, then uses N2Dry up.Thus obtain clean surface.
In step s 102, high-k gate dielectric growth is utilized to process loop cycle side alternately with ozone
Formula, forms high k/GeO over the substratex/ Ge rhythmic structure of the fence.
Concrete, the substrate after first cleaning is transferred quickly in atomic layer deposition system cavity at substrate surface
Deposition a thin layer high-k gate dielectric, described high-k gate dielectric can be HfO2、HfSiO、HfSiON、HfTaO、
HfTiO、HfZrO、Al2O3、La2O3、ZrO2, one in LaAlO or a combination thereof.Then to heavy
Sample after Ji carries out ozone in-situ process.High-k gate dielectric to deposition carries out the ozone process of certain time,
High-k gate dielectric quality can be improved further, reduce dielectric leakage, improve device electrology characteristic.Wherein,
From dielectric deposition to ozone, process whole process all in atomic layer deposition system (ALD), carry out in-situ treatment.?
In the present embodiment, as in figure 2 it is shown, ozone treating process 203, the time is 10min.Then Fig. 1 step is pressed
S102a-S102c repetition period cyclic deposition high-k gate dielectric 202 and ozone process 203 steps, thus obtain
Set grid medium thickness.In wherein said circular round-robin manner, in each cycle period, ozone treatment time can
Depositing the change of high K thin film thickness according to each cycle and change, typically, its excursion is 1min-60min.
In wherein said circular round-robin manner, in each repetitive cycling cycle, the high K medium thickness of deposition can be as requested
Changing, typically, its excursion is 0.1nm-1.5nm.In the present embodiment, as in figure 2 it is shown, weigh
Step process 202 in multiple loop cycle, the high-k gate dielectric Al of deposition2O3Thickness is 0.5nm.Wherein said
The loop cycle number of circular round-robin manner can require to carry out according to concrete grid medium thickness and equivalent oxide thickness
Regulation and control.In the present embodiment, as it is shown on figure 3, according to repetitive cycling 202 shown in Fig. 2,203 process step
In 10 cycles, on Ge substrate 301, finally obtain the thickness GeO less than 1nmxPassivation layer 302 is used for changing
Kind interface, obtains high-quality high-k gate dielectric Al2O3Gate medium 303, thickness is 5nm.
After the above step is finished, in step s 103, utilize quick anneal oven to described high-k gate dielectric
Carry out cryogenic oxygen annealing, further enhance described high K medium quality.Typically, described cryogenic oxygen moves back
Pressure ignition is 1 normal atmosphere.Typically, described cryogenic oxygen annealing temperature is 350-400 DEG C, annealing
Time is 1min-60min.In the present embodiment, step S103 as shown in Figure 1, gate medium after deposition is entered
Row cryogenic oxygen annealing 30min, further enhances mass of medium.
With reference to shown in Fig. 4, present invention also offers and utilize the high k/Ge interface of ozone passivation to improve high k grid simultaneously
The method of medium makes the manufacture method of Ge-based MOSFETs and includes:
Identical with first embodiment, step S101 is first carried out, first a substrate 401 is provided.Wherein institute
Stating substrate is that Ge (100), (110), (111) and silica-based epitaxial Germanium etc. are multiple containing Ge film surface
Wafer.Preferably, high k/GeO is being formedxBefore/Ge rhythmic structure of the fence, acetone ethanol can be selected to have
Machine cleans, and removes the natural oxide of substrate surface, transfers it in atomic layer deposition system cavity.
Specific implementation sees step S101 of above-mentioned first embodiment, and identical part no longer repeats.
Then, performing step S102a-S102c uses high-k gate dielectric growth to process week alternately with ozone
Phase endless form, forms high k/GeOx/ Ge rhythmic structure of the fence, i.e. 402GeOx, 403Al2O3, structure is such as
Shown in Fig. 4 a.
Then on described gate dielectric layer 403 formed metal gates 404, can pass through depositing Ti, Au,
TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax
In one or a combination thereof formed.
In the present embodiment, depositing Ti/Au gate electrode 404 on described gate medium, such as Fig. 4 b.
Then, forming source-drain area, source/drain region 406 can be by implanting p-type or N in substrate 401
Type alloy or impurity and formed, such as, for PMOS, source/drain region 406 can be p-type
The Ge of doping, for NMOS, source/drain region 406 can be the Ge of N doping.Source/drain region 406
Can be formed by the method including photoetching, ion implanting, diffusion and/or other appropriate process.Then, right
Described semiconductor structure is annealed, and to activate the doping in source/drain region 406, annealing can use and include
Other suitable methods such as short annealing, spike annealing are formed.
In the present embodiment, Si is deposited at source-drain area3N4Layer 405, as ion implanting barrier layer, carries out n
Type or p-type ion implanting also activate, and form heavily doped region 406, as illustrated in fig. 4 c.
Finally, such as Fig. 4 d, Si is removed3N4Layer 405, makes source-drain electrode 407, so far Ge-based MOSFETs
Preparation completes.The Ge base MOS device obtained through flow operations step process shown in Fig. 1 is at high k/Ge interface
Define one layer of very thin GeOxInterposed layer.So, substantially improve interface quality, reduce interfacial state
Density.Meanwhile, utilize the method described in this example to obtain higher-quality high-k gate dielectric, change further
It is apt to electric leakage of the grid characteristic.
Wherein, structure composition, material and the forming method etc. of each several part in embodiment each to semiconductor structure
All can with aforesaid semiconductor Structure formation method embodiment described in identical, repeat no more.Although about
Example embodiment and advantage thereof are described in detail, it should be understood that without departing from the spirit of the present invention and appended
In the case of the protection domain that claim limits, these embodiments can be carried out various change, replacement
And amendment.For other examples, those of ordinary skill in the art is it should be readily appreciated that keeping the present invention
While in protection domain, the order of processing step can change.
Additionally, the range of application of the present invention be not limited to the specific embodiment described in description technique,
Mechanism, manufacture, material composition, means, method and step.From the disclosure, as this
The those of ordinary skill in field will readily appreciate that, at present having existed or will develop later
Technique, mechanism, manufacture, material composition, means, method or step, wherein they perform and the present invention
The result that the function that is substantially the same of corresponding embodiment described or acquisition are substantially the same, can according to the present invention
So that they are applied.Therefore, claims of the present invention are intended to these technique, mechanism, system
Make, material composition, means, method or step are included in its protection domain.
Claims (10)
1. ozone is passivated high k/Ge interface and improves a manufacture method for high-k gate dielectric, and the method includes
Following steps:
Thering is provided a substrate, wherein said substrate is Ge substrate or the wafer containing Ge film surface；
The growth of described substrate alternately high-k gate dielectric is processed with ozone, forms height over the substrate
k/GeOx/ Ge rhythmic structure of the fence；
Described high-k gate dielectric is carried out cryogenic oxygen annealing, to strengthen described high K medium quality.
Manufacture method the most according to claim 1, is situated between at described k grid the highest to described substrate
Also comprise the steps: before the step that matter growth and ozone process
Remove the natural oxide of described substrate surface.
Manufacture method the most according to claim 1, wherein said k grid the highest to described substrate
Dielectric growth processes with ozone and farther includes following steps:
Substrate surface deposition a thin layer high-k gate dielectric after cleaning；
Post-depositional sample is carried out ozone in-situ process；
The above-mentioned two step operations of loop cycle.
4. according to the manufacture method described in any one in claim 1-3, wherein said loop cycle side
The loop cycle number of formula can require with equivalent oxide thickness according to concrete grid medium thickness.
5. according to the manufacture method described in described in any one in claim 1-4, wherein said cycle
In endless form, in each repetitive cycling cycle, the high K medium thickness excursion of deposition is 0.1nm-1.5nm.
6. according to the manufacture method described in described in any one in claim 1-5, wherein said cycle
The time in endless form processed the high-k gate dielectric thickness of deposition in the first cycle period and ozone is carried out more
Regulation and control, to obtain the thickness GeO less than 1nmxThin film.
7. according to the manufacture method described in described in any one in claim 1-6, wherein said cycle
In endless form, in each cycle period, ozone treatment time can change according to the high K thin film thickness of deposition of each cycle
Becoming and change, its excursion is 1min-60min.
8. according to the manufacture method described in described in any one in claim 1-7, wherein said high k
Gate medium can be Y2O3, Al2O3, HfO2And La2O3In one, multiple and composition polynary chemical combination
Thing.
Manufacture method the most according to claim 1, wherein said cryogenic oxygen annealing temperature is
350-400 DEG C, annealing time is 1min-60min.
Manufacture method the most according to claim 1, wherein said cryogenic oxygen annealing pressure is 1
Normal atmosphere.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601587A (en) * | 2016-11-29 | 2017-04-26 | 东莞市广信知识产权服务有限公司 | Ge base MOS device structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601587A (en) * | 2016-11-29 | 2017-04-26 | 东莞市广信知识产权服务有限公司 | Ge base MOS device structure |
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Application publication date: 20161123 |