CN101924034A

CN101924034A - Method for adjusting threshold voltage of high k gate medium and metal gate structured pMOSFET (p type Metal-Oxide -Semiconductor Field Effect Transistor) apparatus

Info

Publication number: CN101924034A
Application number: CN2009100873469A
Authority: CN
Inventors: 王文武; 陈世杰; 陈大鹏
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2009-06-17
Filing date: 2009-06-17
Publication date: 2010-12-22

Abstract

The invention discloses a method for adjusting threshold voltage of a high k gate medium and a metal gate structured pMOSFET (p type Metal-Oxide -Semiconductor Field Effect Transistor) apparatus, which comprises the following steps of: growing a hafnium-based or lanthanum-based high k gate medium layer containing Al element on a SiO2 interface layer after growth of the SiO2 interface layer, or doping a certain quantity of Al element in a metal gate electrode; and using a thermal annealing process so that the Al element moves to an Si/SiO2 interface through thermal diffusion to form a certain quantity of negative charges. Therefore, the purposes of adjusting the flat band voltage of the high k gate medium and the metal gate structured pMOSFET apparatus and adjusting the threshold voltage of the apparatus are achieved.

Description

Regulate the method for high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage

Technical field

The effective work function that the present invention relates to high-k gate dielectric and metal-gate structures MOSFET device is regulated and threshold voltage control technology field, relates in particular to a kind of method of regulating high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage.

Background technology

Since first integrated circuit in 1958 came out, the development of microelectric technique was very fast, has become the basis of whole information industry.The core of microelectric technique-CMOS technology (invention in 1963) has become the support technology in the modern electronic product.In decades, logic chip manufacturer adopts silicon dioxide (SiO always ₂) as gate medium and heavily doped polysilicon (poly-Si) as gate material.This combination lasts till 90 nm technology generation always.Along with constantly dwindling of characteristic size, the SiO in the CMOS transistor ₂Gate dielectric has closed on the limit.For example, when 65 nanometer technologies, SiO ₂The thickness of grid has been reduced to 1.2 nanometers, is about 5 silicon atom layer thickness, if continue to dwindle, leakage current and power consumption will sharply increase again.What simultaneously, the doped with boron atom diffusion that is caused by polygate electrodes, depletion of polysilicon effect (poly-depletion) and too high problems such as gate resistance also became is more and more serious.For 32 nanometers and following each technology generation, sharply problems such as leakage current that increases and power consumption with anxious treat new material, new technology, and the exploitation of new device structure solve.

Each main semiconductor company in the international coverage has all taken up towards the exploitation of " high k/ metal gate " technology of 32 nanometers and following technology generation at present.According to Intel, adopt high-k gate dielectric material after, it is original 1/10th that its leakage current is reduced to, but the thing followed is the threshold voltage control problem of CMOSFET device.Because the CMOS arts demand possesses nMOSFET and pOMSFET device simultaneously, institute thinks optimized device performance to greatest extent, require the threshold voltage of nMOS and pMOS device keeping also will reducing the numerical value of threshold voltage as much as possible under the absolute value prerequisite about equally.Utilize suitable metal gate material to regulate effective work function, and then the reduction device threshold voltage is the most direct, feasible at present and effective method.

Discover, when Al diffuses to gate electrode/high-k gate dielectric/SiO ₂The Si/SiO of/n-Si structure devices ₂In the time of at the interface, can the flat band voltage of whole pMOSFET gate capacitance be produced a very large impact, the phenomenon of flat band voltage occur to the forward voltage skew.Utilize this phenomenon, can reach by introducing Al to Si/SiO ₂At the interface, the purpose to flat band voltage is adjusted finally plays the adjustment threshold voltage, improves the effect of device performance.It should be noted that as a rule, when metallic element diffuses to Si/SiO ₂In the time of at the interface, can form the electric charge or the defective of some at this place, this can produce bigger scattering to channel carrier, and then causes carrier mobility to reduce, and finds by a large amount of experiments, at Si/SiO ₂Because the negative electrical charge that the Al diffusion causes is very little to the hole mobility influence of pMOSFET device, what can be similar to ignores at the interface.

Summary of the invention

(1) technical problem that will solve

In view of this, main purpose of the present invention is to provide a kind of method of regulating high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage, to realize the adjusting to high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage.

(2) technical scheme

For achieving the above object, the invention provides a kind of method of regulating high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage, this method comprises:

At SiO ₂After boundary layer has been grown, at SiO ₂Growth comprises the hafnium base or the lanthanum base high-k gate dielectric layer of Al element on the boundary layer, perhaps mixes the Al of some in metal gate electrode;

Utilize thermal anneal process, make the Al element move to Si/SiO by thermal diffusion ₂At the interface, form the negative electrical charge of some, thereby reach the flat band voltage of regulating high-k gate dielectric and metal-gate structures pMOSFET device, the purpose of regulating threshold voltage of element.

In the such scheme, described at SiO ₂The boundary layer growth comprises the hafnium base or the lanthanum base high-k gate dielectric layer of Al element, is to adopt the method for physical vapour deposition (PVD) or chemical vapour deposition (CVD) to realize.

In the such scheme, described at SiO ₂Hafnium base or lanthanum base high-k gate dielectric layer that the boundary layer growth comprises the Al element utilize thermal anneal process afterwards, are to utilize rapid thermal anneal process RTA.

In the such scheme, the described Al that mixes some in metal gate electrode utilizes thermal anneal process afterwards, is to utilize PMA (post metallization annealing) thermal anneal process.

(3) beneficial effect

As can be seen, the present invention has following beneficial effect from technique scheme:

1, utilize the present invention, can regulate the flat band voltage of high-k gate dielectric and metal-gate structures pMOSFET device effectively, and then the threshold voltage characteristic of control device.

2, utilize the present invention, can under the situation that does not increase too much technological process, reach the purpose of optimizing pMOSFET device electrology characteristic.

Description of drawings

Fig. 1 is the method flow diagram of adjusting high-k gate dielectric provided by the invention and metal-gate structures pMOSFET device threshold voltage;

Fig. 2 is the thick SiO of growth 0.5nm on the silicon substrate of carrying out the PROCESS FOR TREATMENT in early stage ₂The schematic diagram of boundary layer;

Fig. 3 is at SiO ₂On the boundary layer with the thick Hf of technique for atomic layer deposition growth one deck 3nm _xAl _1-xThe schematic diagram of O (0＜x＜1) film;

Fig. 4 carries out 800 ℃, the schematic diagram of the PDA annealing in process of 10s to this structure;

Fig. 5 is at SiO ₂Use the thick HfO of ALD technology growth one deck 3nm on the boundary layer ₂The schematic diagram of film;

Fig. 6 is at HfO ₂The schematic diagram of the TiAlN metal gate electrode film that method deposit one deck 30nm of usefulness sputter is thick on the film;

Fig. 7 carries out 800 ℃, the schematic diagram of the PMA annealing in process of 10s in nitrogen atmosphere.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

The invention provides a kind of passing through at gate electrode/high-k gate dielectric/SiO ₂The Si/SiO of/n-Si structure devices ₂Introduce the method that units such as Al usually regulate high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage at the interface.This method is at SiO ₂After boundary layer has been grown, utilize method (MOCVD or the ALD) growth of physical vapor deposition (PVD) or chemical vapour deposition (CVD) to comprise the hafnium base or the lanthanum base high-k gate dielectric layer of Al or other elements, utilize rapid thermal anneal process (RTA) then, make Al or other elements in the high-k gate dielectric layer move to Si/SiO by thermal diffusion ₂At the interface, and the negative electrical charge of formation some, thereby reach the flat band voltage of regulating high-k gate dielectric and metal-gate structures pMOSFET device, and then the purpose of regulating threshold voltage of element.In addition, Si/SiO ₂The diffusion of Al atom also can be by mixing the Al of some in metal gate electrode at the interface, and by PMA (post metalllization annealing) thermal anneal process, allows the Al in the metal gate diffuse to Si/SiO ₂The side at place realizes.

As shown in Figure 1, Fig. 1 is the method flow diagram of adjusting high-k gate dielectric provided by the invention and metal-gate structures pMOSFET device threshold voltage, and this method comprises:

Step 1: at SiO ₂Boundary layer has been grown afterwards at SiO ₂Hafnium base or lanthanum base high-k gate dielectric layer that the boundary layer growth comprises the Al element perhaps mix the Al of some in metal gate electrode;

Step 2: utilize thermal anneal process, make the Al element move to Si/SiO by thermal diffusion ₂At the interface, form the negative electrical charge of some, thereby reach the flat band voltage of regulating high-k gate dielectric and metal-gate structures pMOSFET device, the purpose of regulating threshold voltage of element.

Described in the above-mentioned steps 1 at SiO ₂The boundary layer growth comprises the hafnium base or the lanthanum base high-k gate dielectric layer of Al element, is to adopt the method for physical vapour deposition (PVD) or chemical vapour deposition (CVD) to realize.

Described in the above-mentioned steps 2 at SiO ₂Hafnium base or lanthanum base high-k gate dielectric layer that the boundary layer growth comprises the Al element utilize thermal anneal process afterwards, are to utilize rapid thermal anneal process RTA.

The Al that mixes some described in the above-mentioned steps 2 in metal gate electrode utilizes thermal anneal process afterwards, is to utilize PMA (post metal annealing) thermal anneal process.

Embodiment 1:

As shown in Figure 2, the thick SiO of growth 0.5nm on the silicon substrate of carrying out the PROCESS FOR TREATMENT in early stage ₂Boundary layer.

As shown in Figure 3, at SiO ₂Use the thick Hf of technique for atomic layer deposition (Atomic LayerDeposition/ALD) growth one deck 3nm on the boundary layer _xAl _1-xO (0＜x＜1) film.

As shown in Figure 4, this structure is carried out 800 ℃, PDA (post depositionannealing) annealing in process of 10s.

Embodiment 2:

As shown in Figure 5, at SiO ₂Use the thick HfO of ALD technology growth one deck 3nm on the boundary layer ₂Film.

As shown in Figure 6, at HfO ₂Use the thick TiAlN metal gate electrode film of method deposit one deck 30nm of sputter on the film.

As shown in Figure 7, in nitrogen atmosphere, this structure is carried out 800 ℃, the PMA annealing in process of 10s.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. method of regulating high-k gate dielectric and metal-gate structures pMOSFET device threshold voltage is characterized in that this method comprises:

2. the method for adjusting high-k gate dielectric according to claim 1 and metal-gate structures pMOSFET device threshold voltage is characterized in that, and is described at SiO ₂The boundary layer growth comprises the hafnium base or the lanthanum base high-k gate dielectric layer of Al element, is to adopt the method for physical vapour deposition (PVD) or chemical vapour deposition (CVD) to realize.

3. the method for adjusting high-k gate dielectric according to claim 1 and metal-gate structures pMOSFET device threshold voltage is characterized in that, and is described at SiO ₂Hafnium base or lanthanum base high-k gate dielectric layer that the boundary layer growth comprises the Al element utilize thermal anneal process afterwards, are to utilize rapid thermal anneal process RTA.

4. the method for adjusting high-k gate dielectric according to claim 1 and metal-gate structures pMOSFET device threshold voltage is characterized in that, the described Al that mixes some in metal gate electrode utilizes thermal anneal process afterwards, is to utilize the PMA thermal anneal process.