CN106158032A - For the erasing of eeprom memory and write circuit and method thereof - Google Patents
For the erasing of eeprom memory and write circuit and method thereof Download PDFInfo
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- CN106158032A CN106158032A CN201610501884.8A CN201610501884A CN106158032A CN 106158032 A CN106158032 A CN 106158032A CN 201610501884 A CN201610501884 A CN 201610501884A CN 106158032 A CN106158032 A CN 106158032A
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- Prior art keywords
- page
- data
- write
- erasing
- byte
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Abstract
The present invention discloses a kind of erasing in EEPROM and write circuit and method thereof, including: byte address decoder in time-sequence control mode, memory module, input/output module, caching of page module, page address decoder, page.Before present invention data in erasing eeprom memory, the page data being wiped free of is read in page buffer.Caching of page data can write " 0 " can also one writing, the data needing programming can be whole page, it is also possible to is 1 byte to an any byte between the byte contained by one page.The present invention overcome EEPROM is write that data are dumb, can not use in some application scenario, must whole page to write the memory space utilization rate caused low and write the shortcoming that data speed is slow, with the addition of byte address decoder in page, realizing input data flexible to EEPROM, the suitability is wide.Can only update small part data in one page, improve memory space utilization rate, add the speed of fast write data.
Description
Technical field
The present invention relates to control circuit field, particularly relate to a kind of erasing for eeprom memory and write circuit and
Its method.
Background technology
Existing for EEPROM erasing and write circuit, the mode of data is write in eeprom memory erasing data and programming
The pattern write for the erasing of whole page and whole page.The data being programmed into page corresponding to eeprom memory by whole page must be a whole number of pages
According to, and can not be 1 byte to an any byte between the byte contained by one page.General caching of page data can only one writing or
Can only write " 0 ", the shortcoming of this circuit structure is:
1, EEPROM is write data dumb, some application scenario can not be used.
2, EEPROM writes data must be that whole page is write, and EEPROM memory space utilization rate is low.
3, to having only to update the application scenario of less data, the speed writing data is slow.
Summary of the invention
For the deficiencies in the prior art, the present invention propose kind for the erasing of eeprom memory and write circuit and
Method, to achieve these goals, technical solution of the present invention is as follows:
A kind of erasing for eeprom memory and write circuit, including: time-sequence control mode, memory module, input and output
Module, page buffer, page address decoder；It is characterized in that, also include: address decoder in page.
Further, in the page in described page buffer, address is identical with address in the page in eeprom memory and one by one
Corresponding.
Further, the data in described page buffer can write " 0 " can also one writing.
Further, the data in said write page buffer can be whole page, it is also possible to is that a byte is to one page institute
The most individual byte between the byte contained.
A kind of erasing for eeprom memory and wiring method, it is characterised in that erasing and write step are as follows:
S101, time-sequence control mode receives write signal W and produces signal PE；
S102, the page address needing erasing is carried out decoding and chooses by page address decoder；
S103, is saved in the page data that will be wiped free of in page buffer；
S104, time-sequence control mode produces E signal, page data erasing in the page address that will choose；
S105, in page, byte address decoder is chosen needing the byte address writing data to carry out decoding in page buffer；
S106, it would be desirable in the byte address in the page buffer that the data write of renewal is chosen；
S107, time-sequence control mode produces W signal, writes the data in page buffer through page address decoder one to one
In memory module page corresponding after decoding.
In view of above eeprom memory circuit structure, the present invention has a following characteristics:
1, EEPROM writing data flexible, the suitability is wide.
2, can only update small part data in one page, EEPROM memory space utilization rate is high.
3, to little market demand occasion only need to be updated, data speed is write fast.
Accompanying drawing explanation
Fig. 1 is the structural representation of background technology.
Fig. 2 is the structural representation of the present invention.
Fig. 3 is the flow chart of steps of the present invention.
Detailed description of the invention
Illustrate in specific embodiment in conjunction with accompanying drawings below:
Embodiment one
A kind of erasing for eeprom memory and write circuit, including: time-sequence control mode, memory module, input and output
Module, caching of page module, page address decoder；It is characterized in that, also include: address decoder in page, storing step is as follows:
S101, sequential control circuit produces signal PE after obtaining write signal W;
S102, the page address that need to wipe is carried out decoding and chooses by page address decoder；
S103, is saved in the page data that will be wiped free of in caching of page；
S104, time-sequence control mode produces E signal, is wiped by the page data choosing page address；
S105, in page, byte address decoder is chosen needing the byte address writing data to carry out decoding in page buffer；
S106, it would be desirable in the byte address of the page buffer that the data write of renewal is chosen；
S107, time-sequence control mode produces W signal, writes the data in page buffer through page address decoder one to one
In memory module page corresponding after decoding.
Further, in the page in described page buffer, address is identical with address in the page in eeprom memory and one by one
Corresponding.
Further, the data in described page buffer can write " 0 " can also one writing.
Further, the data in said write page buffer can be whole page, it is also possible to is that a byte is to one page institute
The most individual byte between the byte contained.
Embodiment two
Involved in the present invention for EEPROM erasing and write circuit and method thereof, its feature is: eeprom memory is wiped
It is the pattern that the erasing of whole page is write with whole page that the mode of data is write in data and programming, before erasing data, and eeprom memory quilt
Erasing page data be also read in caching of page, caching of page data, caching of page data can write " 0 " can also one writing, need compile
The data of journey can be whole page, it is also possible to is 1 byte to an any byte between the byte contained by one page, needs the number of programming
According to reading in caching of page, then the data in caching of page are programmed into the page corresponding to eeprom memory by whole page.
When sequential control circuit obtains write signal W, produce a signal PE, the page data that will be wiped free of is saved in
In caching of page.I.e. the page address of the page data will being wiped free of in eeprom memory through page address decoder for decoding, the most just
It is the page address by the memory element in page address decoder selection eeprom memory, then corresponding page address page
Data are read in page buffer.
When page address decoder selects the memory unit address inside eeprom memory, page address can only be navigated to, no
Byte address in page can be navigated to.
After the page data that will be wiped free of is saved in caching of page, sequential control circuit produces E signal, to page ground
The data of the page that location is corresponding after page address decoder decodes are wiped, meanwhile, and address word in page in page
Joint address decoder decodes, and address in the page that byte address decoder for decoding in data write page to be write is gone out
In caching of page.
In the page of required renewal data write identical with address in eeprom memory page and one to one page delay
After depositing, sequential control circuit produces W signal, and caching of page data write eeprom memory one to one and translate through page address
In page corresponding after code device decoding.
Claims (5)
1. for the erasing of eeprom memory and a write circuit, defeated including: time-sequence control mode, memory module, input
Go out module, page buffer, page address decoder；It is characterized in that, also include: address decoder in page.
Erasing the most according to claim 1 and write circuit, it is characterised in that in the page in described page buffer address with
In page in eeprom memory, address is identical and one_to_one corresponding.
Erasing the most according to claim 1 and write circuit, it is characterised in that the data in described page buffer can be write
" 0 " can also one writing.
Erasing the most according to claim 1 and write circuit, it is characterised in that the data in said write page buffer can
To be whole page, it is also possible to be a byte to an any byte between the byte contained by one page.
5. the erasing for eeprom memory and wiring method, it is characterised in that erasing and write step are as follows:
S101, time-sequence control mode receives write signal W and produces signal PE；
S102, the page address needing erasing is carried out decoding and chooses by page address decoder；
S103, is saved in the page data that will be wiped free of in page buffer；
S104, time-sequence control mode produces E signal, page data erasing in the page address that will choose；
S105, in page, byte address decoder is chosen needing the byte address writing data to carry out decoding in page buffer；
S106, it would be desirable in the byte address in the page buffer that the data write of renewal is chosen；
S107, time-sequence control mode produces W signal, writes the data in page buffer through page address decoder one to one
In memory module page corresponding after decoding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610501884.8A CN106158032A (en) | 2016-06-30 | 2016-06-30 | For the erasing of eeprom memory and write circuit and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610501884.8A CN106158032A (en) | 2016-06-30 | 2016-06-30 | For the erasing of eeprom memory and write circuit and method thereof |
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| Publication Number | Publication Date |
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| CN106158032A true CN106158032A (en) | 2016-11-23 |
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| CN201610501884.8A Pending CN106158032A (en) | 2016-06-30 | 2016-06-30 | For the erasing of eeprom memory and write circuit and method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836059A (en) * | 2021-11-26 | 2021-12-24 | 广州智慧城市发展研究院 | Control system applied to EEPROM (electrically erasable programmable read-Only memory) |
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|---|---|---|---|---|
| CN101278356A (en) * | 2005-10-05 | 2008-10-01 | St电子有限公司 | Method of block-writing to a memory element |
| CN101903953A (en) * | 2007-12-21 | 2010-12-01 | 莫塞德技术公司 | Non-volatile semiconductor memory device with power saving feature |
| CN102339644A (en) * | 2011-07-27 | 2012-02-01 | 聚辰半导体(上海)有限公司 | Memorizer and operating method thereof |
| CN103718162A (en) * | 2011-08-12 | 2014-04-09 | 华为技术有限公司 | Method and apparatus for flexible raid in ssd |
-
2016
- 2016-06-30 CN CN201610501884.8A patent/CN106158032A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101278356A (en) * | 2005-10-05 | 2008-10-01 | St电子有限公司 | Method of block-writing to a memory element |
| CN101903953A (en) * | 2007-12-21 | 2010-12-01 | 莫塞德技术公司 | Non-volatile semiconductor memory device with power saving feature |
| CN102339644A (en) * | 2011-07-27 | 2012-02-01 | 聚辰半导体(上海)有限公司 | Memorizer and operating method thereof |
| CN103718162A (en) * | 2011-08-12 | 2014-04-09 | 华为技术有限公司 | Method and apparatus for flexible raid in ssd |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113836059A (en) * | 2021-11-26 | 2021-12-24 | 广州智慧城市发展研究院 | Control system applied to EEPROM (electrically erasable programmable read-Only memory) |
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Application publication date: 20161123 |
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