CN106158030A - Method and relevant storage arrangement to memory device program - Google Patents

Abstract

The invention discloses a kind of method that storage arrangement is programmed, comprise the following steps: perform an insertion programming, including: in one first period, one first memory element is programmed, and in one second period, this first memory element is verified accordingly；Programming one second memory element in one the 3rd period, and verify this second memory element in one the 4th period accordingly, the 4th period is between this first period and this second period；And between this first period and this second period, insert at least one delay period, to guarantee that the unit interval resistance change of this first memory element is less than a threshold value.

Description

Method and relevant storage arrangement to memory device program

Technical field

The present invention relates to a kind of memory operating method and relevant storage arrangement, and particularly to A kind of method to memory device program and relevant storage arrangement.

Background technology

Memory program operation is typically divided into two classes: single memory element programming operation and page program Operation.The former is dependent on programming repeatedly-verify operations to ensure that memory element value falls within the target range. The latter is then to be programmed the memory element of whole page before verification operation.

But, for Ovonics unified memory (the phase change affected by resistance drift effect Memory, PCM) for, its resistive memory cell can change over time.This resistance variations can make The resistive memory cell value being verified is during single memory element programming operation or page programming operation Produce the final resistance value of mistake, and cause final resistance value distribution to broaden.

Therefore, how a kind of resistance drift effect slowed down between memory element is provided and improves data The memory program technology of reliability, is one of problem of being endeavoured of current industry.

Summary of the invention

The present invention relates to a kind of method to memory device program and relevant storage arrangement.

According to one embodiment of the invention, a kind of method to memory device program, this storage are proposed Device device includes multiple memory element.The method comprises the following steps: perform an insertion programming, including: In one first period to one first memory element programming in described memory element, and accordingly one the This first memory element is verified by two periods；In one the 3rd period in described memory element Second memory element programming, and in one the 4th period, this second memory element is verified accordingly, 4th period is between this first period and this second period；And this first period with this At least one delay period is inserted, to guarantee the unit interval resistance of this first memory element between two periods Value change is less than a threshold value.

According to another embodiment of the present invention, a kind of storage arrangement is proposed.This storage arrangement includes Memory array, column decoder, line decoder and controller.This memory array includes multiple depositing Storage unit.This column decoder connects described memory element by a plurality of character line.This line decoder passes through Multiple bit lines connects described memory element.This controller perform one insertion programming, make this column decoder with And this line decoder: in one first period to one first memory element programming in described memory element, And in one second period, this first memory element is verified accordingly；In one the 3rd period to described In memory element one second memory element programming, and accordingly one the 4th period to this second storage Unit is verified, the 4th period is between this first period and this second period；And at this At least one delay period is inserted, to guarantee this first memory element between first period and this second period Unit interval resistance change less than a threshold value.

More preferably understand in order to the above-mentioned and other aspect of the present invention is had, preferred embodiment cited below particularly, And coordinate accompanying drawing, it is described in detail below:

Accompanying drawing explanation

Fig. 1 is based on the storage arrangement of one embodiment of the invention；

Fig. 2 shows the normalized resistance drift characteristic of an example memory element；

Fig. 3 is based on the flow chart of the memory program of one embodiment of the invention；

Fig. 4 is based on the flow chart inserting scheduling of one embodiment of the invention；

Fig. 5 is based on the flow chart inserting programming of one embodiment of the invention；

Fig. 6 shows ISPP sequence after resetting according to an example of one embodiment of the invention；

Fig. 7 shows ISPP sequence after resetting according to another example of one embodiment of the invention；

Fig. 8 A shows and wafts based on the exemplary resistance obtained by the insertion programming technique that the present invention provides Move distribution；

Exemplary resistance drift obtained by Fig. 8 B shows based on initial program technology is distributed；

Fig. 9 shows the Drift Parameter calculated in 8A and 8B figure.

[description of reference numerals]

100: storage arrangement

102: memory array

104: column decoder

106: sensing amplifier/data input structure

108: line decoder

110: controller

112: consult table

202: normalized resistance characteristic curve

300,400,500: flow chart

302、304、306、308、310、312、402、404、502、504、506、508、 510,512,514: step

MC (1,1)～MC (M, N): memory element

WL (1)～WL (M): character line

BL (1)～BL (N): bit line

RDR: quickly drift region

SDR: drift region at a slow speed

Δ r: resistance change

Δ t: the unit interval

P (n, m): programming operation

V (n, m): verification operation

D, D1, D2, D3: delay period

TP: programming time

T_V: the proving time

T_D: time delay

T₁～T_k、T₁'～T_k': interval time

IP: the starting stage

PV: programming and Qualify Phase

VD: checking and delayed phase

Detailed description of the invention

Being described in detail by the following examples, embodiment, can't only in order to illustrate as example Limit the scope that the present invention to be protected.Additionally, the accompanying drawing in embodiment eliminates unnecessary element, To clearly show that the technical characterstic of the present invention.

Fig. 1 is based on the storage arrangement 100 of one embodiment of the invention.Storage arrangement 100 wraps Include memory array 102, column decoder 104, sensing amplifier/data input structure 106, go and translate Code device 108 and controller 110.Memory array 102 include multiple memory element MC (1,1), MC (1,2) ... and MC (M, N) (referred to here as memory element MC).Memory element MC can be Ovonics unified memory (phase change memory, PCM) memory element or the storage list of other kind Unit.Column decoder 104 is by a plurality of character line WL (1)-WL (M) (referred to here as character line WL) even It is connected to memory element MC.In response to the address information received, column decoder 104 can be by described Character line WL selects one of them in memory element MC that M arranges.Sensing amplifier/data are defeated Enter structure 106 to pass through bit line BL (1)-BL (N) (referred to here as bit line BL) detecting to be stored in storage single Data in unit MC.For example, sensing amplifier/data input structure 106 include for reading, Set and reset the current source of mode, and be coupled to line decoder 108 by bit line BL.Row is translated Code device 108 is connected to memory element MC by described bit line BL.In response to the address letter received Breath, line decoder 108 can be selected wherein in memory element MC of N row by described bit line BL One of.Controller 110 can control column decoder 104 and line decoder 108 perform programming operation, Verification operation, delay operation or other operation.In one embodiment, storage arrangement 100 can also wrap Include one and consult table 112 to record the parameter of multiple resistance characteristic being associated with memory element MC.Store It is available for controller 110 for formulating optimal Programming Strategy in the parameter consulted in table 112.

Refer to Fig. 2 and Fig. 3.Fig. 2 shows the normalized resistance characteristic of example memory element MC. Fig. 3 is based on the flow chart 300 of the memory program of one embodiment of the invention.

It is said that in general, the resistance of memory element MC can drift in time can be by following index Function carrys out modelling:

$R\left(t\right)=R_0{\left(\frac{t}{t_0}\right)}^{\mathrm{\γ}}---\left(\mathrm{eq}1\right)$

Its middle term time R₀Represent initial resistance, item time t₀Represent that reference time, item time γ represent resistance drift Coefficient.

By by equation eq1 divided by R₀And make γ=0.1 and t₀=1, the standardization in available Fig. 2 Resistance characteristic 202.In general, the resistance characteristic curve of memory element MC is divided into two Region: quickly drift region RDR and at a slow speed drift region SDR.In one embodiment, quick drift District RDR and at a slow speed drift region SDR can (Δ r/ Δ t) distinguishes by the tangent slope of resistance characteristic. For example, for tangent slope more than the curve section of a threshold value, can be regarded as quickly wafing Move district RDR；And for tangent slope less than the curve section of a threshold value, then can be regarded as slowly Speed drift region SDR.Therefore, memory element MC unit interval (Δ t) in quick drift region RDR (Δ r) is more than the unit interval resistance change in drift region SDR at a slow speed for resistance change.Such as Fig. 2 Shown in, the quick drift region RDR of curve 202 rises rapidly, and delays at drift region SDR at a slow speed Slowly rise.Owing to the data in memory element MC are determined by its resistance value, therefore when a memory element MC operates at its quick drift region RDR, it will reduce the reliability of data.

For solving resistance drift problem, controller 110 can perform insertion (interleaving) scheduling to keep away Exempt from operation quick drift region RDR (step 302).For example, controller 110 can be based on storage Parameter in consulting table 112, rearranges increment step pulse program (Incremental adaptively Step Pulse Programming, ISPP) in order of operation corresponding to guarantee each programming operation Verification operation between have enough interval times.In one embodiment, the strategy inserting scheduling can be examined Consider following condition:

1. guarantee there are enough interval times between the verification operation that each programming operation is corresponding to keep away Exempt from operation at quick drift region RDR；And/or

2. make difference interval time between described memory element MC minimize/equalization；And

Insert delay period (postponing operation) the most when necessary to meet one or two conditions above-mentioned.

In step 304, controller 110 can perform to insert programming and translate to control column decoder 104 and row Code device 108 performs the programmed/verified after scheduling/delay operation.For example, controller 110 is controlled Column decoder 104 processed and line decoder 108:

In the first period, memory element MC (1,1) shown in Fig. 1 is programmed, and accordingly This memory element MC (1,1) is verified by two periods；

In the 3rd period, memory element MC (1,2) is programmed, and in the 4th period, this is deposited accordingly Storage unit MC (1,2) verifies, the 4th period is between the first period and the second period；With And

At least one delay period is inserted, to guarantee memory element between the first period and the second period The unit interval resistance change of MC (1,1) is less than a threshold value, say, that, it is ensured that in memory element The SDR of drift region at a slow speed or the non-rapid drift region of MC (1,1) are read out.

In step 306, controller 110 can check whether that (such as, the memory element after all schedulings operates Programmed/verified/delay operation) all it is performed.If it is not, then perform step 308, next operation is performed.

After memory element operation after all schedulings is all performed, controller 110 can check whether institute Some memory element MC (or the target group in memory element MC, such as memory element MC (1,1) All (step 310) is shielded to MC (1, n), n is the integer less than N).If still have residue not by Memory element MC of shielding, then perform step 312, and next programming phases is quilt according to ISPP scheme Apply memory element MC so far not shielded a bit.

Fig. 4 is based on the flow chart 400 inserting scheduling of one embodiment of the invention.In step 402, Controller 402 can determine one based on above-mentioned insertion scheduling strategy for each Destination Storage Unit MC The insertion time is read out avoiding the quick drift region RDR at described Destination Storage Unit MC.

The insertion time may indicate that the interval time between the corresponding verification operation of programming operation.Real one Executing in example, the insertion time can consult table 112 by search and obtain, and this is consulted table 112 and records multiple It is related to the parameter of the resistance characteristic of memory element MC.When described parameter such as includes temperature, programming Between, proving time, target insert time and time delay at least one.In another embodiment In, the insertion time can access by memory element MC performs test one or more times and obtain.Lift For example, controller 110 can read memory element MC and reads result data to obtain, and based on reading Take the resistance characteristic of result data modelling memory element MC to determine the insertion time.

In step 404, controller 110 can be based on the insertion time again scheduling ISPP sequence and determine The operation of unscreened memory element MC.For example, controller 110 can according to the time of insertion certainly Surely to be inserted into how many interval time between the corresponding verification operation of programming operation and postpone week Phase, programming operation or verification operation.Based on the ISPP sequence after scheduling again, to not shielding storage The operation of unit MC can then be determined.

Fig. 5 is based on the flow chart 500 inserting programming of one embodiment of the invention.As it was previously stated, Insert the programmed/verified/delay operation of ISPP sequence after programming includes performing to reset.As it is shown in figure 5, Controller 110 first judges whether the current operation for Destination Storage Unit MC is verification operation (step Rapid 502).If so, Destination Storage Unit MC will be verified by controller 110.For example, Controller 110 can verify that memory element value (such as, voltage, the electric current of Destination Storage Unit MC Or resistance value) whether fall in target resistance region (step 504).If so, controller 110 then should Destination Storage Unit MC be shielded from after operation (step 506).Otherwise, if the sentencing of step 502 Disconnected result is no, then controller 110 will check whether current operation is programming (step 508).If It is that Destination Storage Unit MC will be programmed by controller 110.For example, controller 110 Can search and consult table 112 to obtain a program conditions (step 510), and with programming pulse, target be deposited Storage unit MC is programmed (step 512).If it is not, then controller 110 may wait for (delay) delay Cycle T D is with satisfied insertion scheduling strategy (step 514).

Fig. 6 shows ISPP sequence after resetting according to an example of one embodiment of the invention.At Fig. 6 In, " X (n, m) " represent at m-th ISPP step the n-th storage in Destination Storage Unit group Unit is programmed/verifies (X=P or V) operation；" D " represents delay period.Assume that target storage is single Tuple includes that (such as, (1, k), k is whole less than or equal to N to MC (1,1) to MC to k memory element Number), then P (1,1) represents the programming operation when the 1st ISPP step to memory element MC (1,1)； P (2,1) represents the programming operation P (2,1) when the 1st ISPP step to memory element MC (1,2)； P (k-1,1) represents the programming operation when the 1st ISPP step to memory element MC (1, k-1)；P (k, 1) Represent when the 1st ISPP step to memory element MC (1, programming operation k), by that analogy.Class As, P (1,2) represents the programming operation when the 2nd ISPP step to memory element MC (1,1)； P (2,2) represents the programming operation P (2,1) when the 2nd ISPP step to memory element MC (1,2)； P (k-1,2) represents the programming operation when the 2nd ISPP step to memory element MC (1, k-1)；P (k, 2) Represent when the 2nd ISPP step to memory element MC (1, programming operation k), by that analogy.

In this embodiment, each programming operation has the verification operation of its correspondence.As shown in Figure 6, right Should represent when the 1st ISPP step memory element MC (1,1) by the V (1,1) in programming operation P (1,1) Verification operation；V (2,1) corresponding to programming operation P (2,1) represents when the 1st ISPP step pair The verification operation of memory element MC (1,2)；V (k-1,1) corresponding to programming operation P (k-1,1) represents Verification operation to memory element MC (1, k-1) during the 1st ISPP step；Corresponding to programming operation The V (k, 1) of P (k, 1) represent when the 1st ISPP step to memory element MC (1, verification operation k), By that analogy.

In the example of fig. 6, the programming time of each programming operation is T_P, during the checking of individual verification operation Between be T_V, and the time delay of each delay period D is T_D.If T_P＞ ＞ T_VAnd T_P=T_D, for (the insertion time of such as MC (1,1) to MC (1, k)) will be equal to T for Destination Storage Unit_P, and respectively program behaviour Make each interval time of the T between corresponding verification operation₁To T_kIt is represented by:

T₁=T_P

T₂=T_P+T_V≈T_P

.

. (eq2)

.

T_k-1=T_P+T_V≈T_P

T_k=T_V+T_D≈T_P

Be can be seen that by equation eq2, interval time T₁To T_kApproximate insertion time (1*T_P).For For identical ISPP step, can be considered between the corresponding verification operation of each programming operation across one Individual programming operation, the verification operation corresponding except last programming operation postpones week across one Phase D.As shown in Figure 6, between corresponding for programming operation P (1,1) verification operation V (1,1) across Programming operation P (2,1)；Across programming between verification operation V (2,1) corresponding for programming operation P (2,1) Operation P (3,1)；Across programming between verification operation V (k-1,1) corresponding for programming operation P (k-1,1) Operation P (k, 1)；Across a delay between verification operation V (k, 1) corresponding for programming operation P (k, 1) Cycle D.

Fig. 7 shows ISPP sequence after resetting according to another example of one embodiment of the invention.Fig. 6 And the Main Differences between Fig. 7 example is in Fig. 7 for each Destination Storage Unit MC (1,1) extremely (1, insertion time k) is 3*T to MC_P.If T_P＞ ＞ T_VAnd T_P=T_D, each programming operation is corresponding to be tested Each interval time of T between card operation₁' to T_k' it is represented by:

T₁'=3T_P

T₂'=3T_P+T_V≈3T_P

.

. (eq3)

.

T_k-1'=T_P+2T_D+T_V≈T_P+2T_D≈3T_P

T_k'=3T_D+3T_V≈3T_D≈3T_P

Be can be seen that by equation eq3, interval time T₁' to T_k' approximate insertion time (3*T_P).Pin For identical ISPP step, can be considered between the corresponding verification operation of each programming operation across Three programming operations, except the verification operation that last programming operation (such as P (k, 1)) is corresponding (such as V (k, 1)) across three delay period D, as shown in Figure 7.

It will be appreciated that the present invention is not limited with above-mentioned example.In another embodiment, multiple mesh Mark memory element each self-corresponding insertion time can select according to actual demand, and can be not phase Deng.

Scheduling rule based on the 6th, in 7 figures, after rearrangement, ISPP sequence can include a starting stage (Initial Phase) IP, a programming and Qualify Phase (Program&Verify Phase) PV and test Card and delayed phase (Verify&Dummy Phase) VD.In starting stage IP, multiple targets are deposited A part in storage unit is programmed in order and is not performed checking.It is to say, multiple programmings Operation is performed in order at this stage IP, and does not perform any verification operation.In starting stage IP The quantity of programming operation is determined by inserting the time.As shown in Figure 6, the two (volumes in the 1+ insertion time Journey pulse wave) memory element MC (1,1), MC (1,2) be programmed (P (1,1) in starting stage IP in order And P (2,1)).Similarly, as it is shown in fig. 7, four (the programming pulse wave in the 1+ insertion time) storage is single Unit MC (1,1) is programmed (P (1,1) to P (4,1)) to MC (Isosorbide-5-Nitrae) in starting stage IP in order.

Programming and Qualify Phase PV can be considered the mixing of programming operation and verification operation.In an embodiment In, programming operation is alternately performed in this stage PV with verification operation.As a example by Fig. 6, test Card operation V (1,1), programming operation P (3,1), verification operation (2,1), programming operation (4,1) ..., and test Card operation V (k-1,1) is alternately performed in programming and Qualify Phase PV.

Checking and delayed phase VD can be considered verification operation and postpone the mixing of operation.As shown in Figure 6, In checking and delayed phase VD, verification operation V (k, 1) and then delay period (postponing operation) D. In the figure 7, delay period D1, verification operation V (k-2,1), delay period D2, verification operation V (k-1,1), Delay period D3 and proving period V (k, 1) is alternately performed in this stage VD.

Refer to Fig. 8 A and Fig. 8 B.Fig. 8 A shows the insertion programming technique provided based on the present invention Obtained exemplary resistance drift distribution.Obtained by Fig. 8 B shows based on initial program technology Exemplary resistance drift is distributed, in this initial program technology, and the volume of each verification operation and then its correspondence Journey operates.

Comparing for convenience, the resistance drift distribution in 8A and 8B figure obtains (example after the identical time Such as 100 seconds), and for the memory element (such as 256 memory element) of equal number.At Fig. 8 A In, the insertion time approximates 16*T_P(about 1.6 μ s, wherein T_P=100ns), and initial resistivity value (R0) Equal to 1M Ω.Be can be seen that by described figure, insert programming technique and can produce more close resistance drift Distribution.

Fig. 9 shows the Drift Parameter (γ) calculated in 8A and 8B figure.As it is shown in figure 9, this The insertion programming technique that invention provides can make Drift Parameter more averagely reduce 33%, therefore can slow down resistance and waft Move effect.

Sum it up, embodiments of the invention can by the corresponding verification operation of programming operation it Between update with avoid in quick drift region read resistive memory cell value.This operates a bit and can include Delay period, insertion programming operation, insertion verification operation or other operation.Based on inserting scheduling strategy, The order of ISPP sequence can be rearranged by being suitably inserting the time, to obtain electricity relatively closely Resistance drift distribution.Therefore, the resistance drift effect between memory element is reduced, and digital independent Reliability also can obtain improvement.

Particular embodiments described above, is carried out the purpose of the present invention, technical scheme and beneficial effect Further describe it should be understood that the foregoing is only the specific embodiment of the present invention, Be not limited to the present invention, all within the spirit and principles in the present invention, any amendment of being made, Equivalent, improvement etc., should be included within the scope of the present invention.

Claims (10)

1. the method to memory device program, this storage arrangement includes multiple memory element, The method includes:

Perform an insertion programming, including:

In one first period to one first memory element programming in described memory element, and exist accordingly This first memory element is verified by one second period；

In one the 3rd period to one second memory element programming in described memory element, and exist accordingly This second memory element is verified by one the 4th period, and the 4th period is between this first period and is somebody's turn to do Between second period；And

Between this first period and this second period, insert at least one delay period, with guarantee this first The unit interval resistance change of memory element is less than a threshold value.

2. the method for claim 1, it is characterised in that also include:

Perform an insertion scheduling, including:

According to the resistance characteristic of respectively this memory element, determine the insertion time for respectively this memory element； And

Determine the operation performing described memory element according to this insertion time, wherein said operation includes One programming operation, a verification operation and the delay operation corresponding to this at least one delay period.

3. method as claimed in claim 2, it is characterised in that this insertion persond eixis respectively programs Operate the interval time between corresponding verification operation, and the quantity of this at least one delay period by This insertion time determines；Wherein determine that this insertion time also includes:

Search one and consult table to obtain this insertion time；

Wherein this consults the multiple parameter of table record, and the resistance that described parameter is relevant to described memory element is special Property.

4. method as claimed in claim 2, it is characterised in that this insertion scheduling also includes:

The indivedual insertion times making described memory element are impartial；

Determine that this insertion time also includes:

Read described memory element and read result data to obtain；And

This resistance characteristic based on this reading result data modelling respectively this memory element is to determine that this is inserted The angle of incidence.

5. method as claimed in claim 2, it is characterised in that this insertion programming also includes:

One starting stage, including:

Perform multiple first programming operation in order and do not perform any verification operation；

One programming and Qualify Phase, including:

Alternately perform multiple second programming operation and multiple first verification operation；And

One checking and delayed phase, including:

Alternately perform one or more second verification operation and one or more the first delay operation；

Wherein the quantity of described first programming operation in this starting stage was determined by this insertion time.

6. a storage arrangement, including:

One memory array, including multiple memory element；

One column decoder, connects described memory element by a plurality of character line；

One line decoder, connects described memory element by multiple bit lines；And

One controller, performs an insertion programming, makes this column decoder and this line decoder:

In one first period to one first memory element programming in described memory element, and exist accordingly This first memory element is verified by one second period；

In one the 3rd period to one second memory element programming in described memory element, and exist accordingly This second memory element is verified by one the 4th period, and the 4th period is between this first period and is somebody's turn to do Between second period；And

Between this first period and this second period, insert at least one delay period, with guarantee this first The unit interval resistance change of memory element is less than a threshold value.

7. storage arrangement as claimed in claim 6, it is characterised in that this controller performs Insert scheduling with:

According to the resistance characteristic of respectively this memory element, determine the insertion time for respectively this memory element； And

Determine the operation performing described memory element according to this insertion time, wherein said operation includes One programming operation, a verification operation and the delay operation corresponding to this at least one delay period.

8. storage arrangement as claimed in claim 7, it is characterised in that this insertion persond eixis An interval time between the corresponding verification operation of each programming operation, and this at least one delay period Quantity was determined by this insertion time, and wherein this storage arrangement also includes:

One consults table, records multiple parameter, and described parameter is relevant to the resistance characteristic of described memory element.

9. storage arrangement as claimed in claim 7, it is characterised in that this controller controls should Column decoder and this line decoder read result data to read described memory element to obtain, and base In this resistance characteristic of this reading result data modelling respectively this memory element to determine this insertion time, The indivedual of wherein said memory element insert time equalization.

10. storage arrangement as claimed in claim 7, it is characterised in that this insertion programming is also wrapped Include:

One starting stage, including:

Perform multiple first programming operation in order and do not perform any verification operation；

One programming and Qualify Phase, including:

Alternately perform multiple second programming operation and multiple first verification operation；And

One checking and delayed phase, including:

Alternately perform one or more second verification operation and one or more the first delay operation；

Wherein the quantity of described first programming operation in this starting stage was determined by this insertion time.