CN106130535B - Local oscillator drive circuit based on phase inverter - Google Patents

Local oscillator drive circuit based on phase inverter Download PDF

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CN106130535B
CN106130535B CN201610666069.7A CN201610666069A CN106130535B CN 106130535 B CN106130535 B CN 106130535B CN 201610666069 A CN201610666069 A CN 201610666069A CN 106130535 B CN106130535 B CN 106130535B
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mos transistor
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inverter
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drain
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CN106130535A (en
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张君志
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Shenzhen Blue Lion Microelectronics Co ltd
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Shenzhen Blue Lion Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The embodiment of the invention provides a local oscillator drive circuit based on an inverter. The local oscillator drive circuit based on the phase inverter comprises a first input end, a second input end, a first output end, a second output end, a first phase inverter and a second phase inverter, wherein the first phase inverter is electrically connected between the first input end and the first output end, the second phase inverter is electrically connected between the second input end and the second output end, a third phase inverter and a fourth phase inverter are also electrically connected between the first input end and the second output end in sequence, and a fifth phase inverter and a sixth phase inverter are also electrically connected between the second input end and the first output end in sequence. By arranging the third inverter and the fourth inverter between the first input end and the second output end and arranging the fifth inverter and the sixth inverter between the second input end and the first output end, the common mode noise cancellation method is adopted, the noise suppression capability on the power supply and the ground is enhanced, and the robustness and the stability of the power supply and the ground are improved.

Description

Local oscillator drive circuit based on phase inverter
Technical Field
The invention relates to the field of communication electronic circuits, in particular to a local oscillator drive circuit based on an inverter.
Background
In a radio frequency receiver circuit, a local oscillator drive circuit is an indispensable part for amplifying and supplying a high-quality clock signal output from a phase locked loop to a mixer circuit, and such a local oscillator drive circuit is required both for a down-mixer circuit of the receiver and for an up-mixer circuit of the transmitter. In general, local oscillation driving circuits can be divided into two major types, namely a current-mode logic circuit-based driving circuit and an inverter-based driving circuit, in the traditional process, the local oscillation driving circuit based on the current-mode logic circuit has the advantage of speed, but in the background that the CMOS process below 130nm becomes the main flow process of a radio-frequency transceiver at present, the use of the local oscillation driving circuit based on the inverter is more and more common, on the one hand, because the device speed is continuously improved after the process is improved, and on the other hand, the local oscillation driving circuit based on the inverter often has the advantages of large oscillation amplitude and low power consumption. The prior art inverter unit has excessively high gain and is very sensitive to common mode noise on a power supply and the ground, and when the noise on the power supply exceeds a threshold value, the noise is amplified by the circuit, so that oscillation is formed, and the circuit loses normal functions.
Disclosure of Invention
Therefore, an objective of the embodiments of the present invention is to provide a local oscillator driving circuit based on an inverter, so that the circuit can overcome the influence of power supply and ground node mode noise during operation, and increase the robustness and stability of the circuit.
The local oscillator driving circuit based on the inverter provided by the embodiment of the invention comprises a first input end, a second input end, a first output end, a second output end, a first inverter and a second inverter, wherein the first inverter is electrically connected between the first input end and the first output end, the second inverter is electrically connected between the second input end and the second output end, a third inverter and a fourth inverter are also electrically connected between the first input end and the second output end in sequence, and a fifth inverter and a sixth inverter are also electrically connected between the second input end and the first output end in sequence.
Preferably, the first inverter includes a first N-type MOS transistor and a first P-type MOS transistor, a gate of the first N-type MOS transistor is connected to a gate of the first P-type MOS transistor, the first input terminal is connected between the gate of the first N-type MOS transistor and the gate of the first P-type MOS transistor, a drain of the first N-type MOS transistor is connected to a drain of the first P-type MOS transistor, a source of the first N-type MOS transistor is connected to a power supply, and a source of the first P-type MOS transistor is grounded.
Preferably, the first inverter further includes a first capacitor and a first resistor, one end of the first capacitor is connected to the first input end, the other end of the first capacitor is connected between the gate of the first N-type MOS transistor and the gate of the first P-type MOS transistor, one end of the first resistor is connected between the gate of the first N-type MOS transistor and the gate of the first P-type MOS transistor, and the other end of the first resistor is connected between the drain of the first N-type MOS transistor and the drain of the first P-type MOS transistor.
Preferably, the drain electrode of the first N-type MOS transistor is connected to the drain electrode of the first P-type MOS transistor, and then connected to the first output terminal.
Preferably, the second inverter includes a second N-type MOS transistor and a second P-type MOS transistor, where a gate of the second N-type MOS transistor is connected to a gate of the second P-type MOS transistor, the second input terminal is connected between the gate of the second N-type MOS transistor and the gate of the second P-type MOS transistor, a drain of the second N-type MOS transistor is connected to a drain of the second P-type MOS transistor, a source of the second N-type MOS transistor is connected to a power supply, a source of the second P-type MOS transistor is grounded, and a drain of the second N-type MOS transistor is connected to a drain of the second P-type MOS transistor and then connected to the second output terminal.
Preferably, the second inverter further includes a second capacitor and a second resistor, one end of the second capacitor is connected to the second input end, the other end of the second capacitor is connected between the gate of the second N-type MOS transistor and the gate of the second P-type MOS transistor, one end of the second resistor is connected between the gate of the second N-type MOS transistor and the gate of the second P-type MOS transistor, and the other end of the second resistor is connected between the drain of the second N-type MOS transistor and the drain of the second P-type MOS transistor.
Preferably, the third inverter includes a third P-type MOS transistor and a seventh P-type MOS transistor, both a gate and a drain of the third P-type MOS transistor are connected to a power supply, a source of the third P-type MOS transistor is connected to a drain of the seventh P-type MOS transistor, a gate of the seventh P-type MOS transistor is connected to the first input terminal, and a source of the seventh P-type MOS transistor is grounded.
Preferably, the fourth inverter includes a fourth N-type MOS transistor and a fourth P-type MOS transistor, where a gate of the fourth N-type MOS transistor and a gate of the fourth P-type MOS transistor are both connected to a source of the third P-type MOS transistor, a drain of the fourth N-type MOS transistor is connected to a drain of the fourth P-type MOS transistor, and the second output terminal is connected between the drain of the fourth N-type MOS transistor and the drain of the fourth P-type MOS transistor, and a source of the fourth N-type MOS transistor is connected to the power supply, and a source of the fourth P-type MOS transistor is grounded.
Preferably, the fifth inverter includes a fifth P-type MOS transistor and an eighth P-type MOS transistor, wherein a gate and a drain of the fifth P-type MOS transistor are both connected to a power supply, a source of the fifth P-type MOS transistor is connected to a drain of the eighth P-type MOS transistor, a gate of the eighth P-type MOS transistor is connected to the second input terminal, and a source of the eighth P-type MOS transistor is grounded.
Preferably, the sixth inverter includes a sixth N-type MOS transistor and a sixth P-type MOS transistor, the gate of the sixth N-type MOS transistor and the gate of the sixth P-type MOS transistor are both connected to the source of the fifth P-type MOS transistor, the drain of the sixth N-type MOS transistor and the drain of the sixth P-type MOS transistor are connected, the first output terminal is connected between the drain of the sixth N-type MOS transistor and the drain of the sixth P-type MOS transistor, the source of the sixth N-type MOS transistor is connected to the power supply, and the source of the sixth P-type MOS transistor is grounded.
Compared with the prior art, the local oscillator drive circuit based on the inverter has the advantages that the third inverter and the fourth inverter are arranged between the first input end and the second output end, the fifth inverter and the sixth inverter are arranged between the second input end and the first output end, and the common mode noise cancellation method is adopted, so that the noise suppression capability on power supply and ground is enhanced, and the robustness and the stability of the local oscillator drive circuit based on the inverter are improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of a local oscillator driving circuit based on an inverter according to a preferred embodiment of the present invention.
Fig. 2 is a schematic diagram of a local oscillator driving circuit based on an inverter according to a preferred embodiment of the present invention.
Fig. 3 is a graph of noise value as a function of gain value.
Description of the main reference signs
A first input 10; a second input 20; a first output 30; a second output 40; a first inverter 100; a first N-type MOS transistor 101; a first P-type MOS transistor 102; a first capacitor 103; a first resistor 104; a second inverter 200; a second N-type MOS transistor 201; a second P-type MOS transistor 202; a second capacitor 203; a second resistor 204; a third inverter 300; a third P-type MOS transistor 301; a seventh P-type MOS transistor 302; a fourth inverter 400; a fourth N-type MOS transistor 401; a fourth P-type MOS transistor 402; a fifth inverter 500; a fifth P-type MOS transistor 501; an eighth P-type MOS transistor 502; a sixth inverter 600; a sixth N-type MOS transistor 601; a sixth P-type MOS transistor 602.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, a schematic block diagram of a local oscillator driving circuit based on an inverter according to a preferred embodiment of the present invention is shown. The inverter-based local oscillator driving circuit according to the preferred embodiment of the present invention includes a first input terminal 10, a second input terminal 20, a first output terminal 30, a second output terminal 40, a first inverter 100, a second inverter 200, a third inverter 300, a fourth inverter 400, a fifth inverter 500, and a sixth inverter 600.
The first inverter 100 is electrically connected between the first input terminal 10 and the first output terminal 30, the second inverter 200 is electrically connected between the second input terminal 20 and the second output terminal 40, the third inverter 300 and the fourth inverter 400 are sequentially electrically connected between the first input terminal 10 and the second output terminal 40, and the fifth inverter 500 and the sixth inverter 600 are sequentially electrically connected between the second input terminal 20 and the first output terminal 30.
The first input terminal 10 and the second input terminal 20 are respectively two input ports for differential input, and the first output terminal 30 and the second output terminal 40 are respectively two output ports for differential output. The first inverter 100 and the second inverter 200 are used to implement a drive amplification function. The third inverter 300 and the fourth inverter 400 are used for canceling noise of the second inverter 200; the fifth inverter 500 and the sixth inverter 600 are used to cancel noise of the first inverter 100.
In general, the interference signal is common mode noise of the power supply or ground, and the interference signal at the first input terminal 10 and the second output terminal 40 is the same. Because if the power supply has a noise, their power supplies are equally disturbed for the first inverter and the second inverter 200, the disturbing signals are identical.
For example, when the input signals of the first input terminal 10 and the second input terminal 20 are both superimposed with an interference signal vcm + According to the principle of the inverter, the output end of the first inverter 100 is vcm - However, after the interference signal passes through the fifth inverter 500 and the sixth inverter 600, the signal output at the output terminal of the sixth inverter 600 is vcm + The first output 30 obtains interference signals vc from different pathsm - And vcm of + Can cancel each other out, so that the common mode of the output is suppressed. Similarly, interfering signals obtained from different paths at the second output 40 may be cancelled.
Fig. 2 is a schematic diagram of a local oscillator driving circuit based on an inverter according to a preferred embodiment of the present invention. The schematic diagram of fig. 1 is shown, in which the first inverter 100 includes a first N-type metal oxide semiconductor (metal oxide semiconductor, MOS) field effect transistor 101, a first P-type MOS transistor 102, a first capacitor 103, and a first resistor 104.
The gate of the first N-type MOS transistor 101 is connected to the gate of the first P-type MOS transistor 102, one end of the first capacitor 103 is connected to the first input terminal 10, and the other end of the first capacitor 103 is connected between the gate of the first N-type MOS transistor 101 and the gate of the first P-type MOS transistor 102. The drain of the first N-type MOS transistor 101 is connected to the drain of the first P-type MOS transistor 102, the source of the first N-type MOS transistor 101 is connected to a power supply, the source of the first P-type MOS transistor 102 is grounded, one end of the first resistor 104 is connected between the gate of the first N-type MOS transistor 101 and the gate of the first P-type MOS transistor 102, and the other end of the first resistor 104 is connected between the drain of the first N-type MOS transistor 101 and the drain of the first P-type MOS transistor 102.
The drain of the first N-type MOS transistor 101 is connected to the drain of the first P-type MOS transistor 102, and then connected to the first output terminal 30.
The second inverter 200 includes a second N-type MOS transistor 201, a second P-type MOS transistor 202, a second capacitor 203, and a second resistor 204, where a gate of the second N-type MOS transistor 201 is connected to a gate of the second P-type MOS transistor 202, one end of the second capacitor 203 is connected to the second input terminal 20, the other end of the second capacitor 203 is connected between the gate of the second N-type MOS transistor 201 and the gate of the second P-type MOS transistor 202, a drain of the second N-type MOS transistor 201 is connected to a drain of the second P-type MOS transistor 202, a source of the second N-type MOS transistor 201 is connected to a power supply, a source of the second P-type MOS transistor 202 is grounded, one end of the second resistor 204 is connected between the gate of the second N-type MOS transistor 201 and the gate of the second P-type MOS transistor 202, and the other end of the second resistor 204 is connected between the drain of the second N-type MOS transistor 201 and the drain of the second P-type MOS transistor 201.
The drain of the second N-type MOS transistor 201 is connected to the drain of the second P-type MOS transistor 202, and then connected to the second output terminal 40.
The first capacitor 103 and the second capacitor 203 are used for isolating the direct current of the first input terminal 10 and the direct current of the second input terminal 20, respectively. An ac small signal may be input from the first input terminal 10 to the gate of the first N-type MOS transistor 101 and the gate of the first P-type MOS transistor 102, and output to the first output terminal 30 through inverting amplification. An ac small signal may be input from the second input terminal 20 to the gate of the second N-type MOS transistor 201 and the gate of the second P-type MOS transistor 202, and output to the second output terminal 40 through inverting amplification.
The first resistor 104 and the second resistor 204 are used to provide self-biased dc operating points for the first inverter 100 and the second inverter 200, respectively, such that the gates of the first N-type MOS transistor 101, the first P-type MOS transistor 102, the second N-type MOS transistor 201, and the second P-type MOS transistor 202 are biased at reasonable dc levels.
The third inverter includes a third P-type MOS transistor 301 and a seventh P-type MOS transistor 302, where a gate and a drain of the third P-type MOS transistor 301 are both connected to a power supply, a source of the third P-type MOS transistor 301 is connected to a drain of the seventh P-type MOS transistor 302, a gate of the seventh P-type MOS transistor 302 is connected to the first input 10, and a source of the seventh P-type MOS transistor 302 is grounded.
The fourth inverter 400 includes a fourth N-type MOS transistor 401 and a fourth P-type MOS transistor 402, where a gate of the fourth N-type MOS transistor 401 and a gate of the fourth P-type MOS transistor 402 are both connected to a source of the third P-type MOS transistor 301, a drain of the fourth N-type MOS transistor 401 and a drain of the fourth P-type MOS transistor 402 are connected to the second output terminal 40, a source of the fourth N-type MOS transistor 401 is connected to the power supply, and a source of the fourth P-type MOS transistor 402 is grounded.
The third inverter 300 and the fourth inverter 400 are used for performing two-time inversion adjustment on the interference signal of the first output end 30, and the output end of the fourth inverter 400 is connected to the output end of the second inverter 200, so that the interference signals of the first output end 30 and the second output end 40 are identical, the inverted interference signals output by the second inverter 200 can be cancelled, and common mode noise on the power supply can be suppressed.
The fifth inverter includes a fifth P-type MOS transistor 501 and an eighth P-type MOS transistor 502, where the gate and the drain of the fifth P-type MOS transistor 501 are both connected to a power supply, the source of the fifth P-type MOS transistor 501 is connected to the drain of the eighth P-type MOS transistor 502, the gate of the eighth P-type MOS transistor 502 is connected to the second input terminal 20, and the source of the eighth P-type MOS transistor 502 is grounded.
The sixth inverter 600 includes a sixth N-type MOS transistor 601 and a sixth P-type MOS transistor 602, where a gate of the sixth N-type MOS transistor 601 and a gate of the sixth P-type MOS transistor 602 are both connected to a source of the fifth P-type MOS transistor 501, a drain of the sixth N-type MOS transistor 601 and a drain of the sixth P-type MOS transistor 602 are connected to the first output terminal 30, a source of the sixth N-type MOS transistor 601 is connected to the power supply, and a source of the sixth P-type MOS transistor 602 is grounded.
The fifth inverter 500 and the sixth inverter 600 are used for performing two-time inversion adjustment on the interference signal of the second output terminal 40, and the output terminal of the sixth inverter 600 is connected to the output terminal of the first inverter 100, so that the interference signals of the first output terminal 30 and the second output terminal 40 are identical, the inverted interference signal output by the first inverter 100 can be cancelled, and the common mode noise on the power supply can be suppressed.
Please refer to fig. 3, which is a graph of noise value and gain value. Wherein curve a is a relationship curve of the inverter-based local oscillator drive circuit shown in fig. 1. Curve B is a relationship curve of the inverter-based local oscillator driving circuit shown in fig. 1 with the third inverter 300, the fourth inverter 400, the fifth inverter 500, and the sixth inverter 600 removed.
The Gain represents the amount of noise, and dB represents the unit value of the amount of noise. Freq is the gain value and GHz is the unit of gain value. It can be seen from the B curve that the power supply node to the output node is positive gain and has a maximum gain of 33dB in the frequency range 1-10 GHz. As can be seen from curve a, the power supply rejection ratio is negative gain, and the maximum is not more than-7.5 dB in the range of tens of hertz. Indicating that common mode noise on the power supply is suppressed rather than amplified. Under the condition of multistage driving circuit connection, common mode noise can be further suppressed, and robustness and stability are greatly improved.
Therefore, the local oscillator driving circuit based on the phase inverter of the invention adopts a common mode noise cancellation method by arranging two phase inverters between the first input end 10 and the second output end 40 and two phase inverters between the second input end 20 and the first output end 30, thereby enhancing the noise suppression capability to power supply and ground and improving the robustness and stability.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present invention may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. The local oscillator driving circuit based on the inverter is characterized by comprising a first input end, a second input end, a first output end, a second output end, a first inverter and a second inverter, wherein the first inverter is electrically connected between the first input end and the first output end, the second inverter is electrically connected between the second input end and the second output end, a third inverter and a fourth inverter are further electrically connected between the first input end and the second output end in sequence, and a fifth inverter and a sixth inverter are further electrically connected between the second input end and the first output end in sequence.
2. The inverter-based local oscillator drive circuit of claim 1, wherein the first inverter comprises a first N-type MOS transistor and a first P-type MOS transistor, wherein a gate of the first N-type MOS transistor is connected to a gate of the first P-type MOS transistor, wherein the first input terminal is connected between the gate of the first N-type MOS transistor and the gate of the first P-type MOS transistor, wherein a drain of the first N-type MOS transistor is connected to a drain of the first P-type MOS transistor, wherein a source of the first N-type MOS transistor is connected to a power supply, and wherein a source of the first P-type MOS transistor is grounded.
3. The inverter-based local oscillator drive circuit of claim 2, wherein the first inverter further comprises a first capacitor and a first resistor, one end of the first capacitor is connected to the first input terminal, the other end of the first capacitor is connected between the gate of the first N-type MOS transistor and the gate of the first P-type MOS transistor, one end of the first resistor is connected between the gate of the first N-type MOS transistor and the gate of the first P-type MOS transistor, and the other end of the first resistor is connected between the drain of the first N-type MOS transistor and the drain of the first P-type MOS transistor.
4. The inverter-based local oscillator drive circuit of claim 2, wherein the drain of the first N-type MOS transistor is connected to the drain of the first P-type MOS transistor and then connected to the first output terminal.
5. The inverter-based local oscillator drive circuit of claim 1, wherein the second inverter comprises a second N-type MOS transistor and a second P-type MOS transistor, wherein the gate of the second N-type MOS transistor is connected to the gate of the second P-type MOS transistor, wherein the second input terminal is connected between the gate of the second N-type MOS transistor and the gate of the second P-type MOS transistor, wherein the drain of the second N-type MOS transistor is connected to the drain of the second P-type MOS transistor, wherein the source of the second N-type MOS transistor is connected to a power supply, wherein the source of the second P-type MOS transistor is grounded, and wherein the drain of the second N-type MOS transistor is connected to the drain of the second P-type MOS transistor and then connected to the second output terminal.
6. The inverter-based local oscillator drive circuit of claim 5, wherein the second inverter further comprises a second capacitor and a second resistor, wherein one end of the second capacitor is connected to the second input terminal, the other end of the second capacitor is connected between the gate of the second N-type MOS transistor and the gate of the second P-type MOS transistor, one end of the second resistor is connected between the gate of the second N-type MOS transistor and the gate of the second P-type MOS transistor, and the other end of the second resistor is connected between the drain of the second N-type MOS transistor and the drain of the second P-type MOS transistor.
7. The inverter-based local oscillator drive circuit of claim 1, wherein the third inverter comprises a third P-type MOS transistor and a seventh P-type MOS transistor, wherein a gate and a drain of the third P-type MOS transistor are both connected to a power supply, a source of the third P-type MOS transistor is connected to a drain of the seventh P-type MOS transistor, a gate of the seventh P-type MOS transistor is connected to the first input, and a source of the seventh P-type MOS transistor is grounded.
8. The inverter-based local oscillator drive circuit of claim 7, wherein the fourth inverter comprises a fourth N-type MOS transistor and a fourth P-type MOS transistor, wherein a gate of the fourth N-type MOS transistor and a gate of the fourth P-type MOS transistor are both connected to a source of the third P-type MOS transistor, wherein a drain of the fourth N-type MOS transistor and a drain of the fourth P-type MOS transistor are connected, wherein the second output terminal is connected between the drain of the fourth N-type MOS transistor and the drain of the fourth P-type MOS transistor, wherein a source of the fourth N-type MOS transistor is connected to the power supply, and wherein a source of the fourth P-type MOS transistor is grounded.
9. The inverter-based local oscillator drive circuit of claim 1, wherein the fifth inverter comprises a fifth P-type MOS transistor and an eighth P-type MOS transistor, wherein a gate and a drain of the fifth P-type MOS transistor are both connected to a power supply, a source of the fifth P-type MOS transistor is connected to a drain of the eighth P-type MOS transistor, a gate of the eighth P-type MOS transistor is connected to the second input, and a source of the eighth P-type MOS transistor is grounded.
10. The inverter-based local oscillator drive circuit of claim 9, wherein the sixth inverter comprises a sixth N-type MOS transistor and a sixth P-type MOS transistor, wherein a gate of the sixth N-type MOS transistor and a gate of the sixth P-type MOS transistor are both connected to a source of the fifth P-type MOS transistor, wherein a drain of the sixth N-type MOS transistor and a drain of the sixth P-type MOS transistor are connected, wherein the first output terminal is connected between the drain of the sixth N-type MOS transistor and the drain of the sixth P-type MOS transistor, wherein a source of the sixth N-type MOS transistor is connected to the power supply, and wherein a source of the sixth P-type MOS transistor is grounded.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07162284A (en) * 1993-12-07 1995-06-23 Toshiba Corp Output buffer circuit
JP2002237733A (en) * 2000-12-05 2002-08-23 Nippon Telegr & Teleph Corp <Ntt> Transconductance amplifier circuit
JP2011166461A (en) * 2010-02-10 2011-08-25 Seiko Npc Corp Level shift circuit and oscillator using the same
CN205864386U (en) * 2016-08-12 2017-01-04 深圳市蓝狮微电子有限公司 Local oscillator drive circuit based on phase inverter

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI323573B (en) * 2006-11-22 2010-04-11 Ind Tech Res Inst Differential bidirectional transceiver
KR20130130478A (en) * 2012-05-22 2013-12-02 삼성전자주식회사 Input buffer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07162284A (en) * 1993-12-07 1995-06-23 Toshiba Corp Output buffer circuit
JP2002237733A (en) * 2000-12-05 2002-08-23 Nippon Telegr & Teleph Corp <Ntt> Transconductance amplifier circuit
JP2011166461A (en) * 2010-02-10 2011-08-25 Seiko Npc Corp Level shift circuit and oscillator using the same
CN205864386U (en) * 2016-08-12 2017-01-04 深圳市蓝狮微电子有限公司 Local oscillator drive circuit based on phase inverter

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