CN106128353A - Line-scanning drive circuit that a kind of TFT is integrated and driving method thereof - Google Patents
Line-scanning drive circuit that a kind of TFT is integrated and driving method thereof Download PDFInfo
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- CN106128353A CN106128353A CN201610804907.2A CN201610804907A CN106128353A CN 106128353 A CN106128353 A CN 106128353A CN 201610804907 A CN201610804907 A CN 201610804907A CN 106128353 A CN106128353 A CN 106128353A
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The invention discloses line-scanning drive circuit integrated for a kind of TFT and driving method thereof, this line-scanning drive circuit at least includes that a line-scanning drive circuit unit, each line-scanning drive circuit element circuit include six TFT and an electric capacity.Described line-scanning drive circuit is controlled by two-way clock signal, and initialization module uses the first pulse signal CK1 to coordinate control with bootstrapping node Q, simplifies line-scanning drive circuit and reduces the output noise voltage that clock feedthrough brings.High level maintains and uses electric charge shared structure in module, it is possible to achieve multiplex pulse signal controls, and utilizes the pulse signal of different duty to do control signal and can reduce circuit power consumption.
Description
Technical field
The present invention relates to electronic circuit field, particularly relate to line-scanning drive circuit integrated for a kind of TFT and driving side thereof
Method.
Background technology
At present, non-crystalline silicon tft (a-Si TFT) and multi-crystal TFT (Poly-Si TFT) are that flat display field is main
Volume production technology.Although a-Si TFT has the advantages such as large-area uniformity is good, process costs is cheap, it is suitable for relatively low resolution
The application scenario of rate bigger display area.But it is constrained to relatively low carrier mobility and poor electrology characteristic stability,
A-Si TFT is not suitable for IC design.On the other hand, multi-crystal TFT then has higher carrier mobility, and
Electrical stability is good, and it is not only widely applied in the high-quality mobile phone display screen of high-resolution, and it is suitable for
Make integrated circuit on the glass substrate.When multi-crystal TFT horizontal drive circuit and pel array are integrated in same substrate, not only
Peripheral driver IC and connecting line thereof can be reduced so that the frame of TFT display floater is narrower, and display module work can be simplified
Skill, improves yield.
In the line-scanning drive circuit design of traditional LTPS TFT, need to use more clock signal play control and
The effect driven.But owing to clock signal quantity is too much, the line-scanning drive circuit performance of LTPS TFT is the best.This is mainly
Because: 1) clock signal of multichannel leggy requires complicated control sequential, sequencing contro IC and level shift IC are carried by this
Go out the requirement being more difficult to realize, easily brought and drive increasing substantially of IC price；2) in line-scanning drive circuit layout design
In, the conducting resistance less in order to ensure clock cabling, it is to avoid owing to RC postpones to have influence on the most greatly the function of scanning circuit, typically
The width number of clock cabling is in terms of 100um.Therefore, when the quantity of clock signal is too much, the area mistake that line-scan circuit takies
Greatly, the narrow frame design of display floater it is unfavorable for.Therefore, how to simplify the complexity of integrated line-scanning drive circuit, with more
Few number of signals realizes the problem that more preferable circuit performance, always flat display field need solution badly.
Summary of the invention
The present invention is directed to line-scanning drive circuit in prior art and need too much sequencing contro and baroque problem,
Provide line-scanning drive circuit integrated for TFT and the driving method thereof of a kind of simple in construction.
The line-scanning drive circuit that a kind of TFT is integrated, including a line-scanning drive circuit unit；
Described line-scanning drive circuit unit includes initialization module 10, drives module 30, input module 20, high level dimension
Hold module 40 and electric charge sharing module 50；
Described initialization module 10 is connected with the first pulse signal end and bootstrapping node Q, is passed by the signal on earth terminal GND
Deliver to the outfan of line-scanning drive circuit unit, line-scanning drive circuit is initialized；
Described driving module 30 is connected with the first pulse signal end, the significant level of the first pulse signal is sent to row and sweeps
Retouch the outfan of drive circuit unit；
Described input module 20 is coupled in bootstrapping node Q with driving module, the Automatic level control input mould of response initial pulse
The switching state of block breaker in middle；
Described high level maintains module 40 for, after line-scanning drive circuit unit output line scan signals, driving mould
The line scan signals outfan of block maintains high level；
Described electric charge sharing module 50 is coupled between bootstrapping node Q and the outfan of line-scanning drive circuit unit, uses
In responsive trip scan drive circuit unit outfan state self-adaption adjust bootstrapping node Q current potential；
Described line-scanning drive circuit initialization module 10 is connected with input module 20, and the first signal IN passes through input module
(10) it is delivered to drive module 30, after driving module 30 to respond the first signal IN, the first pulse signal is delivered to row scanning electricity
Road outfan；High level maintains module 40 to be connected with initialization module 10, and signal on earth terminal GND is sent to row scanning respectively
The outfan of drive circuit unit and output end signal is sent to the node Q that boots；Described electric charge sharing module 50 one end with from
Lifting node Q to be connected, the other end is connected with the outfan of line-scanning drive circuit unit.
The significant level of the first signal IN arrives the significant level arrival time early than the first pulse signal CK1 time, institute
The significant level stating the first signal IN and the first pulse signal CK1 does not overlaps.
Described initialization module 10 includes the 4th transistor T4 and the 6th transistor T6；
After the control pole of the 4th transistor T4 couples with the first pole, it is connected with the first pulse signal end CK1；4th transistor
Second pole of T4 coupled to first pole of the 6th transistor T6 and forms primary nodal point P；
Second pole of the 6th transistor T6 coupled to earth terminal GND；The control pole of the 6th transistor T6 coupled to bootstrapping joint
Point Q.
Described driving module 30 includes the first transistor T1 and the first electric capacity C1；
The control pole of the first transistor T1 coupled to the node Q that boots；First pole of the first transistor T1 and the first pulse letter
Number end CK1 be connected；Second pole of the first transistor T1 coupled to output node F；
The two ends of the first electric capacity C1 coupled between the control pole of the first transistor T1 and the second pole.
Described input module 20 includes third transistor T3；
Second pole of third transistor T3 coupled to the node Q that boots；The control pole of third transistor T3 couples with the first pole,
Input for the first signal N.
Described high level maintains module 40 to include the 5th transistor T5；
The pole that controls of the 5th transistor T5 coupled to second pole of the 4th transistor T4；The first pole coupling of the 5th transistor T5
It is bonded to output node F；Second pole of the 5th transistor T5 coupled to earth terminal GND.
Described electric charge sharing module 50 includes transistor seconds T2；
The control pole of transistor seconds T2 coupled to the first pulse signal end；First pole of transistor seconds T2 coupled to certainly
Lift node Q；Second pole of transistor seconds T2 coupled to output node F, exports for line-scanning drive circuit unit.
Described transistor seconds T2 control pole, the 4th transistor T4 control pole and first the most all with the second pulse signal
End is connected.
Including at least including two line-scanning drive circuit unit cascaded；
The signal output part of prime line-scanning drive circuit unit and the first signal of rear class line-scanning drive circuit unit
End IN is connected.
Described initialization module 10 also includes that the two ends of the second electric capacity C2, described second electric capacity C2 connect and the 6th transistor
Control pole and bootstrapping node Q between, and the 4th transistor control pole be connected with one end of the second electric capacity C2.
The first of all transistors extremely source electrode or drain electrode, the second extremely drain electrode or source electrode, control extremely grid, i.e. when the
One extremely source electrode time, second extremely drains；First when extremely draining, the second extremely source electrode；
The driving method of the line-scanning drive circuit that a kind of TFT is integrated, uses row turntable driving electricity integrated for above-mentioned TFT
Road, inputs the first signal from input module, from driving module input pulse signal, inputs at the earth terminal GND of initialization module
GND signal；
When line-scanning drive circuit be series of rows scan drive circuit unit cascaded time, odd level line-scanning drive circuit
First pulse signal is provided by the first clock signal CK1, when the first pulse signal of even level line-scanning drive circuit is by second
Clock CK2 provides；
When there is the second pulse signal end in line-scanning drive circuit unit, the second arteries and veins of odd level line-scanning drive circuit
Rushing signal to be provided by second clock signal CK2, the second pulse signal of even level line-scanning drive circuit is carried by the first clock CK1
Supply；
Wherein, the sequential of second clock signal CK2 and the first clock signal CK1 is contrary.
When there is the second pulse signal end in line-scanning drive circuit unit, and whole row scan drive cell uses multichannel
During pulse control signal, the first pulse signal of the first order is CK1, the second pulse signal is CK2, the first pulse letter of the second level
Number being CK3 for CK2, the second pulse signal, first pulse signal of the third level is CK3, the second pulse signal is CK4, successively class
Push away, be circulated by pulse way.
Beneficial effect
The invention provides line-scanning drive circuit integrated for a kind of TFT and driving method thereof, this line-scanning drive circuit
At least include that a line-scanning drive circuit unit, each line-scanning drive circuit element circuit include 6 TFT and 1 electric capacity,
Comparing more traditional line-scanning drive circuit uses multiple TFT to constitute with electric capacity, and this design simplifies answering of line-scanning drive circuit
Miscellaneous degree.Circuit of the present invention uses 2 tunnel clock signals to control, and wherein in initialization module design, uses the first pulse signal CK1
Coordinate control with bootstrapping node Q, do not set special control signal, solve tradition line-scanning drive circuit and control loaded down with trivial details the asking of sequential
Inscribe, reduce the circuit output noise caused because clock signal coupling.Meanwhile, specialized designs high level maintains module,
This module have employed a kind of electric charge shared structure, solve control clock feed-through effect to driving TFT gate and source voltage
Impact, thus the high level voltage of line scan signals of holding circuit output.Additionally, high level maintains module to control the shape of end
State switching signal and output module control signal are multiplexings, further simplify circuit structure, the active TFT of the narrowest frame
The realization of panel.This driving method can realize multiplex pulse signal control, utilizes the pulse signal of different duty to do and controls
Signal can reduce the dynamic power consumption of circuit.
Accompanying drawing explanation
Fig. 1 is low temperature polycrystalline silicon TFT structure figure；
Fig. 2 is the embodiment of the present application one the first line-scanning drive circuit cellular construction figure disclosed；
Fig. 3 is the second line-scanning drive circuit cellular construction figure disclosed in the embodiment of the present application one；
Fig. 4 is the embodiment of the present application one the third line-scanning drive circuit cellular construction figure disclosed；
Fig. 5 is a kind of working timing figure of the embodiment of the present application one the first line-scanning drive circuit unit disclosed；
Fig. 6 is the simulation working timing figure of line-scanning drive circuit unit corresponding for Fig. 5；
Fig. 7 is a kind of simulation working timing figure of line-scanning drive circuit unit corresponding for Fig. 4；
Fig. 8 is a kind of line-scanning drive circuit cellular construction block diagram disclosed in the embodiment of the present application two；
Fig. 9 is a kind of line-scanning drive circuit structural representation disclosed in the embodiment of the present application two；
Figure 10 is a kind of working timing figure of line-scanning drive circuit corresponding for Fig. 9；
Figure 11 is a kind of simulation working timing figure of line-scanning drive circuit corresponding for Figure 10.
Detailed description of the invention
In order to make techniques disclosed in this application content more detailed and complete, can refer to the following of accompanying drawing and the present invention
Various specific embodiments, labelling identical in accompanying drawing represents same or analogous assembly.
With reference to the accompanying drawings, detailed description of the invention to various aspects of the present invention is described in further detail.
First some terms are illustrated:
Transistor in the present invention can be field-effect transistor or bipolar transistor.
When transistor is field-effect transistor, it controls pole and refers to the grid of field-effect transistor, and first can be extremely
The drain electrode of field-effect transistor or source electrode, corresponding second can be extremely source electrode or the drain electrode of field-effect transistor.
When transistor is bipolar transistor, it controls pole and refers to the base stage of bipolar transistor, and first can be extremely
The colelctor electrode of bipolar transistor or emitter stage, corresponding second can be extremely emitter stage or the colelctor electrode of bipolar transistor；
A kind of field-effect transistor of transistor in display: thin film transistor (TFT) (TFT).
As a example by transistor is as field-effect transistor, the application is described in detail below, in other embodiments crystal
Pipe can also be bipolar transistor.
With reference to Fig. 1, for low temperature polycrystalline silicon TFT structure figure.Multi-crystal TFT uses the design of autoregistration top-gate type structure, so
Grid can use the Al material of low-resistivity to do electrode, cost is greatly lowered, improves photoetching technique.The making work of polysilicon
Skill is broadly divided into: (1) sputters layer of metal layer on the glass substrate and does source-drain electrode, and chemical wet etching forms source-drain electrode (2) PECVD
(plasma enhanced chemical vapor deposition) deposition substrate film and amorphous silicon membrane, and by low
Temperature laser annealing method, becomes amorphous silicon membrane crystallization polysilicon membrane and uses the mode of ion implanting to mix boron, forming doping
District (3) PECVD depositing insulating layer, insulating layer material is generally SiO2(4) sputtering layer of metal film, chemical wet etching forms grid,
And deposit a layer insulating (5) and be lithographically formed contact hole, sputtering pixel electrode nesa coating ITO, chemical wet etching forms pixel
Electrode.
LTPS TFT has higher carrier mobility and stable electric property, it is adaptable to high response speed, Gao Ke
By in the circuit design such as property, low-power consumption.N-type LTPS that compares TFT manufacturing process, p-type LTPS TFT manufacturing process is simpler.
This is because when forming doped region, p-type structure needs boron ion implanting, ion energy has only to 10KeV, and N type junction structure needs
The P ion energy demand wanted reaches 70KeV.The thermostability of next p-type LTPS TFT and good stability are in N-type LTPS TFT.Therefore
When designing circuit based on LTPS TFT, it is typically chosen the TFT of p-type structure.
In this enforcement, significant level is low level, this is because the device chosen in circuit design of the present invention is p-type
TFT.In other alternate embodiment, it is also possible to determine that significant level is high level according to the transistor chosen.As based on N
When type TFT realizes this circuit function, can choose significant level is high level.The signal being previously mentioned in the present invention is overlapping refers to two-way
Signal at least in a certain phase in the same time all in significant level state, therefore, do not overlap and be not co-located on for two paths of signals
The moment of effect level state.
Embodiment one；
With reference to Fig. 2, a kind of line-scanning drive circuit cellular construction figure disclosed in the present embodiment, including: initialization module
10, input module 20, driving module 30, high level maintain module 40 and electric charge sharing module 50；
Wherein, initialization module 10 is connected with the first pulse signal end and bootstrapping node Q, for being cut by off state
Change, GND is sent to the outfan of line-scanning drive circuit unit, circuit is initialized.
In one embodiment, initialization module 10 includes the 4th transistor, the 6th transistor；The control of the 4th transistor
Pole processed (such as grid) coupled to the first pole (such as drain electrode), for input the first pulse signal CK1；The second of 4th transistor
Pole (such as source electrode) coupled to first pole (such as drain electrode) of the 6th transistor and forms primary nodal point (P)；The of 6th transistor
One pole (such as drain electrode) coupled to the first pole of the 4th transistor；Second pole (such as source electrode) of the 6th transistor couples paramount electricity
Flush end；The control pole (such as grid) of the 6th transistor coupled to the node Q that boots.In other embodiments, initialization module is also
Can be other implementation, or increase or reduce components and parts, such as Fig. 3, initialization module not only includes the 4th crystal
Pipe T4, the 5th transistor T5, the 6th transistor T6, also include the second electric capacity C2.
Input module 20 couples formation bootstrapping node Q with driving module 30, and bootstrapping node Q responds the level of the first signal IN
Control switching on off state, for inputting the first signal IN from the first signal input part, bootstrapping node Q coupled to low level,
It is used for providing driving voltage；In a kind of instantiation, input module 20 includes the third transistor for inputting the first signal
T3, the control pole (such as grid) of third transistor T3 couples the first pole (such as drain electrode), for inputting the first signal IN, the 3rd
Second pole (such as source electrode) of transistor T3 coupled to the control pole (such as grid) of the first transistor T1 and forms bootstrapping node Q.
Drive module 30 for being switched by off state, by the significant level V of the first pulse signal CK1LIt is sent to row
The row scanning output end of scan drive circuit, thus export line scan signals OUT [n].In a kind of specific embodiment, drive mould
Block 30 can include the first transistor T1 for being coupled to line-scanning drive circuit unit outfan and for storing driving control
First electric capacity C1 of end Q electric charge processed.Such as, the control pole (such as grid) of the first transistor T1 be coupled to boot node Q, first
Pole (such as drain electrode) is for input the first pulse signal CK1, and the second pole (such as source electrode) is the output of line-scanning drive circuit unit
End；First electric capacity C1 is coupled respectively between the control pole (such as grid) of the first transistor T1 and the second pole (such as source electrode).
High level maintains module 40, controls, for being maintained by its high level, the on off state that end-grain cutting is changed, scans at this row
After drive circuit unit output line scan signals, the line scan signals outfan driving module is maintained high level.Concrete one
In embodiment, high level maintains module 40 to include transistor seconds T2.Control pole (such as grid) coupling of transistor seconds T2
To the first pulse signal CK1；First pole (such as drain electrode) of transistor seconds T2 coupled to the node Q that boots；Transistor seconds T2
The second pole (such as source electrode) coupled to output node F, for line-scanning drive circuit export.
Electric charge sharing module (50) includes transistor seconds T2；The control pole of transistor seconds T2 coupled to the first pulse letter
Number end；First pole of transistor seconds T2 coupled to the node Q that boots；Second pole of transistor seconds T2 coupled to output node F,
Export for line-scanning drive circuit unit；For responsive trip scan drive circuit unit outfan state self-adaption adjust
The current potential of bootstrapping node Q.
In the present embodiment, arriving of the significant level that the significant level of the first signal IN arrives early than the first pulse signal CK1
Carrying out the time, the significant level of the first signal IN and the significant level of the first pulse signal CK1 do not overlap.
Refer to Fig. 5, a kind of working timing figure of line-scanning drive circuit unit disclosed in the embodiment of the present application one.Under
Face will illustrate the work process of line-scanning drive circuit unit shown in Fig. 2, Fig. 3 and Fig. 4 in conjunction with Fig. 5.First with Fig. 2 it is
Example:
Initial phase (P1): the first signal IN is high level, third transistor T3 is closed.As the first pulse signal CK1
For low level, transistor seconds T2, the 4th transistor T4, the 5th transistor T5 open.Bootstrapping node Q and output OUT1 is by the
Two-transistor T2 connects together and is all charged to GND by the 5th transistor T5.When the first pulse signal CK1 is high electricity
At ordinary times, the 5th transistor T5 remains in that open mode, bootstrapping node Q are maintained at high level with output OUT1.
Input phase (P2): the first pulse signal CK1 is high level, transistor seconds T2, the 4th transistor T4 close.The
One signal IN signal is low level, and third transistor T3 is opened, and bootstrapping node Q is pulled to low level, and then the first transistor T1,
6th transistor T6 opens.Now the 6th transistor T6 opens and causes the 5th transistor T5 to close, and the first transistor T1 beats simultaneously
The high level convincing cause the first pulse signal CK1 by patient analysis is delivered to line-scanning drive circuit unit outfan.
Bootstrapping stage (P3): the first signal IN signal is high level, third transistor T3 is closed.Due to bootstrapping node Q still
Low level, the first transistor T1 and the 6th transistor T6 is so kept to remain in that and open.When the first pulse signal CK1 is for becoming low
During level, due to the boot strap of the first electric capacity, bootstrapping node Q is pulled to (VL-VTH_T3)+(VL-VH).OUT1 is by quickly in output
Move V toL.Transistor seconds T2 closes simultaneously, this is because output OUT1 is transistor seconds source electrode and is quickly moved to
VL, the gate source voltage of transistor seconds T2 is 0V, much larger than the threshold voltage of transistor seconds T2.When the first pulse signal becomes
During high level, transistor seconds T2, the 4th transistor T4 close.Owing to the first transistor T1, the 6th transistor T6 still open,
Causing the 5th transistor T5 still to close, the first pulse signal CK1 is delivered to line-scanning drive circuit by the first transistor T1
Unit outfan.Now due to the boot strap of the first electric capacity C1, bootstrapping node Q is pulled high to VL-VTH_T3。
Charge sharing phase (P4): the first pulse signal CK1 is low level, transistor seconds T2, the 4th transistor T4 beat
Open.4th transistor T4 opens and causes the 5th transistor T5 to open, and CND is delivered to outfan OUT1 by the 5th transistor.By
Connect together by transistor seconds T2 with output OUT1 in bootstrapping node Q, the voltage of node of booting by the first electric capacity C1 and
The shared electric charge of load capacitance C determines.Now being stored in the total electrical charge on electric capacity is: QAlways=C1×(VL-VTH_T3), load capacitance
C shares electric charge:Owing to load capacitance is far longer than the first electric capacity C1, so being stored on the first electric capacity
Electric charge almost flow to load capacitance C, on the first electric capacity C1 almost without storage electric charge, so boot node Q be pulled high to height
Level.
High level keeps the stage (P5): the first signal IN is high level, and third transistor T3 is closed.When the first pulse signal
CK1 is low level, and transistor seconds T2, the 4th transistor T4, the 5th transistor T5 open.Bootstrapping node Q and outfan OUT1
Link together, and keep high level constant.
When the first pulse signal CK1 is high level, transistor seconds T2, the 4th transistor T4 close, the 5th transistor
T5 remains in that and opens.Bootstrapping node Q links together with outfan OUT1, and remains in that high level is constant.
Hereafter, no matter the first pulse signal is high level or low level, and the 5th transistor T5 is always maintained at open mode,
Output OUT1 is also high voltage, until next frame the first signal IN re-enters low level.
It should be noted that in the high level maintenance stage, the grid of the first transistor T1 and the voltage of source electrode are easily subject to
The impact of clock feed-through effect, their voltage can be followed the change of the first pulse signal CK1 and be floated.And for row cutting electricity
For road, outside line scan signals, time most, the output of line-scanning drive circuit should be in high level maintenance
State.The floating of the grid of the first transistor T1 and the voltage of source electrode may be transmitted in line-scanning drive circuit link, leads
There is, in high level maintenance part, the noise voltage that amplitude is bigger in the line scan signals causing line-scanning drive circuit output, and this
Planting noise voltage likely to accumulate by pole, the logic ultimately resulting in line-scanning drive circuit output is disorderly, produces misleading.In order to
The impact of suppression clock feed-through effect, just introduces high level in circuit embarked on journey by collection and maintains module, maintain control at its high level
When end processed obtains significant level, the 5th transistor T5 and transistor seconds T2 conducting, respectively will bootstrapping node Q and the output of row signal
End coupled to high level end, maintains high level voltage VH, thus maintain the line scan signals that line-scanning drive circuit exports
High level voltage.
In another kind of specific embodiment, refer to Fig. 3, initialization module can include the 4th transistor T4, the 5th crystal
Pipe T5, the 6th transistor T6 and the second electric capacity C2.Can be by the control pole (such as grid) of the 4th transistor T4 and the 6th crystal
The control pole (such as grid) of pipe T6 is coupled together, and is coupled to, by the second electric capacity C2, the node Q that boots.This embodiment excellent
Gesture is:
The control pole (such as grid) of (1) the 4th transistor T4 coupled to bootstrapping node Q by the second electric capacity C2 and improves
4th transistor T4 driving force and decrease circuit dynamic power consumption.This is because the grid voltage of the 4th transistor T4 is by certainly
Lifting the modulation of node Q, in the drop-down stage, the grid voltage of the 4th transistor T4 can pulled down to (VL-VTH_T3)+(VL-VH),
Thus improve the driving force of the 4th transistor.Secondly in the high level maintenance stage, the 4th transistor T4 closes, its grid source with
Gate-drain parasitic capacitances no longer produces dynamic power consumption.
(2) the 4th transistor T4 are operated in linear zone, improve the response speed of circuit.This is because the 4th transistor T4
The method no longer using grid source short circuit, the 4th transistor T4 can quickly open when the node Q that boots is low level, improves circuit
Response speed.
In another kind of specific embodiment, refer to Fig. 4, initialization module can include the 4th transistor T4, the 5th crystal
Pipe T5, the 6th transistor T6 and the second pulse signal CK2.Can be by the controlled stage (such as grid) and second of the 4th transistor T4
The controlled stage (such as grid) of transistor T2 coupled to the second pulse signal CK2, and the first order of the 4th transistor T4 (is such as leaked
Level) it coupled to controlled stage.The controlled stage (such as grid) of the 6th transistor T6 coupled to the node Q that boots.So can realize by
Three tunnel dutycycles be 1/3 pulse signal control circuit, four tunnel dutycycles be the pulse control circuit etc. of 1/4, and 4 road duties
Than the overlapping bursts signal control circuit being 1/2.As a example by the pulse signal control circuit that three tunnel dutycycles are 1/3, when using 3
When road dutycycle is the clock pulses control of 1/3, the first order the first pulse signal end output CK1, the second pulse input end input
CK2；The second level the first pulse signal end output CK2, the second pulse input end input CK3；The third level the first pulse signal end is defeated
Go out CK3, the second pulse input end input CK1；Three grades of loop structures.
Secondly, as a example by the pulse signal control circuit that three tunnel dutycycles are 1/3, keep stage, the second arteries and veins at high level
Rushing signal CK2 is low level, and transistor seconds T2 opens, and the high level of the first pulse signal CK1 is given by transistor seconds T2
Bootstrapping node Q charging, such 6th transistor T6 closes.Now the 4th transistor T4 opens, and primary nodal point P becomes low level,
And then the 5th transistor T5 persistently open, such high level keep the stage output OUT [n] high level will be always remained as.This is real
The advantage executing example is:
(1) pulse signal utilizing different duty does control signal can reduce the dynamic power consumption of circuit.This is because use
Control signal of doing the pulse signal of different duty can reduce the frequency of pulse signal in circuit, and then reduces in pulse clock jumping
During change, the dynamic power consumption that the parasitic capacitance being connected with pulse signal produces.
(2) can also be by controlling input pulse signal, it is achieved overlapping output OUT [n].
Fig. 6 is line-scanning drive circuit unit simulation result shown in Fig. 2, be the most successively the first pulse signal CK1,
First input signal IN, bootstrapping node Q output voltage, primary nodal point P output voltage and output signal OUT [1].And be expert at
It is 2000 load resistances that scanning signal OUT [1] outfan has mounted resistance, and capacitance is the load capacitance of 300pF.Fig. 6 shows, this
Line-scanning drive circuit disclosed in embodiment can normally export line scan signals.
Fig. 7 is line-scanning drive circuit unit simulation result shown in Fig. 4, and wherein using three tunnel dutycycles is the pulse of 1/3
Signal does and controls.Analog result figure is followed successively by the first pulse signal CK1, the second pulse signal CK2, the first input letter from top to bottom
Number IN, bootstrapping node Q output voltage, primary nodal point P output voltage and output signal OUT [1].And in line scan signals OUT
[1] outfan has mounted resistance is 2000 load resistances, and capacitance is the load capacitance of 300pF.Fig. 7 shows, the present embodiment is open
The scan drive circuit of structure row as shown in Figure 4 can normally export line scan signals.
In sum, the advantage of line-scanning drive circuit element circuit of the present invention is:
(1) circuit structure is simple, and element circuit is only with 6 P-TFT, 1 electric capacity and 1 tunnel clock signal.Be conducive to
The realization of the active TFT panel of narrow frame.
(2) being compared to traditional circuit uses 2 big driving pipes to realize pull-up pulldown function, and this element circuit uses
One big driving pipe realizes above-mentioned functions, saves circuit area and the big power consumption driving pipe parasitic capacitance to bring.
Embodiment two:
Cascade above-mentioned line-scanning drive circuit unit, disclosure one line-scanning drive circuit.Refer to Fig. 8,
A kind of line-scanning drive circuit structured flowchart disclosed in the embodiment of the present application two, every grade of line-scanning drive circuit unit needs
3 input signals: the first input signal IN, the first pulse signal CK1 or the second pulse signal CK2, high level input GND is at figure
In use VHRepresent, road output signal OUT [n].
Knowable to the single-stage line-scanning drive circuit of Fig. 6, the significant level of line-scanning drive circuit element output signal is
First pulse signal CK1 low level output produces, therefore can determine output signal by regulating the first pulse signal CK1.
Refer to Fig. 9, a kind of line-scanning drive circuit structural representation, wherein OUT disclosed in the embodiment of the present application two
[n] is the output signal of n-th grade of line-scanning drive circuit unit, n=1,2,3,4 ....
This line-scanning drive circuit includes:
The line-scanning drive circuit unit of multiple cascades.
Refer to Figure 10, a kind of line-scanning drive circuit sequencing contro figure disclosed in the embodiment of the present application two.
2 clock lines (CK1, CK2) clock signal needed for transmitting to line-scanning drive circuit unit at different levels.
It is the clock signal of 50% that CK1 Yu CK2 provides two dutycycles.The first of odd level line-scanning drive circuit
Pulse signal is provided by clock cable CK1, and the first pulse signal of even level line-scanning drive circuit is carried by clock line CK2
Supply.
Concrete, the output of the first signal IN of this line-scanning drive circuit unit this line-scanning drive circuit unit advanced
Signal.For m level line-scanning drive circuit, its first signal IN input node is connected to m-1 level line-scanning drive circuit
The signal output part of unit；The first signal that its output signal OUT [m] is connected to m-1 level line-scanning drive circuit unit is defeated
Ingress.
Figure 11 be the line-scanning drive circuit analog result shown in Fig. 9, wherein OUT [1]～OUT [4] be that the first row is to
The line scan signals of four row, and having mounted resistance at every line scans signal output part is 2000 load resistances, and capacitance is
The load capacitance of 300pF.Figure 11 shows, line-scanning drive circuit disclosed in the present embodiment logically true, it is possible to the most defeated
Go out line scan signals.
Shown in sum up, line-scanning drive circuit disclosed in the present application has the advantage that
(1) line-scanning drive circuit element circuit simple in construction, single-stage has only to 6 TFT and 1 electric capacity.
(2) high level maintains module to control the state switching signal of end is multiplexing with output module control signal, then
Overall circuit structure is simple, the realization of the active TFT panel of the narrowest frame.
(3) relative to by line-scanning drive circuit, (n level line-scanning drive circuit unit altogether, as row turntable driving
Circuit) for the active TFT panel that is integrated on TFT panel, save the external pin of nearly n.Therefore, the present embodiment is open
Line-scanning drive circuit for formed narrow frame display floater be extremely advantageous.
The present invention is illustrated by use above specific case, is intended merely to help those skilled in the art
It is well understood by.In the case of without departing from the spirit and scope of the present invention, it is also possible to the detailed description of the invention of the present invention is made
Various deductions, deform and replace.These changes and replacement all will fall in claims of the present invention limited range.
Claims (10)
1. a line-scanning drive circuit integrated for TFT, it is characterised in that include a line-scanning drive circuit unit；
Described line-scanning drive circuit unit includes initialization module (10), drives module (30), input module (20), high level
Maintain module (40) and electric charge sharing module (50)；
Described initialization module (10) is connected, by the signal transmission on earth terminal GND with the first pulse signal end and bootstrapping node Q
To the outfan of line-scanning drive circuit unit, line-scanning drive circuit is initialized；
Described driving module (30) is connected with the first pulse signal end, and the significant level of the first pulse signal is sent to row scanning
The outfan of drive circuit unit；
Described input module (20) is coupled in bootstrapping node Q, the Automatic level control input module of response initial pulse with driving module
The switching state of breaker in middle；
Described high level maintains module (40) for, after line-scanning drive circuit unit output line scan signals, driving module
Line scan signals outfan maintain high level；
Described electric charge sharing module (50) is coupled between bootstrapping node Q and the outfan of line-scanning drive circuit unit, is used for
The state self-adaption ground of responsive trip scan drive circuit unit outfan adjusts the current potential of bootstrapping node Q；
Described line-scanning drive circuit initialization module (10) is connected with input module (20), and the first signal IN passes through input module
(10) it is delivered to drive module (30), after driving module (30) to respond the first signal IN, the first pulse signal is delivered to row and sweeps
Scanning circuit outfan；High level maintains module (40) to be connected with initialization module (10), respectively by signal transmission on earth terminal GND
To the outfan of line-scanning drive circuit unit and output end signal is sent to boot node Q；Described electric charge sharing module
(50) one end is connected with bootstrapping node Q, and the other end is connected with the outfan of line-scanning drive circuit unit.
Line-scanning drive circuit the most according to claim 1, it is characterised in that described initialization module (10) includes the 4th
Transistor T4 and the 6th transistor T6；
After the control pole of the 4th transistor T4 couples with the first pole, it is connected with the first pulse signal end CK1；4th transistor T4's
Second pole coupled to first pole of the 6th transistor T6 and forms primary nodal point P；
Second pole of the 6th transistor T6 coupled to earth terminal GND；The control pole of the 6th transistor T6 coupled to the node Q that boots.
Line-scanning drive circuit the most according to claim 2, it is characterised in that described driving module (30) includes that first is brilliant
Body pipe T1 and the first electric capacity C1；
The control pole of the first transistor (T1) coupled to the node Q that boots；First pole of the first transistor (T1) and the first pulse letter
Number end CK1 be connected；Second pole of the first transistor T1 coupled to output node F；
The two ends of the first electric capacity C1 coupled between the control pole of the first transistor T1 and the second pole.
Line-scanning drive circuit the most according to claim 3, it is characterised in that described input module (20) includes that is trimorphism
Body pipe T3；
Second pole of third transistor T3 coupled to the node Q that boots；The control pole of third transistor T3 couples with the first pole, is used for
The input of the first signal N.
Line-scanning drive circuit the most according to claim 4, it is characterised in that described high level maintains module (40) to include
5th transistor T5；
The pole that controls of the 5th transistor T5 coupled to second pole of the 4th transistor T4；First pole of the 5th transistor T5 coupled to
Output node F；Second pole of the 5th transistor T5 coupled to earth terminal GND.
Line-scanning drive circuit the most according to claim 5, it is characterised in that described electric charge sharing module (50) includes
Two-transistor T2；
The control pole of transistor seconds T2 coupled to the first pulse signal end；First pole of transistor seconds T2 coupled to bootstrapping joint
Point Q；Second pole of transistor seconds T2 coupled to output node F, exports for line-scanning drive circuit unit.
Line-scanning drive circuit the most according to claim 6, it is characterised in that the control pole of described transistor seconds T2,
The control pole of the 4th transistor T4 is the most all connected with the second pulse signal end with first.
8. according to the line-scanning drive circuit described in any one of claim 1-7, it is characterised in that include at least including two levels
The line-scanning drive circuit unit of connection；
The signal output part of prime line-scanning drive circuit unit and the first signal end IN of rear class line-scanning drive circuit unit
It is connected.
9. according to the line-scanning drive circuit described in any one of claim 2-7, it is characterised in that described initialization module (10)
Also include that the two ends of the second electric capacity C2, described second electric capacity C2 connect between the control pole of the 6th transistor and bootstrapping node Q,
And the 4th transistor control pole be connected with one end of the second electric capacity C2.
10. the driving method of a line-scanning drive circuit, it is characterised in that use the row described in any one of claim 1-9
Scan drive circuit, inputs the first signal from input module, from driving module input pulse signal, the ground connection of initialization module
End GND inputs GND signal；
When line-scanning drive circuit be series of rows scan drive circuit unit cascaded time, the first of odd level line-scanning drive circuit
Pulse signal is provided by the first clock signal CK1, and the first pulse signal of even level line-scanning drive circuit is by second clock CK2
There is provided；
When there is the second pulse signal end in line-scanning drive circuit unit, the second pulse letter of odd level line-scanning drive circuit
Number by second clock signal CK2 provide, the second pulse signal of even level line-scanning drive circuit is provided by the first clock CK1；
Wherein, the sequential of second clock signal CK2 and the first clock signal CK1 is contrary.
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| CN201610804907.2A CN106128353B (en) | 2016-09-06 | 2016-09-06 | A kind of line-scanning drive circuit and its driving method that TFT is integrated |
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| CN201610804907.2A CN106128353B (en) | 2016-09-06 | 2016-09-06 | A kind of line-scanning drive circuit and its driving method that TFT is integrated |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109448629A (en) * | 2019-01-10 | 2019-03-08 | 合肥京东方光电科技有限公司 | Shift register cell, gate driving circuit and its driving method |
| CN110992897A (en) * | 2019-12-31 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel driving method, display driving circuit and display panel |
| CN116707278A (en) * | 2023-08-08 | 2023-09-05 | 上海英联电子科技有限公司 | Bootstrap capacitor charging control circuit and DC-DC conversion circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6064713A (en) * | 1996-01-11 | 2000-05-16 | Thomson Lcd | Shift register using "MIS" transistors of like polarity |
| CN101783124A (en) * | 2010-02-08 | 2010-07-21 | 北京大学深圳研究生院 | Grid electrode driving circuit unit, a grid electrode driving circuit and a display device |
| CN102723064A (en) * | 2012-03-28 | 2012-10-10 | 北京大学深圳研究生院 | Driving circuit unit, gate driving circuit and display device |
| CN103226981A (en) * | 2013-04-10 | 2013-07-31 | 京东方科技集团股份有限公司 | Shift register unit and gate driving circuit |
| CN204189456U (en) * | 2014-11-12 | 2015-03-04 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit, display panel |
| CN105632446A (en) * | 2016-03-30 | 2016-06-01 | 京东方科技集团股份有限公司 | GOA unit, driving method thereof, GOA circuit and display device |
-
2016
- 2016-09-06 CN CN201610804907.2A patent/CN106128353B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6064713A (en) * | 1996-01-11 | 2000-05-16 | Thomson Lcd | Shift register using "MIS" transistors of like polarity |
| CN101783124A (en) * | 2010-02-08 | 2010-07-21 | 北京大学深圳研究生院 | Grid electrode driving circuit unit, a grid electrode driving circuit and a display device |
| CN102723064A (en) * | 2012-03-28 | 2012-10-10 | 北京大学深圳研究生院 | Driving circuit unit, gate driving circuit and display device |
| CN103226981A (en) * | 2013-04-10 | 2013-07-31 | 京东方科技集团股份有限公司 | Shift register unit and gate driving circuit |
| CN204189456U (en) * | 2014-11-12 | 2015-03-04 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit, display panel |
| CN105632446A (en) * | 2016-03-30 | 2016-06-01 | 京东方科技集团股份有限公司 | GOA unit, driving method thereof, GOA circuit and display device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109448629A (en) * | 2019-01-10 | 2019-03-08 | 合肥京东方光电科技有限公司 | Shift register cell, gate driving circuit and its driving method |
| CN110992897A (en) * | 2019-12-31 | 2020-04-10 | 深圳市华星光电半导体显示技术有限公司 | Display panel driving method, display driving circuit and display panel |
| CN116707278A (en) * | 2023-08-08 | 2023-09-05 | 上海英联电子科技有限公司 | Bootstrap capacitor charging control circuit and DC-DC conversion circuit |
| CN116707278B (en) * | 2023-08-08 | 2023-10-20 | 上海英联电子科技有限公司 | Bootstrap capacitor charging control circuit and DC-DC conversion circuit |
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| CN106128353B (en) | 2019-07-12 |
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