CN106125433A - A kind of array base palte wire structures, display panels and liquid crystal display - Google Patents
A kind of array base palte wire structures, display panels and liquid crystal display Download PDFInfo
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- CN106125433A CN106125433A CN201610763655.3A CN201610763655A CN106125433A CN 106125433 A CN106125433 A CN 106125433A CN 201610763655 A CN201610763655 A CN 201610763655A CN 106125433 A CN106125433 A CN 106125433A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Nonlinear Science (AREA)
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- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
nullThe present invention provides a kind of array base palte wire structures to include some routing cells，Each routing cell includes the first to Article 8 data wire、The first to Article 5 gate line and film transistor matrix，First、Four、Six and seven data line are the first data wire，Second、Three、Five and eight data line are the second data wire，And the opposite polarity of first and second data wire，First data wire connects the source electrode of the thin film transistor (TFT) of the odd-numbered line odd column in respective sets row and even number line even column，Second data wire connects the source electrode of the thin film transistor (TFT) of the odd-numbered line even column in respective sets row and even number line odd column，Second、Article four, gate line connects the grid of two thin film transistor (TFT)s of the adjacent lines being positioned at the first data wire side，First、Article three and five, gate line connects the grid of two thin film transistor (TFT)s of the adjacent lines being positioned at the second data wire side，So that the opposite polarity of the polarity of each pixel in picture element matrix corresponding to film transistor matrix and the pixel of arbitrary neighborhood.
Description
Technical field
The present invention relates to display field, particularly relate to a kind of array base palte wire structures, display display floater and liquid crystal
Show device.
Background technology
Traditional red, green, blue, Bai Sise LTPS (Low Temperature Poly-silicon, low temperature polycrystalline silicon skill
Art) in Display Technique, in order to reduce limb number and fan-out cabling at the integrated chip of driving, often one is walked by design shunt
Line is divided into 4 data lines, carrys out pixel data line by sequential.Adjacent under but any fan-out line so can be caused to control
The polarity of 4 data lines identical, liquid crystal is accomplished that 4 row reversing mode during polarity inversion, so can be big
Reduce greatly image display quality.The limit that the data wire intersection thread-changing generally using the existing control line of adjacent fan-out improves panel is anti-
Rotary-die type, then the some reversing mode of panel is realized by the polarity inversion of data wire.Picture display matter can be improved although it is so
Amount, but so drive integrated chip can frequently change the polarity of data wire output, thus considerably increase the integrated chip of driving
Driving power consumption.
Summary of the invention
The present invention provides a kind of voltage generation circuit, to reduce the temperature of the data driving chip of LCD TV.The present invention
Also provide for a kind of LCD TV.
The present invention provides kind of an array base palte wire structures, is applied in display panels, described array base palte wire bond
Structure includes that some routing cells, described some routing cells are arranged setting, wherein, each wiring the most successively
Unit includes the first to the Article 8 data wire from left to right arranged, the first to the Article 5 grid arranged the most from top to bottom
Line, and the thin film transistor (TFT) with 4 × 8 matrix form arrangements, first and second data line described forms first group of data wire, institute
State the 3rd and Article 4 data wire form second group of data wire, the described 5th and Article 6 data wire form the 3rd group of data wire,
Described 7th and Article 8 data wire formed the 4th group of data wire, described first, the four, the 6th and Article 7 data wire be first
Data wire, described second, third, the 5th and Article 8 data wire be the second data wire, and the polarity of described first data wire with
The opposite polarity of described second data wire, often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, described first data
Line connects the source electrode of the thin film transistor (TFT) of the odd-numbered line odd column in respective sets row and even number line even column, described second data wire
Connect the odd-numbered line even column in respective sets row and the source electrode of thin film transistor (TFT) of even number line odd column, second, Article 4 grid
Line connects the grid of two thin film transistor (TFT)s of the adjacent lines being positioned at the first data wire side, the first, the 3rd and Article 5 grid
Line connects the grid of two thin film transistor (TFT)s of the adjacent lines being positioned at the second data wire side, so that described thin film transistor (TFT) square
The polarity of each pixel in the picture element matrix that battle array is corresponding and the opposite polarity of the pixel of arbitrary neighborhood；
Wherein, the gate line of described array base palte wire structures opens the last item grid successively from Article 1 gate line
Polar curve is a cycle, and within a cycle, the polarity of all data wires is constant.
Wherein, when described first data wire output positive voltage signal, described second data wire output negative voltage signal；Work as institute
Stating the first data wire and switch to negative voltage signal, described second data wire switches to positive voltage signal the most accordingly.
Wherein, first in the first row to the source electrode of thin film transistor (TFT) of the 8th row be respectively connecting to first, second, the
Four, the three, the six, the five, the 7th and Article 8 data wire on, the first, the four, the 6th and the 7th row thin film in the first row is brilliant
The grid of body pipe is connected to Article 2 gate line, in the first row second, third, the 5th and the 8th grid of row thin film transistor (TFT)
It is connected to Article 1 gate line；In second row first to the source electrode of thin film transistor (TFT) of the 8th row is respectively connecting to second, the
One, the three, the four, the five, the six, the 8th and Article 7 data wire on, in the second row the first, the four, the 6th and the 7th row
The grid of thin film transistor (TFT) is connected to Article 2 gate line, in the second row second, third, the 5th and the 8th row thin film transistor (TFT)
Grid be connected to Article 3 gate line；In the third line first to the source electrode of thin film transistor (TFT) of the 8th row is respectively connecting to the
One, second, the four, the three, the six, the five, the 7th and Article 8 data wire on, in the third line first, the four, the 6th and
The grid of the 7th row thin film transistor (TFT) is connected to Article 2 gate line, in the third line second, third, the 5th and the 8th row thin film
The grid of transistor is connected to Article 3 gate line；In fourth line first connects respectively to the source electrode of the thin film transistor (TFT) of the 8th row
Be connected to second, first, the three, the four, the five, the six, the 8th and Article 7 data wire on, first, the 4th, in fourth line
The grid of the six and the 7th row thin film transistor (TFT) is connected to Article 4 gate line, in fourth line second, third, the 5th and the 8th row
The grid of thin film transistor (TFT) is connected to Article 5 gate line.
The present invention provides a kind of display panels, including:
Some routing cells, described some routing cells are arranged setting, wherein, Mei Yibu the most successively
Line unit includes the first to the Article 8 data wire from left to right arranged, the first to the Article 5 grid arranged the most from top to bottom
Line, and the thin film transistor (TFT) with 4 × 8 formal matrices form arrangements；
Pel array, described pel array includes that some pixel cells, each pixel cell are carried out with 4 × 8 matrix forms
Arrangement, described pixel cell is arranged the most successively, and corresponding corresponding film transistor matrix；
Wherein, first and second data line described forms first group of data wire, the described 3rd and Article 4 data linear
Become second group of data wire, the described 5th and Article 6 data wire the 3rd group of data wire of formation, the described 7th and Article 8 data wire
Form the 4th group of data wire, described first, the four, the 6th and Article 7 data wire be the first data wire, described second, third,
5th and Article 8 data wire be the second data wire, and the polarity phase of the polarity of described first data wire and described second data wire
Instead, often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, and described first data wire connects the odd number in respective sets row
The source electrode of the thin film transistor (TFT) of row odd column and even number line even column, described second data wire connects the odd-numbered line in respective sets row
The source electrode of the thin film transistor (TFT) of even column and even number line odd column, second, Article 4 gate line connect be positioned at the first data wire one
The grid of two thin film transistor (TFT)s of the adjacent lines of side, the first, the 3rd and Article 5 gate line connect be positioned at the second data wire one
The grid of two thin film transistor (TFT)s of the adjacent lines of side, so that every in picture element matrix corresponding to described film transistor matrix
The polarity of one pixel and the opposite polarity of the pixel of arbitrary neighborhood；
Wherein, the gate line of described liquid crystal panel opens the last item gate line successively from Article 1 gate line is one
In the individual cycle, within a cycle, the polarity of described data wire is constant.
Wherein, when described first data wire output positive voltage signal, described second data wire output negative voltage signal；Work as institute
Stating the first data wire and switch to negative voltage signal, described second data wire switches to positive voltage signal the most accordingly.
Wherein, first in the first row to the source electrode of thin film transistor (TFT) of the 8th row be respectively connecting to first, second, the
Four, the three, the six, the five, the 7th and Article 8 data wire on, the first, the four, the 6th and the 7th row thin film in the first row is brilliant
The grid of body pipe is connected to Article 2 gate line, in the first row second, third, the 5th and the 8th grid of row thin film transistor (TFT)
It is connected to Article 1 gate line；In second row first to the source electrode of thin film transistor (TFT) of the 8th row is respectively connecting to second, the
One, the three, the four, the five, the six, the 8th and Article 7 data wire on, in the second row the first, the four, the 6th and the 7th row
The grid of thin film transistor (TFT) is connected to Article 2 gate line, in the second row second, third, the 5th and the 8th row thin film transistor (TFT)
Grid be connected to Article 3 gate line；In the third line first to the source electrode of thin film transistor (TFT) of the 8th row is respectively connecting to the
One, second, the four, the three, the six, the five, the 7th and Article 8 data wire on, in the third line first, the four, the 6th and
The grid of the 7th row thin film transistor (TFT) is connected to Article 2 gate line, in the third line second, third, the 5th and the 8th row thin film
The grid of transistor is connected to Article 3 gate line；In fourth line first connects respectively to the source electrode of the thin film transistor (TFT) of the 8th row
Be connected to second, first, the three, the four, the five, the six, the 8th and Article 7 data wire on, first, the 4th, in fourth line
The grid of the six and the 7th row thin film transistor (TFT) is connected to Article 4 gate line, in fourth line second, third, the 5th and the 8th row
The grid of thin film transistor (TFT) is connected to Article 5 gate line.
The present invention provides a kind of liquid crystal display, including display panels, backlight module and driving control circuit, described
Backlight module is used for providing the light needed for described display panels, described display panels to include some routing cells,
Described some routing cells are arranged setting the most successively, and wherein, each routing cell includes from left to right arranging
The first to the Article 8 data wire of cloth, the first to the Article 5 gate line arranged the most from top to bottom, and with 4 × 8 matrix forms
The thin film transistor (TFT) of arrangement；
Pel array, described pel array includes that some pixel cells, each pixel cell are carried out with 4 × 8 matrix forms
Arrangement, described pixel cell is arranged the most successively, and corresponding corresponding film transistor matrix；Described driving
Control circuit is used for controlling described pel array；
Wherein, first and second data line described forms first group of data wire, the described 3rd and Article 4 data linear
Become second group of data wire, the described 5th and Article 6 data wire the 3rd group of data wire of formation, the described 7th and Article 8 data wire
Form the 4th group of data wire, described first, the four, the 6th and Article 7 data wire be the first data wire, described second, third,
5th and Article 8 data wire be the second data wire, and the polarity phase of the polarity of described first data wire and described second data wire
Instead, often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, and described first data wire connects the odd number in respective sets row
The source electrode of the thin film transistor (TFT) of row odd column and even number line even column, described second data wire connects the odd-numbered line in respective sets row
The source electrode of the thin film transistor (TFT) of even column and even number line odd column, second, Article 4 gate line connect be positioned at the first data wire one
The grid of two thin film transistor (TFT)s of the adjacent lines of side, the first, the 3rd and Article 5 gate line connect be positioned at the second data wire one
The grid of two thin film transistor (TFT)s of the adjacent lines of side, so that every in picture element matrix corresponding to described film transistor matrix
The polarity of one pixel and the opposite polarity of the pixel of arbitrary neighborhood；
Wherein, the gate line of described liquid crystal panel opens the last item gate line successively from Article 1 gate line is one
In the individual cycle, within a cycle, the polarity of described data wire is constant.
Wherein, when described first data wire output positive voltage signal, described second data wire output negative voltage signal；Work as institute
Stating the first data wire and switch to negative voltage signal, described second data wire switches to positive voltage signal the most accordingly.
Wherein, first in the first row to the source electrode of thin film transistor (TFT) of the 8th row be respectively connecting to first, second, the
Four, the three, the six, the five, the 7th and Article 8 data wire on, the first, the four, the 6th and the 7th row thin film in the first row is brilliant
The grid of body pipe is connected to Article 2 gate line, in the first row second, third, the 5th and the 8th grid of row thin film transistor (TFT)
It is connected to Article 1 gate line；In second row first to the source electrode of thin film transistor (TFT) of the 8th row is respectively connecting to second, the
One, the three, the four, the five, the six, the 8th and Article 7 data wire on, in the second row the first, the four, the 6th and the 7th row
The grid of thin film transistor (TFT) is connected to Article 2 gate line, in the second row second, third, the 5th and the 8th row thin film transistor (TFT)
Grid be connected to Article 3 gate line；In the third line first to the source electrode of thin film transistor (TFT) of the 8th row is respectively connecting to the
One, second, the four, the three, the six, the five, the 7th and Article 8 data wire on, in the third line first, the four, the 6th and
The grid of the 7th row thin film transistor (TFT) is connected to Article 2 gate line, in the third line second, third, the 5th and the 8th row thin film
The grid of transistor is connected to Article 3 gate line；In fourth line first connects respectively to the source electrode of the thin film transistor (TFT) of the 8th row
Be connected to second, first, the three, the four, the five, the six, the 8th and Article 7 data wire on, first, the 4th, in fourth line
The grid of the six and the 7th row thin film transistor (TFT) is connected to Article 4 gate line, in fourth line second, third, the 5th and the 8th row
The grid of thin film transistor (TFT) is connected to Article 5 gate line.
Wherein, described driving control circuit includes:
Gate drivers, is arranged at the side of described display panels, and is coupled in the institute of described display panels
There is described gate line, provide scanning signal in order to sequence；
Source electrode driver, couples all data wires of described display panels, in order to provide multiple video data；And
Time schedule controller, couples and controls described gate drivers and source electrode driver.
The array base palte wire structures of the present invention, described array base palte wire structures includes some routing cells, if described
Dry routing cell is arranged setting the most successively, and wherein, each routing cell includes from left to right arranged
One to Article 8 data wire, the first to the Article 5 gate line arranged the most from top to bottom, and with 4 × 8 matrix form arrangements
Thin film transistor (TFT), first and second data line described forms first group of data wire, the described 3rd and the formation of Article 4 data wire
Second group of data wire, the described 5th and Article 6 data wire formed the 3rd group of data wire, the described 7th and Article 8 data linear
Become the 4th group of data wire, described first, the four, the 6th and Article 7 data wire be the first data wire, described second, third,
Five and Article 8 data wire be the second data wire, and the polarity phase of the polarity of described first data wire and described second data wire
Instead, often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, and described first data wire connects the odd number in respective sets row
The source electrode of the thin film transistor (TFT) of row odd column and even number line even column, described second data wire connects the odd-numbered line in respective sets row
The source electrode of the thin film transistor (TFT) of even column and even number line odd column, second, Article 4 gate line connect be positioned at the first data wire one
The grid of two thin film transistor (TFT)s of the adjacent lines of side, the first, the 3rd and Article 5 gate line connect be positioned at the second data wire one
The grid of two thin film transistor (TFT)s of the adjacent lines of side, so that every in picture element matrix corresponding to described film transistor matrix
The polarity of one pixel and the opposite polarity of the pixel of arbitrary neighborhood.Therefore, present invention achieves a reversion, improve liquid crystal
Show the quality of the display picture of panel.It addition, opening the last item gate line successively from Article 1 gate line is a cycle,
Within a cycle, the polarity of all data wires is constant, thus decreases the polarity switching frequency of data wire, and then reduces and drive
The driving power consumption of the driving chip of dynamic data wire.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to
Other accompanying drawing is obtained according to these accompanying drawings.
The schematic diagram of the array base palte wire structures that Fig. 1 provides for first aspect of the present invention embodiment.
Fig. 2 is the schematic diagram of the routing cell in Fig. 1.
Fig. 3 is the polarity design sketch of the pixel cell that routing cell is corresponding.
Fig. 4 is the schematic diagram of the routing cell after the data wire polarity switching in routing cell.
Fig. 5 is the polarity design sketch of the pixel cell that the routing cell of Fig. 4 is corresponding.
The schematic diagram of the display panels that Fig. 6 provides for second aspect of the present invention embodiment.
The block diagram of the liquid crystal display that Fig. 7 provides for third aspect of the present invention embodiment.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Referring to Fig. 1 and Fig. 2, first aspect of the present invention embodiment provides a kind of array base palte wire structures 100.Described
Array base palte wire structures 100 is applied in display panels.Described array base palte wire structures 100 includes that some wirings are single
Unit 200, described some routing cells 200 are arranged setting the most successively.Wherein, each routing cell 200 wraps
The first to the Article 5 grid include the first to the Article 8 data wire D1-D8 the most from left to right arranged, arranging the most from top to bottom
Polar curve G1-G5, and the thin film transistor (TFT) 30 with 4 × 8 matrix form arrangements.Described first and second data line D1 and D2 is formed
First group of data wire 10, the described 3rd and Article 4 data wire D3 and D4 forms second group of data wire 10.Described 5th and the 6th
Data line D5 and D6 forms the 3rd group of data wire 10, and the described 7th and Article 8 data wire D7 and D8 forms the 4th group of data wire
10, described first, the four, the 6th and Article 7 data wire D1, D4, D6 and D7 be the first data wire 11.Described second, third,
5th and Article 8 data wire D2, D3, D5 and D8 be the second data wire 12, and described first data wire 11 and described second data
The opposite polarity of line 12.Often the group corresponding two row thin film transistor (TFT)s of data wire 10 form one group of row 40.Described first data wire 11 is even
Connect the source electrode of the thin film transistor (TFT) 30 of the odd-numbered line odd column in respective sets row 40 and even number line even column.Described second data wire
The source electrode of 12 thin film transistor (TFT)s 30 connecting the odd-numbered line even column in respective sets row and even number line odd column.The second, Article 4
Gate lines G 2, G4 connect the grid of two thin film transistor (TFT)s 30 of the adjacent lines being positioned at the first data wire 11 side.The first, the 3rd
And Article 5 gate lines G 1, G3, G5 connect the grid of two thin film transistor (TFT)s 30 of the adjacent lines being positioned at the second data wire 12 side
Pole, so that the pixel of the polarity of each pixel in picture element matrix corresponding to described film transistor matrix and arbitrary neighborhood
Opposite polarity.Wherein, the gate line 30 of described array base palte wire structures opens the N article successively from Article 1 gate lines G 1
Gate lines G n is a cycle, and within a cycle, the polarity of all data wires is constant.
It should be noted that described gate line 30 is for controlling the keying of described thin film transistor (TFT) 30.Described first and
Thin film transistor (TFT) 30 is charged after opening at corresponding thin film transistor (TFT) 30 by two data wires 11 and 12.When brilliant to thin film
When body pipe 30 is charged data wire output positive voltage signal, the polarity of the pixel of described thin film transistor (TFT) 30 correspondence is just.When
When thin film transistor (TFT) 30 is charged data wire output negative voltage signal, the polarity of the pixel of described thin film transistor (TFT) 30 correspondence
It is negative.
In the present embodiment, described first data wire 11 connects the odd-numbered line odd column in respective sets row 40 and even number line is even
The source electrode of the thin film transistor (TFT) 30 of ordered series of numbers.Described second data wire 12 connects the odd-numbered line even column in respective sets row and even number line
The source electrode of the thin film transistor (TFT) 30 of odd column.The second, Article 4 gate lines G 2, G4 connects the phase being positioned at the first data wire 11 side
The grid of two thin film transistor (TFT)s 30 of adjacent rows.The first, the 3rd and Article 5 gate lines G 1, G3, G5 connect be positioned at the second data
The grid of two thin film transistor (TFT)s 30 of the adjacent lines of line 12 side, so that the pixel square that described film transistor matrix is corresponding
The polarity of each pixel in Zhen and the opposite polarity of the pixel of arbitrary neighborhood.Therefore, present invention achieves a reversion, improve
The quality of the display picture of display panels.It addition, open the N article gate lines G n successively from Article 1 gate lines G 1 it is
In one cycle, within a cycle, the polarity of all groups of data wires is constant, thus decreases the polarity switching frequency of data wire,
And then reduce the driving power consumption of the driving chip of driving data line.
In the present embodiment, described first polarity is positive pole.Described second polarity is negative pole.In other embodiments, institute
Stating the first polarity can also be for negative pole, and described second polarity can also be positive pole.After the polarity of the most all data wires switches over,
The polarity of each pixel in described picture element matrix is the most contrary with the polarity of the pixel of arbitrary neighborhood, therefore, and all data
The polarity switching of line does not haves scintillation, does not interferes with the quality of the display picture of display panels.
Specifically, first in the first row to the source electrode of thin film transistor (TFT) 30 of the 8th row be respectively connecting to first, second,
Four, the three, the six, the five, the 7th and Article 8 data wire D1, D2, D4, D3, D6, D5, D7 and D8 on.In the first row
One, the grid of the four, the 6th and the 7th row thin film transistor (TFT) 30 is connected to Article 2 gate lines G 2.In the first row second,
Three, the grid of the 5th and the 8th row thin film transistor (TFT) 30 is connected to Article 1 gate lines G 1.In second row first is to the 8th row
The source electrode of thin film transistor (TFT) 30 be respectively connecting to second, first, the three, the four, the five, the six, the 8th and Article 7 data
On line D2, D1, D3, D4, D5, D6, D8 and D7.The grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) 30 in the second row
Pole is connected to Article 2 gate lines G 2.In second row second, third, the 5th and the 8th row thin film transistor (TFT) 30 grid connect
To Article 3 gate lines G 3.In the third line first to the source electrode of thin film transistor (TFT) 30 of the 8th row is respectively connecting to first, the
Two, the four, the three, the six, the five, the 7th and Article 8 data wire D1, D2, D4, D3, D6, D5, D7 and D8 on.The third line
In the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) 30 be connected to Article 2 gate lines G 2.In the third line
Two, the grid of the thin film transistor (TFT) 30 of the three, the 5th and the 8th row is connected to Article 3 gate lines G 3；In fourth line first to
The source electrode of the thin film transistor (TFT) 30 of the 8th row is respectively connecting to second, first, the three, the four, the five, the six, the 8th and the 7th
On data line D2, D1, D3, D4, D5, D6, D8 and D7.The first, the four, the 6th and the 7th row thin film transistor (TFT) in fourth line
The grid of 30 is connected to Article 4 gate lines G 4.In fourth line second, third, the 5th and the 8th grid of row thin film transistor (TFT) 30
Pole is connected to Article 5 gate lines G 5.
In the present embodiment, the routing cell 200 source electrode driver at display panels and the driving of gate drivers
Under so that the polarity of each pixel in the picture element matrix that described film transistor matrix is corresponding and the pixel of arbitrary neighborhood
Opposite polarity.Therefore, present invention achieves a reversion (refering to Fig. 3), improve the quality of the display picture of display panels.
It addition, opening the N article gate line successively from Article 1 gate line 30 is a cycle, within a cycle, described M group data
The polarity of line is constant, thus decreases the polarity switching frequency of data wire, and then reduces the driving chip driving M group data wire
Driving power consumption.
In the present embodiment, described first polarity is positive pole, and described second polarity is negative pole.In other embodiments,
The polarity of described data wire can switch over, and if the first polarity is negative pole, described second polarity is positive pole, and the present invention still may be used
To realize some reversion (such as Fig. 4 and Fig. 5).The principle of reversion is identical with the inversion principle in the present embodiment.
Referring to Fig. 6, second aspect of the present invention provides a kind of display panels 400.Described display panels 400 wraps
Including some routing cells, described some routing cells are arranged setting, wherein, each routing cell the most successively
200 include the first to the Article 8 data wire D1-D8 the most from left to right arranged, arrange the most from top to bottom first to the 5th
Bar gate lines G 1-G5, and the thin film transistor (TFT) 30 with 4 × 8 matrix form arrangements.
Pel array, described pel array includes that some pixel cells, each pixel cell are carried out with 4 × 8 matrix forms
Arrangement.Described pixel cell 50 is arranged the most successively, and corresponding corresponding film transistor matrix.
Described first and second data line D1 and D2 forms first group of data wire 10, the described 3rd and Article 4 data wire
D3 and D4 forms second group of data wire 10.Described 5th and Article 6 data wire D5 and D6 forms the 3rd group of data wire 10, described
7th and Article 8 data wire D7 and D8 forms the 4th group of data wire 10, described first, the four, the 6th and Article 7 data wire
D1, D4, D6 and D7 are the first data wire 11.Described second, third, the 5th and Article 8 data wire D2, D3, D5 and D8 be second
Data wire 12, and the opposite polarity of described first data wire 11 and described second data wire 12.Often corresponding two row of group data wire 10
Thin film transistor (TFT) forms one group of row 40.Described first data wire 11 connects the odd-numbered line odd column in respective sets row 40 and even number line
The source electrode of the thin film transistor (TFT) 30 of even column.Described second data wire 12 connects the odd-numbered line even column in respective sets row and even number
The source electrode of the thin film transistor (TFT) 30 of row odd column.The second, Article 4 gate lines G 2, G4 connection is positioned at the first data wire 11 side
The grid of two thin film transistor (TFT)s 30 of adjacent lines.The first, the 3rd and Article 5 gate lines G 1, G3, G5 connect be positioned at second number
According to the grid of two thin film transistor (TFT)s 30 of the adjacent lines of line 12 side, so that the pixel that described film transistor matrix is corresponding
The polarity of each pixel in matrix and the opposite polarity of the pixel of arbitrary neighborhood.Wherein, described array base palte wire structures
Gate line 30 to open the N article gate lines G n successively from Article 1 gate lines G 1 be a cycle, within a cycle, all
The polarity of data wire is constant.
It should be noted that described gate line 30 is for controlling the keying of described thin film transistor (TFT) 30.Described first and
Thin film transistor (TFT) 30 is charged after opening at corresponding thin film transistor (TFT) 30 by two data wires 11 and 12.When brilliant to thin film
When body pipe 30 is charged data wire output positive voltage signal, the polarity of the pixel of described thin film transistor (TFT) 30 correspondence is just.When
When thin film transistor (TFT) 30 is charged data wire output negative voltage signal, the polarity of the pixel of described thin film transistor (TFT) 30 correspondence
It is negative.
In the present embodiment, described first data wire 11 connects the odd-numbered line odd column in respective sets row 40 and even number line is even
The source electrode of the thin film transistor (TFT) 30 of ordered series of numbers.Described second data wire 12 connects the odd-numbered line even column in respective sets row and even number line
The source electrode of the thin film transistor (TFT) 30 of odd column.The second, Article 4 gate lines G 2, G4 connects the phase being positioned at the first data wire 11 side
The grid of two thin film transistor (TFT)s 30 of adjacent rows.The first, the 3rd and Article 5 gate lines G 1, G3, G5 connect be positioned at the second data
The grid of two thin film transistor (TFT)s 30 of the adjacent lines of line 12 side, so that the pixel square that described film transistor matrix is corresponding
The polarity of each pixel in Zhen and the opposite polarity of the pixel of arbitrary neighborhood.Therefore, present invention achieves a reversion, improve
The quality of the display picture of display panels.It addition, open the N article gate lines G n successively from Article 1 gate lines G 1 it is
In one cycle, within a cycle, the polarity of all groups of data wires is constant, thus decreases the polarity switching frequency of data wire,
And then reduce the driving power consumption of the driving chip of driving data line, therefore present invention reduces the power consumption of display panels 400.
Referring to Fig. 7, third aspect of the present invention provides a kind of liquid crystal display 500.Described liquid crystal display includes liquid crystal
Display floater 400, backlight module 510 and driving control circuit 520.Described backlight module 510 is used for providing described liquid crystal display
Light needed for panel 400.The display panels 400 that described display panels provides for above-mentioned alternative plan.Due to institute
State display panels 400 to be described in detail in above-mentioned alternative plan embodiment, therefore do not repeat them here.Described
Control circuit 520 is driven to be used for controlling described pel array.
Further, described driving control circuit 520 also includes gate drivers, source electrode driver and time schedule controller.
Described gate drivers is arranged at the side of described display panels, and is coupled in all described of described display panels
Gate line, provides scanning signal in order to sequence.Described source electrode driver couples all data wires of described display panels, uses
To provide multiple video datas.Described time schedule controller couples and controls described gate drivers and source electrode driver.
In the present embodiment, the often group data wire 10 of described liquid crystal display includes the first data wire 11 and the second data wire
12, described first data wire 11 and the opposite polarity of described second data wire 12.The often group corresponding two row film crystals of data wire 10
Pipe forms one group of row 40.Described first data wire 11 connects the odd-numbered line odd column in respective sets row 40 and even number line even column
The source electrode of thin film transistor (TFT) 30.Described second data wire 12 connects the odd-numbered line even column in respective sets row and even number line odd column
The source electrode of thin film transistor (TFT) 30.The second, Article 4 gate lines G 2, G4 connects the adjacent lines being positioned at first data wire 11 side
The grid of two thin film transistor (TFT)s 30.The first, the 3rd and Article 5 gate lines G 1, G3, G5 connect be positioned at the second data wire 12 1
The grid of two thin film transistor (TFT)s 30 of the adjacent lines of side, so that in picture element matrix corresponding to described film transistor matrix
The polarity of each pixel and the opposite polarity of the pixel of arbitrary neighborhood.Therefore, present invention achieves a reversion, improve liquid crystal
The quality of the display picture of display floater 400.It addition, it addition, open the N article gate lines G n successively from Article 1 gate lines G 1
Being a cycle, within a cycle, the polarity of all groups of data wires is constant, thus decreases the polarity switching frequency of data wire
Rate, and then reduce the driving power consumption of the driving chip of driving data line, therefore present invention reduces display panels 400
Power consumption, i.e. reduces the power consumption of described liquid crystal display 500.
Above disclosed it is only one preferred embodiment of the present invention, certainly can not limit the power of the present invention with this
Profit scope, one of ordinary skill in the art will appreciate that all or part of flow process realizing above-described embodiment, and weighs according to the present invention
Profit requires the equivalent variations made, and still falls within the scope that invention is contained.
Claims (10)
1. an array base palte wire structures, is applied in display panels, it is characterised in that: described array base palte wire bond
Structure includes that some routing cells, described some routing cells are arranged setting, wherein, each wiring the most successively
Unit includes the first to the Article 8 data wire from left to right arranged, the first to the Article 5 grid arranged the most from top to bottom
Line, and the thin film transistor (TFT) with 4 × 8 matrix form arrangements, first and second data line described forms first group of data wire, institute
State the 3rd and Article 4 data wire form second group of data wire, the described 5th and Article 6 data wire form the 3rd group of data wire,
Described 7th and Article 8 data wire formed the 4th group of data wire, described first, the four, the 6th and Article 7 data wire be first
Data wire, described second, third, the 5th and Article 8 data wire be the second data wire, and the polarity of described first data wire with
The opposite polarity of described second data wire, often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, described first data
Line connects the source electrode of the thin film transistor (TFT) of the odd-numbered line odd column in respective sets row and even number line even column, described second data wire
Connect the odd-numbered line even column in respective sets row and the source electrode of thin film transistor (TFT) of even number line odd column, second, Article 4 grid
Line connects the grid of two thin film transistor (TFT)s of the adjacent lines being positioned at the first data wire side, the first, the 3rd and Article 5 grid
Line connects the grid of two thin film transistor (TFT)s of the adjacent lines being positioned at the second data wire side, so that described thin film transistor (TFT) square
The polarity of each pixel in the picture element matrix that battle array is corresponding and the opposite polarity of the pixel of arbitrary neighborhood；
Wherein, the gate line of described array base palte wire structures opens the last item gate line successively from Article 1 gate line
Being a cycle, within a cycle, the polarity of all data wires is constant.
2. array base palte wire structures as claimed in claim 1, it is characterised in that when described first data wire output positive voltage
Signal, described second data wire output negative voltage signal；When described first data wire switches to negative voltage signal, described second number
Positive voltage signal is switched to the most accordingly according to line.
3. array base palte wire structures as claimed in claim 2, it is characterised in that it is thin that first in the first row to the 8th arranges
The source electrode of film transistor be respectively connecting to first, second, the four, the three, the six, the five, the 7th and Article 8 data wire on,
The grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in a line is connected to Article 2 gate line, in the first row
Two, the grid of the three, the 5th and the 8th row thin film transistor (TFT) is connected to Article 1 gate line；In second row first is to the 8th row
The source electrode of thin film transistor (TFT) be respectively connecting to second, first, the three, the four, the five, the six, the 8th and Article 7 data wire
On, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in the second row is connected to Article 2 gate line, the second row
In second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 3 gate line；In the third line first to
The source electrode of thin film transistor (TFT) of the 8th row be respectively connecting to first, second, the four, the three, the six, the five, the 7th and the 8th
On data line, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in the third line is connected to Article 2 grid
Line, in the third line second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 3 gate line；Fourth line
In the source electrode of thin film transistor (TFT) of the first to the 8th row be respectively connecting to second, first, the 3rd, the 4th, the 5th, the 6th, the
Eight and Article 7 data wire on, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in fourth line is connected to the 4th
Bar gate line, in fourth line second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 5 gate line.
4. a display panels, including:
Some routing cells, described some routing cells arrange setting the most successively, and wherein, each wiring is single
Unit includes the first to the Article 8 data wire from left to right arranged, the first to the Article 5 gate line arranged the most from top to bottom,
And the thin film transistor (TFT) with 4 × 8 formal matrices form arrangements；
Pel array, described pel array includes that some pixel cells, each pixel cell are arranged with 4 × 8 matrix forms,
Described pixel cell is arranged the most successively, and corresponding corresponding film transistor matrix；
Wherein, first and second data line described forms first group of data wire, the described 3rd and Article 4 data wire form the
Two groups of data wires, the described 5th and Article 6 data wire the 3rd group of data wire of formation, the described 7th and the formation of Article 8 data wire
4th group of data wire, described first, the four, the 6th and Article 7 data wire be the first data wire, described second, third, the 5th
And Article 8 data wire is the second data wire, and the opposite polarity of the polarity of described first data wire and described second data wire,
Often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, and the odd-numbered line that described first data wire connects in respective sets row is strange
The source electrode of the thin film transistor (TFT) of ordered series of numbers and even number line even column, described second data wire connects the odd-numbered line even number in respective sets row
Row and the source electrode of thin film transistor (TFT) of even number line odd column, second, Article 4 gate line connects and be positioned at the first data wire side
The grid of two thin film transistor (TFT)s of adjacent lines, the first, the 3rd and Article 5 gate line connect be positioned at the second data wire side
The grid of two thin film transistor (TFT)s of adjacent lines, so that each in picture element matrix corresponding to described film transistor matrix
The polarity of pixel and the opposite polarity of the pixel of arbitrary neighborhood；
Wherein, the gate line of described liquid crystal panel opens the last item gate line successively from Article 1 gate line is a week
Phase, within a cycle, the polarity of described data wire is constant.
5. display panels as claimed in claim 4, it is characterised in that when described first data wire output positive voltage letter
Number, described second data wire output negative voltage signal；When described first data wire switches to negative voltage signal, described second data
Line switches to positive voltage signal the most accordingly.
6. display panels as claimed in claim 5, it is characterised in that the thin film of first in the first row to the 8th row is brilliant
The source electrode of body pipe be respectively connecting to first, second, the four, the three, the six, the five, the 7th and Article 8 data wire on, the first row
In the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) be connected to Article 2 gate line, in the first row second,
The grid of the three, the 5th and the 8th row thin film transistor (TFT) is connected to Article 1 gate line；In second row first is to the 8th row
The source electrode of thin film transistor (TFT) be respectively connecting to second, first, the three, the four, the five, the six, the 8th and Article 7 data wire on,
The grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in the second row is connected to Article 2 gate line, in the second row
Second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 3 gate line；In the third line first is to the 8th
The source electrode of thin film transistor (TFT) of row be respectively connecting to first, second, the four, the three, the six, the five, the 7th and Article 8 number
According on line, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in the third line is connected to Article 2 gate line, the
In three row second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 3 gate line；In fourth line
The source electrode of thin film transistor (TFT) of one to the 8th row is respectively connecting to the second, first, the 3rd, the 4th, the 5th, the 6th, the 8th and the
On seven data line, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in fourth line is connected to Article 4 grid
Line, in fourth line second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 5 gate line.
7. a liquid crystal display, including display panels, backlight module and driving control circuit, described backlight module is used for
The light needed for described display panels, described display panels is provided to include some routing cells, described some wirings
Unit is arranged setting the most successively, and wherein, each routing cell includes first to from left to right arranged
Eight data line, the first to the Article 5 gate line arranged the most from top to bottom, and the thin film with 4 × 8 matrix form arrangements is brilliant
Body pipe；
Pel array, described pel array includes that some pixel cells, each pixel cell are arranged with 4 × 8 matrix forms,
Described pixel cell is arranged the most successively, and corresponding corresponding film transistor matrix；Described driving controls
Circuit is used for controlling described pel array；
Wherein, first and second data line described forms first group of data wire, the described 3rd and Article 4 data wire form the
Two groups of data wires, the described 5th and Article 6 data wire the 3rd group of data wire of formation, the described 7th and the formation of Article 8 data wire
4th group of data wire, described first, the four, the 6th and Article 7 data wire be the first data wire, described second, third, the 5th
And Article 8 data wire is the second data wire, and the opposite polarity of the polarity of described first data wire and described second data wire,
Often the corresponding two row thin film transistor (TFT)s of group data wire form one group of row, and the odd-numbered line that described first data wire connects in respective sets row is strange
The source electrode of the thin film transistor (TFT) of ordered series of numbers and even number line even column, described second data wire connects the odd-numbered line even number in respective sets row
Row and the source electrode of thin film transistor (TFT) of even number line odd column, second, Article 4 gate line connects and be positioned at the first data wire side
The grid of two thin film transistor (TFT)s of adjacent lines, the first, the 3rd and Article 5 gate line connect be positioned at the second data wire side
The grid of two thin film transistor (TFT)s of adjacent lines, so that each in picture element matrix corresponding to described film transistor matrix
The polarity of pixel and the opposite polarity of the pixel of arbitrary neighborhood；
Wherein, the gate line of described liquid crystal panel opens the last item gate line successively from Article 1 gate line is a week
Phase, within a cycle, the polarity of described data wire is constant.
8. liquid crystal display as claimed in claim 7, it is characterised in that when described first data wire output positive voltage signal,
Described second data wire output negative voltage signal；When described first data wire switches to negative voltage signal, described second data wire
Switch to positive voltage signal the most accordingly.
9. liquid crystal display as claimed in claim 8, it is characterised in that the film crystal of first in the first row to the 8th row
The source electrode of pipe be respectively connecting to first, second, the four, the three, the six, the five, the 7th and Article 8 data wire on, in the first row
The grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) be connected to Article 2 gate line, second, in the first row
Three, the grid of the 5th and the 8th row thin film transistor (TFT) is connected to Article 1 gate line；In second row first is thin to the 8th row
The source electrode of film transistor be respectively connecting to second, first, the three, the four, the five, the six, the 8th and Article 7 data wire on,
The grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in two row is connected to Article 2 gate line, in the second row
Two, the grid of the three, the 5th and the 8th row thin film transistor (TFT) is connected to Article 3 gate line；In the third line first is to the 8th row
The source electrode of thin film transistor (TFT) be respectively connecting to first, second, the four, the three, the six, the five, the 7th and Article 8 data
On line, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in the third line is connected to Article 2 gate line, and the 3rd
In row second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 3 gate line；In fourth line first
Source electrode to the 8th thin film transistor (TFT) arranged is respectively connecting to second, first, the three, the four, the five, the six, the 8th and the 7th
On data line, the grid of the first, the four, the 6th and the 7th row thin film transistor (TFT) in fourth line is connected to Article 4 grid
Line, in fourth line second, third, the 5th and the 8th the grid of row thin film transistor (TFT) be connected to Article 5 gate line.
10. liquid crystal display as claimed in claim 9, it is characterised in that described driving control circuit includes:
Gate drivers, is arranged at the side of described display panels, and is coupled in all institutes of described display panels
State gate line, provide scanning signal in order to sequence；
Source electrode driver, couples all data wires of described display panels, in order to provide multiple video data；And
Time schedule controller, couples and controls described gate drivers and source electrode driver.
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| CN106773407A (en) * | 2016-12-29 | 2017-05-31 | 深圳市华星光电技术有限公司 | Display panel and preparation method thereof |
| CN108335683A (en) * | 2018-03-14 | 2018-07-27 | 北京集创北方科技股份有限公司 | source electrode driver, liquid crystal display device and driving method |
| CN111142298A (en) * | 2020-01-20 | 2020-05-12 | 合肥鑫晟光电科技有限公司 | Array substrate and display device |
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