CN106125033A - A kind of voltage x current synchronicity classification error testing system - Google Patents
A kind of voltage x current synchronicity classification error testing system Download PDFInfo
- Publication number
- CN106125033A CN106125033A CN201610574352.7A CN201610574352A CN106125033A CN 106125033 A CN106125033 A CN 106125033A CN 201610574352 A CN201610574352 A CN 201610574352A CN 106125033 A CN106125033 A CN 106125033A
- Authority
- CN
- China
- Prior art keywords
- voltage
- module
- current
- synchronicity
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/02—Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R21/00—Arrangements for measuring electric power or power factor
- G01R21/006—Measuring power factor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
Abstract
The invention discloses a kind of voltage x current synchronicity classification error testing system, described system includes: main processor modules, FPGA module, voltage conversion acquisition circuit module, synchronization module, fiber optic serial sending module, fiber optic Ethernet receiver module, solve and prior art exists the technical problem that power-factor angle cannot carry out precise and high efficiency test, achieve system reasonable in design, it is possible to the technique effect that power-factor angle is tested of precise and high efficiency.
Description
Technical field
The present invention relates to intelligent substation electronic mutual inductor accuracy technical field of measurement and test, in particular it relates to a kind of electricity
Current voltage synchronicity classification error testing system.
Background technology
At present, signal is delivered to a voltage combining unit (PT by electronic type voltage transformer by the voltage in intelligent station
MU), then by PT MU, voltage signal is delivered to multiple interval MU and cascade, the interval MU voltage by PT MU and the electricity at this interval
Type current transformer (CT) carries out synchronizing to merge exporting again, and multiple interval MU carry out Network Transmitting by switch again and reach
Bay level IED equipment, is shown in the PT MU shown in accompanying drawing and interval MU.
The amplitude accuracy of the electronic mutual inductor of intelligent station is the most relatively stable, whether through cascade or network,
Higher stability can be always maintained in amplitude, do not affected by transmission mode.And the relative phase between voltage and current signal
Position relation, i.e. power-factor angle, but suffer from the impact of cascade and networking model, power-factor angle the most accurately direct relation
Accuracy to electric energy metrical.Based on electronic mutual inductor the digital electric energy metered system often occurred and tradition electric energy metrical
The most slowly there is increasing electric energy difference in system, also tends to there is error with the power-factor angle of MU output relevant
System.
In the at present debugging of intelligent station and detection, only for electronic current mutual inductor and electronic type voltage transformer
Independent accuracy test, lack the special testing scheme to power-factor angle and means, it is impossible to primary side boost while
Current transformer primary side injecting power factor angle is adjustable controlled big electric current, leaves hidden to the safe and stable operation of system
Suffer from.
In sum, present inventor is in realizing the embodiment of the present application during inventive technique scheme, in discovery
At least there is following technical problem in technology of stating:
There is the technical problem that power-factor angle cannot be carried out precise and high efficiency test in the prior art.
Summary of the invention
The invention provides a kind of voltage x current synchronicity classification error testing system, solve and prior art exists nothing
Method carries out the technical problem of precise and high efficiency test to power-factor angle, it is achieved that system is reasonable in design, it is possible to precise and high efficiency right
Power-factor angle carries out the technique effect tested.
For solving above-mentioned technical problem, the embodiment of the present application provides a kind of voltage x current synchronicity classification error testing system
System, described system includes:
On the one hand main processor modules, described main processor modules is used for: run (SuSE) Linux OS, man-machine to system
Interface is managed, harvester Frame group bag, tested combining unit frame receive and resolves；Described main processor modules the opposing party
Face is used for: markers processes, consecutive frame sending value calculates, consecutive frame delivery time calculates, power factor error calculates；
FPGA module, described FPGA module controls for input and the output of system data；
Voltage conversion acquisition circuit module, described voltage conversion acquisition circuit module is used for carrying out voltage conversion, will conversion
After voltage through low-pass filtering conditioning loop after carry out AD sampling；
Synchronization module, described synchronization module for for main processor modules, FPGA module, analog-digital converter provide various not
The operation work tempo of same frequency demand, output 1PPS and IRIG-B code is to tested combining unit simultaneously；
Fiber optic serial sending module, described fiber optic serial sending module has been used for the serial data frame that FPGA module controls
Electricity change to light, it is achieved the analog data frame of Multi-path electricity type current transformer body harvester sends；
Fiber optic Ethernet receiver module, described fiber optic Ethernet receiver module has been used for the light of the tested combining unit of multichannel
Fine Ethernet data receives.
Wherein, voltage conversion acquisition circuit module is all connected with FPGA module, synchronization module, FPGA module and optical fiber ether
Net receiver module is all connected with main processor modules, and FPGA module is connected with fiber optic serial sending module.
Wherein, described main processor modules specifically includes: ARM module and DSP module, described ARM module and described DSP mould
Block connects, described ARM module be used for running (SuSE) Linux OS, system man-machine interface is managed, harvester Frame group
Bag, tested combining unit frame receive and resolve；Described DSP module processes for markers, consecutive frame sending value calculates, consecutive frame is sent out
Send the moment to calculate, power factor error calculates.
Wherein, described FPGA module specifically for: complete multi-channel optical fibre serial ports Frame send, it is achieved multichannel electric current is mutual
The harvester simulation of sensor, controls the reading sequential of analog-digital converter ADC, the sampled value of each ADC is demarcated current time index, will
Primary processor is given in target sampled value during each band.
Wherein, primary side high pressure is changed by described voltage conversion acquisition circuit module specifically for: voltage standard transformer
Becoming the voltage of specified 100V/ √ 3, this voltage enters voltage conversion acquisition circuit module, first by the voltage transformer of 0.01 grade
Completing the 100V/ √ 3 conversion to 5V voltage, 5V voltage nurses one's health loop through low-pass filtering, enters AD sampling element, the work of sampling
Clock synchronization module is come from as clock.
Wherein, AD sampling is carried out under the sequencing contro of synchronization module, obtains sample Du1, T2 moment at moment T1
Obtain Du2, by that analogy, consume during primary side high-voltage signal occurs to the sampling completing this voltage signal, be whole
Definitely delay time is set to Td_u, Td_u less than 50us.
Wherein, power factor error is:
E=(cos (θ t)-cos (θ)) * 100/cos (θ) (1), wherein, θ t is voltage x current angle, and cos (θ t) is tested
The power factor of MU, θ is power-factor angle.
The one or more technical schemes provided in the embodiment of the present application, at least have the following technical effect that or advantage:
1, true electronic type voltage transformer test can be carried out from the boosting of bus, reach with real working conditions without
Difference is tested.
2, based on primary voltage high accuracy conversion with collection, Multi-path electricity type current transformer is locked with voltage-phase
The sequential of simulation data, reaches the effect once flowed up while primary side boosting, and solving current intelligent station cannot be same
Time boosting and up-flow restriction, solve the test blindspot that cannot be carried out power factor angular accuracy.
3, the delay time parameter with actual electronic current mutual inductor accurately controls the current sampling data of simulation data
Output time, test result is consistent with the actual running results.
4, by the size of regulation current simulations output time delay, comprehensively missing under different power-factor angles is reached
Difference test.
5, it is the angle of phase test from power-factor angle essence, avoids the amplitude test in transformer codomain, specially
Note in phase test so that this programme is feasible and efficient.
6, the merit under method of testing goes for different transformer principle, different transformer producer, different networking model
Rate factor error testing；
7, MU at different levels output is concurrently accessed test system, can show in single test that power factor at different levels is by mistake
Difference, it is simple to the power factor error analyzing intelligent station specifically in which link produces, it is simple to fault location and solution.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing being further appreciated by the embodiment of the present invention, constitutes of the application
Point, it is not intended that the restriction to the embodiment of the present invention；
Fig. 1 is the composition schematic diagram of voltage x current synchronicity classification error testing system in the embodiment of the present application one.
Detailed description of the invention
The invention provides a kind of voltage x current synchronicity classification error testing system, solve and prior art exists nothing
Method carries out the technical problem of precise and high efficiency test to power-factor angle, it is achieved that system is reasonable in design, it is possible to precise and high efficiency right
Power-factor angle carries out the technique effect tested.
In order to be better understood from technique scheme, below in conjunction with Figure of description and specific embodiment to upper
State technical scheme to be described in detail.
Below in conjunction with specific embodiment and accompanying drawing, to the detailed description further of present invention work, but the enforcement of the present invention
Mode is not limited to this.
Embodiment one:
Refer to Fig. 1, this application provides a kind of voltage x current synchronicity classification error testing system, this test system master
To be made up of following main functional module:
ARM+DSP main processor modules:
The primary processor of system uses the DM3730 of TI company, and it is by ARM Cortex-A8Core and 800MHz of 1GHz
TMS320C64x+DSP Core two parts composition, ARM end be mainly responsible for (SuSE) Linux OS, device man-machine interface management,
Harvester Frame group bag, tested combining unit frame receive with parsing, DSP be substantially carried out the bigger markers of workload process,
The calculating of consecutive frame sending value, the calculating of consecutive frame delivery time, power factor error calculating etc..Application layer (the application journey of ARM side
Sequence) and signal processing layer (computing of DSP side) between by Codec Engine software module connect, compiling DSP end can hold
When line code and ARM end application program, it is all based on Codec Engine and carries out.
FPGA module:
FPGA uses xilinx company Spartan6 series of X C6SLC150, and FPGA has good sequencing contro performance, main
Input and the output of system bottom data to be responsible for control.FPGA completes the Frame of multi-channel optical fibre serial ports and sends, it is achieved multichannel
The harvester simulation of current transformer, the occurrence of Frame and frame format are all precalculated by primary processor and tissue completes.
FPGA is simultaneously need to control the reading sequential of analog-digital converter ADC, by the sampled value Accurate Calibration current time index of each ADC, and will
Primary processor is given in target sampled value during each band.
Voltage conversion acquisition circuit module:
Primary side high pressure accurate transformation is become the voltage of specified 100V/ √ 3 by voltage standard transformer, and this voltage enters " electricity
Pressure conversion acquisition circuit " module.First this module is completed turning of 100V/ √ 3 to 5V small voltage by the voltage transformer of 0.01 grade
Changing, 5V small voltage nurses one's health loop through low-pass filtering, enters AD sampling element.A/D acquisition chip uses 24 of TI company
ADS1271, this ADC are the Delta-Sigma ADC of high s/n ratio, and the work clock of sampling comes from clock synchronization module.
Synchronization module:
Synchronization module provides the operation work tempo of various different frequency demands for system primary processor, FPGA, ADC etc.,
Output 1PPS and IRIG-B code is to tested combining unit simultaneously, and high-precision clock synchronization module ensure that whole system sequence controls
Accuracy, and long-term stability.Crystal oscillator select OCXO50 constant-temperature crystal oscillator, the operating temperature of-40 to 85 degree,
Less than the temperature drift characteristic of 1ppb, the low phase noise of-160dBc/1KHz, maximum 10ppb/year's is low aging.
Fiber optic serial sending module:
" electric " of the serial data frame that fiber optic serial sending module completes FPGA control arrives the conversion of " light ", it is achieved Multi-path electricity
The analog data frame of type current transformer body harvester sends.Use the HFBR-1414 optical transmitter of Avago company, symbol
Close IEEE 802.3 Ethernet 802.5 Token Ring standard High Performance emitter, include low noise across resistance prime amplifier,
The maximum data rate is up to 175MBd, and longer transmission distance reaches 4km.
Fiber optic Ethernet receiver module:
Completing the fiber optic Ethernet data receiver of the tested combining unit of multichannel, transceiver uses the AFBR5803 of Agilent,
Ensure to have enough bandwidth and response speed, typical case's rising and falling time to reach 2ns.PHY chip uses Intel Company
LXT971, it is 10/100M double speed quick ether controller, compatible IEEE802.3；Support 10Base5,10Base2,
10BaseT, 100BASE-X, 100BASE-TX, 100BASE-FX, and can automatically detect connected medium.
The function of each module and annexation and test philosophy are as follows:
First primary side bus boosting: alternating current 220V voltage is accessed pressure regulator, it is achieved power-frequency voltage regulates, and pressure regulator is defeated
Go out to access booster system.Booster system, according to tested electronic type PT electric pressure, is come by testing transformer or resonator system
Realizing boosting, High voltage output accesses bus.
By the high-precision voltage standard transformer of accuracy class 0.01 grade, primary side high pressure accurate transformation is become 100V/
The voltage-measurable of √ 3, this voltage enters " voltage conversion acquisition circuit " module of test system.Test system is by internal 0.01
The voltage transformer of level completes the conversion of 100V/ √ 3 to 5V, enters AD sampling module.Angular difference according to 0.01 grade of transformer is by mistake
Difference limit value understands, and after Two Stages, the error control of the voltage signal change of disease adds 0.3 point at 0.3 point, and i.e. maximum phase error is 0.6
Within Fen, this phase error is negligible.
5V signal enters AD behind signal condition loop and gathers, and AD sampling is carried out under the sequencing contro of synchronization module,
Obtaining sample Du1 at moment T1, the T2 moment obtains Du2, by that analogy.Occur to completing this electricity from primary side high-voltage signal
The sampling of pressure signal, whole during time (absolute delay time) of consuming be set to Td_u, this delay time may determine that tool
Body value, can accomplish no more than 50us and stablize.This value is less than the time delay of current domestic all electronic current mutual inductor bodies
Time, for controlling the precondition that the simulation data of electronic current mutual inductor provides feasible below.By voltage sample value meter
Calculate real-time frequency value f of current voltage signal.
This test system emulation output is electronic current mutual inductor body digital signal, between accessing from Practical Project
Every MU1 and the absolute delay time of the electronic type CT acquiring product parameters CT body of interval MU2, it is set to Td_ct1 and Td_ct2,
Foundation as emulation.
While primary side boosts, export by emulating actual electronic current mutual inductor, it is achieved while boosting
Carry out the true effect flowed up.To this end, control the simulation data of electronic current mutual inductor on the basis of voltage sample value.First
First voltage sample value is carried out amplitude transformation, as the instantaneous sampling value of current simulations output, then according to reality to be emulated
Electronic current mutual inductor absolute delay time parameter controls the sequential of simulation data.
As a example by the electronic current mutual inductor of dummy spacings MU1 exports, the sampled value in T1 moment is transformed to Di 1=ka*
Du1, T2 instance sample value is transformed to Di2=ka*Du2, by that analogy.By electronic current mutual inductor and voltage signal acquisition
Absolute delay difference Δ T1=Td_ct1-Td_u control the output time of each sampled point, by equal for each sampled point
Time delay Δ T1 sends, i.e. Di 1 sends at T1+ Δ T1, and Di2 sends at T2+ Δ T1.
The electronic current mutual inductor simulation data instantaneous value of interval MU2 is Di 1=kb*Du1, Di2=kb*
Du2 ..., each sampled point time delay Δ T2=Td_ct2-Td_u sends.
Emulation send realize serial communication based on " FPGA module " control " fiber optic serial sending module ", agreement follow by
The output protocol of anti-true electronic current mutual inductor.
Above-mentioned test can realize primary voltage and current in phase position, i.e. power-factor angle θ=0, the situation of cos θ=1,
It is not the situation of 0 to simulate θ, delay time Δ T1 and the Δ T2 that above-mentioned electric current exports need to be adjusted, i.e. Δ T1'=Δ
T1+ θ/2 π f, Δ T2'=Δ T2+ θ/2 π f, f is the above-mentioned frequency values calculated, and now test is exactly system power factor
Situation for cos θ.
It is technique effect 2 herein, the particular content of 3,4 and realize principle.
Measured signal is divided into three grades, i.e. PT combining unit output stage, is spaced combining unit output stage, and network output
Level, is shown in " optic fiber transceiver module " received signal in accompanying drawing." synchronization module " send 1PPS or IRIG-B code to MU at different levels,
Fiber optic Ethernet module receives three grades of tested IEC61850-9-2 sampling value messages, and " ARM+DSP main processor modules " is from often
Calculating its voltage x current angle theta t in the sampled value output of individual MU, the power factor of the most tested MU is cos (θ t), final merit
Rate factor error is:
E=(cos (θ t)-cos (θ)) * 100/cos (θ)
It is the particular content of technique effect 7 herein and realizes principle.
The parts selection of each functional module is as follows:
Test system primary processor uses the DM3730 microprocessor of TI company, and it is by the ARM Cortex-of 1GHz
TMS320C64x+DSP Core two parts composition of A8Core and 800MHz, and it is integrated with 3D graphic process unit, video accelerator
(IVA), USB 2.0, supports MMC/SD card, serial ports etc..
FPGA uses the XC6SLC150 of xilinx company, belongs to Spartan6 series, has 147,443 logical blocks,
Compared with previous generation Spartan series, this series power consumption be only its 50%, and speed faster, linkage function more rich comprehensively.Energy
The pair register 6 enough providing brand-new and more efficient inputs look-up table (LUT) logic and a series of abundant built-in system level module.
ARM end mainly runs (SuSE) Linux OS, and DSP is substantially carried out Digital Signal Processing.
Ethernet controller is Intel Company LXT971.LXT971 is that the quick ether of single port 10/100M double speed controls
Device, its compatible IEEE802.3；Support 10Base5,10Base2,10BaseT, 100BASE-X, 100BASE-TX, 100BASE-
FX, and can automatically detect connected medium, select Agilent AFBR5803 as fiber optic network transceiver.
A/D acquisition chip uses the ADS1271 of TI company to be acquired signal as analog-digital converter, and this ADC is
24,50KHz bandwidth, the Delta-Sigma ADC of high s/n ratio.
OCXO50 constant-temperature crystal oscillator selected by the crystal oscillator of synchronization module, and the operating temperature of-40 to 85 degree, less than 1ppb's
Temperature drift characteristic, the low phase noise of-160dBc/1KHz, maximum 10ppb/year's is low aging, and High Precision Crystal Oscillator is primary processor
Timeticks is provided, it is ensured that the accuracy of sequencing contro, and long-term stability with FPGA.
The one or more technical schemes provided in the embodiment of the present application, at least have the following technical effect that or advantage:
1, true electronic type voltage transformer test can be carried out from the boosting of bus, reach with real working conditions without
Difference is tested.
2, based on primary voltage high accuracy conversion with collection, Multi-path electricity type current transformer is locked with voltage-phase
The sequential of simulation data, reaches the effect once flowed up while primary side boosting, and solving current intelligent station cannot be same
Time boosting and up-flow restriction, solve the test blindspot that cannot be carried out power factor angular accuracy.
3, the delay time parameter with actual electronic current mutual inductor accurately controls the current sampling data of simulation data
Output time, test result is consistent with the actual running results.
4, by the size of regulation current simulations output time delay, comprehensively missing under different power-factor angles is reached
Difference test.
5, it is the angle of phase test from power-factor angle essence, avoids the amplitude test in transformer codomain, specially
Note in phase test so that this programme is feasible and efficient.
6, the merit under method of testing goes for different transformer principle, different transformer producer, different networking model
Rate factor error testing；
7, MU at different levels output is concurrently accessed test system, can show in single test that power factor at different levels is by mistake
Difference, it is simple to the power factor error analyzing intelligent station specifically in which link produces, it is simple to fault location and solution.
Although preferred embodiments of the present invention have been described, but those skilled in the art once know basic creation
Property concept, then can make other change and amendment to these embodiments.So, claims are intended to be construed to include excellent
Select embodiment and fall into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. a voltage x current synchronicity classification error testing system, it is characterised in that described system includes:
Main processor modules, on the one hand described main processor modules is used for: run (SuSE) Linux OS, to system man-machine interface
Be managed, harvester Frame group bag, tested combining unit frame receive and resolve；On the other hand described main processor modules is used
In: markers processes, consecutive frame sending value calculates, consecutive frame delivery time calculates, power factor error calculates；
FPGA module, described FPGA module controls for input and the output of system data；
Voltage conversion acquisition circuit module, described voltage conversion acquisition circuit module is used for carrying out voltage conversion, after conversion
Voltage carries out AD sampling behind low-pass filtering conditioning loop；
Synchronization module, described synchronization module is for providing various different frequency for main processor modules, FPGA module, analog-digital converter
The operation work tempo of rate demand, output 1PPS and IRIG-B code is to tested combining unit simultaneously；
Fiber optic serial sending module, described fiber optic serial sending module has been used for the electricity of the serial data frame that FPGA module controls
Change to light, it is achieved the analog data frame of Multi-path electricity type current transformer body harvester sends；
Fiber optic Ethernet receiver module, described fiber optic Ethernet receiver module be used for the optical fiber of the tested combining unit of multichannel with
Too network data receives.
Voltage x current synchronicity classification error testing system the most according to claim 1, it is characterised in that described main process
Device module specifically includes: ARM module and DSP module, and described ARM module is connected with described DSP module, and described ARM module is used for
Run (SuSE) Linux OS, system man-machine interface is managed, harvester Frame group bag, tested combining unit frame receive
With parsing；Described DSP module processes for markers, consecutive frame sending value calculates, consecutive frame delivery time calculates, power factor is missed
Difference calculates.
Voltage x current synchronicity classification error testing system the most according to claim 1, it is characterised in that described FPGA mould
Block specifically for: the Frame completing multi-channel optical fibre serial ports sends, it is achieved the simulation of the harvester of Multi-path electricity current transformer, controls mould
The reading sequential of number converter ADC, demarcates current time index by the sampled value of each ADC, will send during each band in target sampled value
To primary processor.
Voltage x current synchronicity classification error testing system the most according to claim 1, it is characterised in that described voltage turns
Change acquisition circuit module and specifically for: voltage standard transformer, primary side high pressure is converted into the voltage of specified 100V/ √ 3, should
Voltage enters voltage conversion acquisition circuit module, is first completed turning of 100V/ √ 3 to 5V voltage by the voltage transformer of 0.01 grade
Changing, 5V voltage nurses one's health loop through low-pass filtering, enters AD sampling element, and the work clock of sampling comes from clock and synchronizes mould
Block.
Voltage x current synchronicity classification error testing system the most according to claim 4, it is characterised in that AD sampling is same
Carrying out under the sequencing contro of step module, obtain sample Du1 at moment T1, the T2 moment obtains Du2, by that analogy, from once
Side high-voltage signal occurs to the sampling completing this voltage signal, whole during the absolute delay time that consumes be set to Td_u, Td_
U is less than 50us, is calculated real-time frequency value f of current voltage signal by voltage sample value.
Voltage x current synchronicity classification error testing system the most according to claim 5, it is characterised in that at primary side liter
While pressure, export by emulating actual electronic current mutual inductor, on the basis of voltage sample value, control electronic current
The simulation data of transformer, first carries out amplitude transformation to voltage sample value, as the instantaneous sampling value of current simulations output, so
After the actual electronic current mutual inductor absolute delay time parameter that emulates as required to control the sequential of simulation data.
Voltage x current synchronicity classification error testing system the most according to claim 6, it is characterised in that interval MU1 and
The absolute delay time of interval MU2 is set to: Td_ct1 and Td_ct2, and the sampled value in interval MU1T1 moment is transformed to Di1=
Ka*Du1, T2 instance sample value is transformed to Di2=ka*Du2, by that analogy, by electronic current mutual inductor and voltage signal
The absolute delay difference Δ T1=Td_ct1-Td_u gathered controls the output time of each sampled point, each is sampled
The equal time delay Δ T1 of point sends；
The electronic current mutual inductor simulation data instantaneous value of interval MU2 is Di1=kb*Du1, Di2=kb*Du2, with this type of
Pushing away, each sampled point time delay Δ T2=Td_ct2-Td_u sends；
Carrying out primary voltage and current phase angle is θ test, the delay time Δ T1 and the Δ T2 that are exported by electric current are adjusted, i.e.
Δ T1'=Δ T1+ θ/2 π f, Δ T2'=Δ T2+ θ/2 π f, f are the electric voltage frequency value calculated；
Emulation sends and carries out serial communication based on FPGA module control fiber optic serial sending module.
Voltage x current synchronicity classification error testing system the most according to claim 1, it is characterised in that by defeated for MU at different levels
Going out to be concurrently accessed test system, main processor modules calculates its voltage x current angle theta t from MU sampled values at different levels export,
The power factor of the most tested MU output is cos (θ t), and power factor error is:
E=(cos (θ t)-cos (θ)) * 100/cos (θ) (1), wherein, θ is system power factor angle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610574352.7A CN106125033B (en) | 2016-07-19 | 2016-07-19 | A kind of voltage and current synchronism classification error testing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610574352.7A CN106125033B (en) | 2016-07-19 | 2016-07-19 | A kind of voltage and current synchronism classification error testing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106125033A true CN106125033A (en) | 2016-11-16 |
| CN106125033B CN106125033B (en) | 2018-11-02 |
Family
ID=57290203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610574352.7A Active CN106125033B (en) | 2016-07-19 | 2016-07-19 | A kind of voltage and current synchronism classification error testing system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106125033B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111122942A (en) * | 2019-12-13 | 2020-05-08 | 珠海博杰电子股份有限公司 | Low current test system |
| CN114935887A (en) * | 2022-07-25 | 2022-08-23 | 星河动力(北京)空间科技有限公司 | Distributed signal acquisition device and carrier rocket |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122422A1 (en) * | 2004-06-04 | 2008-05-29 | Iwatt Inc. | Parallel Current Mode Control Using a Direct Duty Cycle Algorithm with Low Computational Requirements to Perform Power Factor Correction |
| CN201886095U (en) * | 2010-11-11 | 2011-06-29 | 中国电力科学研究院 | Test device of merging unit |
| CN103487695A (en) * | 2013-09-26 | 2014-01-01 | 国家电网公司 | Detection device for merging unit based on analog input |
| CN104198977A (en) * | 2014-08-06 | 2014-12-10 | 国家电网公司 | Accuracy detection method based on average power error for analog input combining unit |
-
2016
- 2016-07-19 CN CN201610574352.7A patent/CN106125033B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080122422A1 (en) * | 2004-06-04 | 2008-05-29 | Iwatt Inc. | Parallel Current Mode Control Using a Direct Duty Cycle Algorithm with Low Computational Requirements to Perform Power Factor Correction |
| CN201886095U (en) * | 2010-11-11 | 2011-06-29 | 中国电力科学研究院 | Test device of merging unit |
| CN103487695A (en) * | 2013-09-26 | 2014-01-01 | 国家电网公司 | Detection device for merging unit based on analog input |
| CN104198977A (en) * | 2014-08-06 | 2014-12-10 | 国家电网公司 | Accuracy detection method based on average power error for analog input combining unit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111122942A (en) * | 2019-12-13 | 2020-05-08 | 珠海博杰电子股份有限公司 | Low current test system |
| CN114935887A (en) * | 2022-07-25 | 2022-08-23 | 星河动力(北京)空间科技有限公司 | Distributed signal acquisition device and carrier rocket |
| CN114935887B (en) * | 2022-07-25 | 2022-11-18 | 星河动力(北京)空间科技有限公司 | Distributed signal acquisition device and carrier rocket |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106125033B (en) | 2018-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103278791B (en) | The electronic mutual inductor amplitude phase error check system that Networkable detects | |
| CN103792508B (en) | The error testing system of the digitized measurement device and method of testing | |
| CN103543430B (en) | Standard modulus synchronous signal source | |
| CN101149425B (en) | Electronic electric energy meter debugging, checkout automated system | |
| CN103336264B (en) | Digital electric energy meter quantity value tracing system based on analog quantity detection and digital electric energy meter quantity value tracing method based analog quantity detection | |
| CN202443082U (en) | Merging unit test system with analog input and university | |
| CN103792419B (en) | Realize analog quantity and mix the synchronous sampling method accessed with digital quantity | |
| WO2014194518A1 (en) | Digital power source based on iec61850-9 sampling value and detection method thereof | |
| CN203465409U (en) | Standard analog-digital synchronization signal source | |
| CN105203983A (en) | Flexible alternating current/direct current electronic transformer checking device based on mixed sampling | |
| CN105548769B (en) | A kind of relay protection action delay placement test system and method | |
| CN103884931B (en) | A kind of substation bus bar part throttle characteristics test recording equipment | |
| CN205067713U (en) | Flexible alternating current -direct current electronic transformer calibration equipment based on mix sampling | |
| CN108132455A (en) | Global error check system based on combining unit | |
| CN104155545A (en) | Multichannel analog quantity acquisition module based on GPS signals | |
| CN104215803A (en) | Synchronous standard source and control method applied to distributive type intelligent testing platform | |
| CN101893695B (en) | Analog sampling and protocol generating devices | |
| CN106125033B (en) | A kind of voltage and current synchronism classification error testing system | |
| CN203191430U (en) | Multifunctional electric power parameter display instrument based on DSP | |
| CN202600133U (en) | Digital quantity input electric energy meter calibration system capable of supporting synchronous analog quantity source tracing | |
| CN101950009A (en) | Three-phase intelligent transformer calibrator | |
| CN203101505U (en) | Metering monitoring system based on wireless communication technology | |
| CN201788275U (en) | Analog sampling and protocol generating device | |
| CN204086419U (en) | A kind of merge cells tester multichannel analog amount Acquisition Circuit | |
| CN204330836U (en) | A kind of synchronization criterion source for distributed intelligence test platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |