CN106101585B - Low-noise CCD camera circuit - Google Patents
Low-noise CCD camera circuit Download PDFInfo
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- CN106101585B CN106101585B CN201610601095.1A CN201610601095A CN106101585B CN 106101585 B CN106101585 B CN 106101585B CN 201610601095 A CN201610601095 A CN 201610601095A CN 106101585 B CN106101585 B CN 106101585B
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- 238000006243 chemical reaction Methods 0.000 claims description 10
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/618—Noise processing, e.g. detecting, correcting, reducing or removing noise for random or high-frequency noise
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract
The invention relates to a low-noise CCD camera circuit, which comprises an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology; the analog front-end circuit comprises a blocking capacitor C, a preceding-stage in-phase amplifying circuit QF and an RC low-pass filtering switch KG with adjustable bandwidth; the pre-stage amplifying circuit QF comprises an operational amplifier U; the resistor R is connected with the non-inverting input end of the operational amplifier U; the resistor R1 and the resistor R2 are connected with the reverse input end of the operational amplifier U; the Schottky diode D is connected with the resistor R2 and the reverse input end of the operational amplifier U in parallel; the resistor RS1 and the resistor RS2 are connected with the output end of the operational amplifier U; the switch Ks and the capacitor Cs form a bandwidth adjustable switch KG; the invention provides a low-noise CCD camera circuit which has small volume, light weight, low power consumption, strong anti-interference capability, high safety and reliability, flexible design and strong expansion capability, can effectively reduce noise and improve the dynamic range of a CCD camera.
Description
Technical Field
The invention belongs to the photoelectric field, relates to a low-noise CCD camera circuit implementation method and a low-noise CCD camera circuit implementation system, and particularly relates to a CCD remote sensing camera circuit aiming at the astronomical observation and deep space exploration fields with low noise requirements.
Background
The CCD has the characteristics of high quantum efficiency, good linearity, low noise and the like, and is widely applied to the fields of aerospace and the like, particularly the fields of low illumination, low-light target astronomical observation and the like. However, noise has become a major obstacle to the task of weak light observation, and with the continuous development of miniaturization and integration of CCD devices, the increase in the number of CCD photosensitive elements necessitates a reduction in the area of the photosensitive elements, thereby reducing the output saturation signal of the CCD. In order to expand the dynamic range of the CCD, the noise of the CCD camera must be reduced, otherwise, the CCD camera cannot be applied to the astronomical observation task of a high-precision and low-light target.
The noise of a CCD camera system is summarized mainly to include photon noise, reset noise, dark current noise, thermal noise, off-chip amplifier noise, 1/f noise, and quantization noise. Where photon noise is the CCD intrinsic noise, which characterizes the limit of the highest signal-to-noise ratio of the CCD camera system. The CCD thermal noise and the dark current can be effectively reduced by refrigerating the CCD. The rest of the reset noise, 1/f noise and AD quantization noise can be minimized by the low noise circuit design.
Disclosure of Invention
In order to solve the technical problems in the background art, the invention provides the low-noise CCD camera circuit which has the advantages of small size, light weight, low power consumption, strong anti-interference capability, high safety and reliability, flexible design and strong expansion capability, can effectively reduce noise and improve the dynamic range of the CCD camera.
The technical solution of the invention is as follows: a low noise CCD camera circuit, characterized by: the CCD camera circuit comprises an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology;
the analog front-end circuit comprises a blocking capacitor C, a preceding-stage in-phase amplification circuit QF and a bandwidth-adjustable RC low-pass filtering switch KG; the pre-stage amplifying circuit QF comprises an operational amplifier U; the resistor R is connected with the non-inverting input end of the operational amplifier U; the resistor R1 and the resistor R2 are connected with the reverse input end of the operational amplifier U; the Schottky diode D is connected with the resistor R2 and the reverse input end of the operational amplifier U in parallel; the resistor RS1 and the resistor RS2 are connected with the output end of the operational amplifier U; the switch Ks and the capacitor Cs form a bandwidth adjustable switch KG; the Ks analog switch is switched on and off according to the phase relation of the current CCD video signal output voltage waveform, so that the bandwidth of the analog front end is changed;
the CCD camera digital sampling circuit comprises a high-speed ADC and an FPGA; the high-speed ADC samples and converts analog to digital to CCD signal reference level and pixel level, and the FPGA realizes ADC high-speed sampling control, digital low-pass filtering and digital CDS.
The high-speed ADC is used for correlated double sampling, if the pixel clock frequency of the CCD is f CcD Then, thenSampling frequency f SAMPLE ＝2f CCD I.e. 2 times the pixel clock frequency.
The digital low-pass filter LP is implemented in the FPGA by adopting a plurality of sampling points to average, 2n sampling points are collected under the condition allowed by a time sequence relation, then the average is taken, and high-frequency noise introduced by an analog front end is removed and quantization noise is reduced.
Also comprises digital CDS which is the difference between the reference level and the pixel level sampling point and suppresses the reset noise and low frequency noise of CCD video signal, and is realized in the form of digital subtracter which is used for converting the reference level of CCD signal into conversion value S ref And a pixel level conversion value S pix And carrying out subtraction operation to obtain a required digital image.
The invention has the advantages that: the device has the advantages of small volume, light weight, low power consumption, strong anti-interference capability, high safety and reliability, flexible design and strong expansion capability; the noise can be effectively reduced, and the dynamic range of the CCD camera is improved. The FPGA is adopted to realize high-speed sampling, digital low-pass filtering and digital CDS, so that high-frequency noise introduced by an analog front end can be further removed, quantization noise is reduced, and correlated noise among pixels can be effectively removed. Meanwhile, the FPGA is adopted for realization, and the device has the advantages of simple structure and convenience in realization.
Drawings
FIG. 1 is a schematic diagram of an analog front-end circuit with adjustable bandwidth according to the present invention;
FIG. 2 is a diagram of CCD video signal output voltage waveforms in accordance with the present invention;
FIG. 3 is a schematic diagram of a low noise digital sampling circuit based on CDS technology according to the present invention;
FIG. 4 is a digital sample timing diagram of the present invention;
Detailed Description
The invention provides a low-noise CCD camera circuit realization method and a system thereof, which are composed of an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology.
1. An analog front end circuit; as shown in fig. 1. The low-pass filter circuit consists of a blocking capacitor, a pre-stage amplifying circuit QF and a bandwidth-adjustable RC low-pass filter switch KG. Since the output signal of the CCD is a negative spatially discrete analog signal floating at a dc level (typically tens of volts). If this signal is used directly for post-amplification and analog-to-digital conversion, the amplifier and ADC are easily saturated, and extraction of a useful signal is not facilitated, so that it is necessary to perform pre-processing such as blocking and amplification on this signal. The patent provides an analog front-end circuit with adjustable bandwidth, wherein C is a pre-amplification circuit QF formed by a blocking capacitor, U, R1, R2 and D, and aims to adjust the signal level to be within the input range of a high-speed analog-to-digital converter; d: and the Schottky diode is used for filtering out a part of reset pulse spikes. And the RS1, the RS2, the Ks and the Cs form a bandwidth adjustable switch KG. The Ks analog switch is opened and closed to switch according to the phase relation of the current CCD video signal output voltage waveform, so that the bandwidth of the analog front end is changed. The turning frequency of the RC low-pass filter is f0=1/2 pi RC, and the position of the turning frequency is changed along with RC. If the capacitance of the capacitor is not changed, the resistance value of the low-pass resistor is reduced from RS1 to RS2, and the turning frequency is translated to the high-frequency end.
The characteristics of the output signal of the CCD: some high frequency components (reset spikes) are included in the reset pulse a as shown in fig. 2, while the reference level B and the pixel level C are relatively stable. To further reduce the noise of the analog front end, the bandwidth switch is switched according to the phase relationship of the CCD output signal. When the reset pulse comes, KS hits RS1, the turning frequency of the RC low-pass filter is low, and high-frequency components in the reset pulse can be effectively filtered; when the reference level and the pixel level come, KS hits RS2, and the corner frequency of the RC low-pass filter is high, so that the CCD reference level and the pixel level pass through as lossless as possible.
2. Low noise digital sampling circuit based on CDS technique:
as shown in fig. 3, it consists of a high-speed ADC and an FPGA. The digital sampling circuit of the CCD camera aims to acquire accurate CCD signals and reduce the noise of the CCD as much as possible. Since the reset noise is the most dominant interference source in the CCD output signal and can be suppressed by applying a peripheral sampling processing circuit, the reset noise can be effectively filtered by the correlated double sampling technique, so the CCD camera sampling circuit generally employs an analog domain CDS circuit.
The circuit consists of a high-speed ADC and an FPGA. The circuit firstly performs high-speed analog-to-digital conversion, secondly performs low-pass filtering (LP) of a sampling signal in a digital domain, and finally performs digital subtraction in the digital domain to realize correlated double adoption. The advantage of performing CDS processing in the digital domain is that the digital subtractor is more accurate. The circuit has few (2) types of selected components, and the reliability of the circuit is greatly improved. In addition, the types of the analog-to-digital converters can be selected more, so that the flexibility of circuit design can be increased.
The purpose of the high speed ADC is to sample and analog-to-digital convert the CCD signal reference level and the pixel level. Due to correlated double sampling, if the pixel clock frequency of CCD is f CcD Then the sampling frequency f SAMPLE ＝2f CCD I.e. 2 times the pixel clock frequency. The maximum operating frequency of the analog-to-digital converter is therefore chosen to be at least 2 times the pixel clock frequency. The number of bits of the analog-to-digital converter is selected according to the dynamic range of the CCD signal and the application requirement.
Digital low pass filter (LP): the implementation form adopts a plurality of sampling points to average, and as the implementation is realized in the FPGA, under the condition that the time sequence relation allows, 2n sampling points are generally collected, as shown in figure 3, and then the average is obtained
High-frequency noise introduced by the analog front end can be further removed, and quantization noise is reduced;
digital CDS: in effect the difference between the reference level and the pixel level sampling point. Reset noise and low-frequency noise of the CCD video signal can be effectively suppressed. The implementation form is a digital subtractor. The digital subtracter is used to convert CCD signal reference level into S ref And a pixel level conversion value S pix Carrying out subtraction to obtain the required digital image S img ＝S pix S ref . Due to S ref And S pix The analog-to-digital conversion is carried out in time sequence, so that the digital subtracter only needs to carry out subtraction processing on the current conversion value and the conversion value at the previous moment.
Claims (4)
1. A low noise CCD camera circuit, characterized by: the CCD camera circuit comprises an analog front-end circuit with adjustable bandwidth and a CCD camera digital sampling circuit based on CDS technology;
the analog front-end circuit comprises a blocking capacitor C, a preceding-stage in-phase amplification circuit QF and a bandwidth-adjustable RC low-pass filtering switch KG; the pre-stage amplifying circuit QF comprises an operational amplifier U; the resistor R is connected with the non-inverting input end of the operational amplifier U; the resistor R1 and the resistor R2 are connected with the reverse input end of the operational amplifier U; a Schottky diode D connected with the resistor R2 and the reverse input end of the operational amplifier U in parallel; one ends of the resistor RS1 and the resistor RS2 are connected with the output end of the operational amplifier U; the switch Ks and the capacitor Cs form a bandwidth adjustable switch KG; one end of the switch Ks is connected with the other end of the resistor RS1 or the resistor RS 2; the other end of the switch Ks is connected with one end of the capacitor Cs; the other ends of the resistor R, the resistor R1 and the capacitor Cs are grounded;
the opening and closing of the switch Ks are switched according to the phase relation of the current CCD video signal output voltage waveform, and the bandwidth of the analog front end is changed; when the reset pulse comes, the switch KS is driven to the resistor RS1, the turning frequency of the RC low-pass filter is low, and high-frequency components in the reset pulse are filtered; when the reference level and the pixel level come, the switch KS is driven to the resistor RS2, the turning frequency of the RC low-pass filter is high, and the CCD reference level and the pixel level pass through without loss;
the CCD camera digital sampling circuit comprises a high-speed ADC and an FPGA; the high-speed ADC samples and converts analog to digital to CCD signal reference level and pixel level, and the FPGA realizes ADC high-speed sampling control, digital low-pass filtering and digital CDS.
2. The low noise CCD camera circuit of claim 1, wherein: the high-speed ADC is related double sampling, if the pixel clock frequency of the CCD is
Then sampling frequency
I.e. 2 times the pixel clock frequency.
3. The low noise CCD camera circuit of claim 2, wherein: the digital low-pass filter LP is implemented in the FPGA by adopting a plurality of sampling points to average, 2n sampling points are collected under the condition allowed by a time sequence relation, then the average is taken, and high-frequency noise introduced by an analog front end is removed and quantization noise is reduced.
4. A low noise CCD camera circuit as recited in claim 3, wherein: also comprises a digital CDS which is the difference between the reference level and the pixel level sampling point and suppresses the reset noise and low frequency noise of the CCD video signal, and is realized in the form of a digital subtracter which is a conversion value of the reference level of the CCD signal
And pixel level conversion value
And carrying out subtraction to obtain a required digital image.
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| CN201610601095.1A CN106101585B (en) | 2016-07-27 | 2016-07-27 | Low-noise CCD camera circuit |
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| CN201610601095.1A CN106101585B (en) | 2016-07-27 | 2016-07-27 | Low-noise CCD camera circuit |
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| CN106101585A CN106101585A (en) | 2016-11-09 |
| CN106101585B true CN106101585B (en) | 2022-12-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106961563B (en) * | 2017-03-24 | 2020-07-28 | 长春长光辰芯光电技术有限公司 | Low-noise wide-dynamic-range image sensor related multi-sampling circuit |
| CN112910436A (en) * | 2019-12-03 | 2021-06-04 | 华润微集成电路(无锡)有限公司 | Second-order low-pass active filter integrated circuit for realizing demodulation sampling |
| CN111918006B (en) * | 2020-07-08 | 2023-03-24 | 北京时代民芯科技有限公司 | Direct current reconstruction circuit for CCD signal processing |
| CN115150570B (en) * | 2022-09-06 | 2023-04-28 | 武汉加特林光学仪器有限公司 | Double-sampling signal processing circuit based on digital circuit and display panel detection equipment |
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| CN103259980A (en) * | 2013-05-22 | 2013-08-21 | 北京工业大学 | TDI CCD output signal preprocessor |
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- 2016-07-27 CN CN201610601095.1A patent/CN106101585B/en not_active Expired - Fee Related
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|---|---|---|---|---|
| KR950002496A (en) * | 1993-06-30 | 1995-01-04 | 사또오 후미오 | Chroma Noise Reduction Device |
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Non-Patent Citations (2)
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