CN106098847A - A kind of epitaxy method of silicon-base compound substrate - Google Patents
A kind of epitaxy method of silicon-base compound substrate Download PDFInfo
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- CN106098847A CN106098847A CN201610539789.7A CN201610539789A CN106098847A CN 106098847 A CN106098847 A CN 106098847A CN 201610539789 A CN201610539789 A CN 201610539789A CN 106098847 A CN106098847 A CN 106098847A
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- 239000000758 substrate Substances 0.000 title claims abstract description 66
- 150000001875 compounds Chemical class 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000000407 epitaxy Methods 0.000 title claims abstract description 24
- 238000000137 annealing Methods 0.000 claims abstract description 33
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical group C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000001451 molecular beam epitaxy Methods 0.000 claims abstract description 9
- 229910052714 tellurium Inorganic materials 0.000 claims abstract description 9
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000010792 warming Methods 0.000 claims description 11
- 238000001816 cooling Methods 0.000 claims description 9
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 239000002826 coolant Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 23
- 239000000463 material Substances 0.000 abstract description 19
- 239000013078 crystal Substances 0.000 abstract description 4
- 230000003746 surface roughness Effects 0.000 abstract description 4
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- MCMSPRNYOJJPIZ-UHFFFAOYSA-N cadmium;mercury;tellurium Chemical compound [Cd]=[Te]=[Hg] MCMSPRNYOJJPIZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
- H01L31/1832—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe comprising ternary compounds, e.g. Hg Cd Te
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1864—Annealing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
The invention discloses the epitaxy method of a kind of silicon-base compound substrate, specifically include following steps: extension cadmium telluride forms silicon-base compound substrate on silicon chip；In the chamber of molecular beam epitaxy system, under the protection of tellurium line, silicon-base compound substrate carrying out high/low temperature annealing, high/low temperature annealing includes temperature-rise period and temperature-fall period.By means of technical scheme, solve complex process present in prior art, scantling is required height, the uppity problem of process conditions, the quality of materials of silicon-base compound substrate can be improved, being characterized by FWHM and EPD, the silicon-base compound substrate that the method for the embodiment of the present invention obtains is compared with primary silicon-base compound substrate of the prior art, at the aspect such as surface roughness, crystal mass all to having a distinct increment.
Description
Technical field
The present invention relates to Material Field, particularly to the epitaxy method of a kind of silicon-base compound substrate.
Background technology
High-quality mercury cadmium telluride (HgCdTe) thin-film material is the base preparing high performance mercury cadmium telluride infrared focal plane detector
Plinth.Along with third generation HgCdTe infrared focus plane technology develops towards polychromes extensive, double, low cost direction, molecular beam epitaxy
Si base HgCdTe material advantage highlights.Molecular beam epitaxy Si base HgCdTe material needs first one layer of cadmium telluride of extension on Si wafer
(CdTe) material forms Si base compound substrate, then extension HgCdTe material over the substrate, but high between Si and CdTe material
Reaching the epitaxial layer crystal mass problem that the Macrolattice mismatch of 19.3% caused is preparation CdTe compound lining material on Si substrate
One of technological challenge.It is said that in general, solve this problem have increase cushion, CdTe epitaxial process adds periodically annealing
Homepitaxy process can optimize the quality of epitaxial material.It addition, after epitaxial material completes, outside chamber, the most non-online
(ex-situ) annealing process under the conditions of can also improve quality of materials.
The epitaxial layer crystal mass problem that between Si and CdTe material, the Macrolattice mismatch of up to 19.3% is caused is Si
One of technological challenge of CdTe compound lining material is prepared on substrate.Although there being increase cushion during material epitaxy, week
The processes such as phase property annealing can optimize quality of materials, but compared with cadmium-zinc-teiluride (CdZnTe) substrate, epitaxial material is still
There is bigger optimization space.Although it addition, non-online annealing process can improve quality of materials further, but it exists
Complex process, requires height, the unfavorable factors such as process conditions are wayward to scantling.
Summary of the invention
In view of the above problems, it is proposed that the present invention in case provide one overcome the problems referred to above or at least in part solve on
State the epitaxy method of a kind of silicon-base compound substrate of problem.
The epitaxy method of a kind of silicon-base compound substrate that the present invention provides, comprises the following steps:
On silicon chip, extension cadmium telluride forms silicon-base compound substrate；
In the chamber of molecular beam epitaxy system, under the protection of tellurium line, described silicon-base compound substrate is carried out height
Temperature annealing, the annealing of described high/low temperature includes temperature-rise period and temperature-fall period.
The present invention has the beneficial effect that:
The embodiment of the present invention is by after forming silicon-base compound substrate, and a kind of online high/low temperature of extra increase is annealed,
Solve complex process present in prior art, scantling is required height, the uppity problem of process conditions, it is possible to put forward
The quality of materials of high silicon-base compound substrate, is characterized by FWHM and EPD, the silica-based composite lining that the method for the embodiment of the present invention obtains
The end with of the prior art non-online under the conditions of the silicon-base compound substrate that obtains of annealing process compared with, at surface roughness, crystalline substance
The aspects such as weight are all to having a distinct increment.
Accompanying drawing explanation
Fig. 1 is the flow chart of the epitaxy method of the silicon-base compound substrate of the embodiment of the present invention；
Fig. 2 is temperature-rise period and the temperature-fall period schematic diagram of the high/low temperature annealing of the embodiment of the present invention；
Fig. 3 is temperature-rise period and the temperature-fall period schematic diagram of the high/low temperature annealing of the embodiment of the present invention；
Fig. 4 is temperature-rise period and the temperature-fall period schematic diagram alternately of the embodiment of the present invention；
Fig. 5 is the flow chart of the epitaxy method of the silicon-base compound substrate of embodiment of the present invention example 1；
Fig. 6 is the EPD SEM photograph of the silicon-base compound substrate obtained by embodiment of the present invention example 1；
Fig. 7 is the EPD SEM photograph of the silicon-base compound substrate not obtained through the annealing of online high/low temperature.
Detailed description of the invention
In order to solve the complex process that prior art exists, scantling being required height, process conditions are uppity asks
Topic, the invention provides the epitaxy method of a kind of silicon-base compound substrate, below in conjunction with accompanying drawing and embodiment, carries out the present invention
Further describe.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, does not limit this
Bright.
According to embodiments of the invention, it is provided that the epitaxy method of a kind of silicon-base compound substrate, Fig. 1 is the embodiment of the present invention
The flow chart of epitaxy method of silicon-base compound substrate, as it is shown in figure 1, outside silicon-base compound substrate according to embodiments of the present invention
Prolong method, including processing as follows:
Step 101, on silicon chip, extension cadmium telluride forms silicon-base compound substrate.
Concrete, on silicon chip, extension cadmium telluride formation silicon-base compound substrate comprises the following steps:
Silicon chip is carried out wet chemical cleans and forms oxide layer；
The silicon chip forming oxide layer is heated in molecular beam epitaxy system, is desorbed described oxide layer, forms naked silicon；
Described naked silicon carries out in temperature-fall period arsenic passivation, tellurium passivation and growth zinc telluridse cushion (use
MEE molecular migration strengthens epitaxy technology extension)；
Zinc telluridse cushion grows cadmium telluride substrate layer, forms silicon-base compound substrate.
Step 102, in the chamber of molecular beam epitaxy system, under the protection of tellurium line, to described silicon-base compound substrate
Carrying out high/low temperature annealing, the annealing of described high/low temperature includes temperature-rise period and temperature-fall period.
During actually used, tellurium protection line equivalence pressure, high/low temperature annealing temperature, time and periodicity can be according to realities
Border needs to have adjusted, however it is not limited to design parameter described above.
The form of described high/low temperature annealing is multiple, and such as temperature-rise period can be segmentation: raise uniform temperature also
Keep certain time, then continue to liter high-temperature and keep certain time, lower the temperature again after N number of temperature can being raised and keeping；Equally
Temperature-fall period can also be segmentation: reduce uniform temperature and also keep certain time, then proceed to cooling and keep a timing
Between, it is possible to decrease N number of temperature the technique carrying out next step after keeping certain time again；Certainly annealing process can also heat up cooling
Interlock and carry out.Heating up or the temperature difference of cooling can be different, the retention time (comprising 0) can also be different.
Concrete, temperature-rise period 1 specifically includes following steps:
Described silicon-base compound substrate is directly warming up to preset temperature and keeps Preset Time.
Described temperature-rise period 2 specifically includes following steps:
Step 1: described silicon-base compound substrate is warming up to the first intensification medium temperature and keeps the first intensification Preset Time；
Step 2: continue that silicon-base compound substrate is warming up to the second intensification medium temperature and keep the second intensification Preset Time；
Step 3: repeat step 2, until being warming up to preset temperature and keeping Preset Time.
Concrete, described temperature-fall period 1 specifically includes following steps:
Room temperature directly it is down to by preset temperature by keeping the silicon-base compound substrate of Preset Time at preset temperature.
Described temperature-fall period 2 specifically includes following steps:
Step 4: the silicon-base compound substrate keeping Preset Time at preset temperature is cooled to the first cooling by preset temperature
Medium temperature also keeps the first cooling Preset Time；
Step 5: continue that silicon-base compound substrate is cooled to the second cooling medium temperature and keep the second cooling Preset Time；
Step 6: repeat step 5, until being down to room temperature.
Described temperature-rise period and temperature-fall period can have different compound modes, and Fig. 2 is the high/low temperature of the embodiment of the present invention
The temperature-rise period of annealing and temperature-fall period schematic diagram (temperature-rise period 1+ temperature-fall period 2)；Fig. 3 is the high/low temperature of the embodiment of the present invention
The temperature-rise period of annealing and temperature-fall period schematic diagram (temperature-rise period 2+ temperature-fall period 1).
It addition, described temperature-rise period and temperature-fall period can also alternately, Fig. 4 is the temperature-rise period of the embodiment of the present invention
With temperature-fall period schematic diagram alternately.Concrete, described temperature-rise period and temperature-fall period alternately specifically include following
Step:
Being a cycle with a temperature-rise period and a temperature-fall period, the annealing of described high/low temperature includes multiple cycle, its
In, a cycle, particularly as follows: described silicon-base compound substrate is warming up to 350-600 DEG C, is incubated 0-30min, is then cooled to
200-400 DEG C, it is incubated 0-30min.
The epitaxy method of the silicon-base compound substrate of the embodiment of the present invention compared with non-online annealing process of the prior art,
Have the advantage that
(1) directly entire substrate can be annealed online, improve process efficiency and avoid system outer two simultaneously
Secondary pollution；
(2) line protection is the most adjustable, can reduce the roughness on surface under rational annealing conditions；
(3) annealing process temperature full wafer is uniform, and high/low temperature temperature is accurate, and repeatability is high；
(4) by on-line monitoring equipment, annealing process can be monitored, be beneficial to optimize annealing process；
(5) annealing process procedure is controlled.
For the epitaxy method of the silicon-base compound substrate of the more detailed explanation embodiment of the present invention, provide example 1.
Fig. 5 is the flow chart of the epitaxy method of the silicon-base compound substrate of embodiment of the present invention example 1, as it is shown in figure 5, carry out
After Si base compound substrate extension, carrying out online high/low temperature annealing process procedure by programme-control, annealing process is at tellurium bundle
Under the protection of stream, first it is warming up to 550 DEG C, is incubated 60sec, is then cooled to 300 DEG C, be incubated 60sec.As a week
Phase, carried out for 5 cycles.
Fig. 6 is the EPD SEM photograph of the silicon-base compound substrate obtained by embodiment of the present invention example 1, and Fig. 7 is not warp
Cross the EPD SEM photograph of the silicon-base compound substrate that annealing obtains.It addition, by white light interferometer test surfaces roughness: technique
Optimization can promote about 50%；FWHM Data Comparison, optimization degree is up to 18%.In summary, the method for the embodiment of the present invention obtains
To silicon-base compound substrate compared with primary silicon-base compound substrate, all bigger to having at the aspect such as surface roughness, crystal mass
Promote.Meanwhile, the silicon-base compound substrate obtained by embodiment of the present invention method is obtained with by the annealing of non-online high/low temperature
Silicon-base compound substrate is compared, and surface roughness decreases.
Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention
God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof
Within, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. the epitaxy method of a silicon-base compound substrate, it is characterised in that comprise the following steps:
On silicon chip, extension cadmium telluride forms silicon-base compound substrate；
In the chamber of molecular beam epitaxy system, under the protection of tellurium line, described silicon-base compound substrate is carried out high/low temperature and moves back
Fire, the annealing of described high/low temperature includes temperature-rise period and temperature-fall period.
2. epitaxy method as claimed in claim 1, it is characterised in that extension cadmium telluride forms silicon-base compound substrate on silicon chip
Comprise the following steps:
Silicon chip is carried out wet chemical cleans and forms oxide layer；
The silicon chip forming oxide layer is heated in molecular beam epitaxy system, is desorbed described oxide layer, forms naked silicon；
In temperature-fall period, described naked silicon is carried out arsenic passivation, tellurium passivation and growth zinc telluridse cushion；
Zinc telluridse cushion grows cadmium telluride substrate layer, forms silicon-base compound substrate.
3. epitaxy method as claimed in claim 1, it is characterised in that described temperature-rise period specifically includes following steps:
Described silicon-base compound substrate is directly warming up to preset temperature and keeps Preset Time.
4. epitaxy method as claimed in claim 3, it is characterised in that described temperature-rise period specifically includes following steps:
Step 1: described silicon-base compound substrate is warming up to the first intensification medium temperature and keeps the first intensification Preset Time；
Step 2: continue that silicon-base compound substrate is warming up to the second intensification medium temperature and keep the second intensification Preset Time；
Step 3: repeat step 2, until being warming up to preset temperature and keeping Preset Time.
5. the epitaxy method as described in claim 3 or 4, it is characterised in that described temperature-fall period specifically includes following steps:
Room temperature directly it is down to by preset temperature by keeping the silicon-base compound substrate of Preset Time at preset temperature.
6. the epitaxy method as described in claim 3 or 4, it is characterised in that described temperature-fall period specifically includes following steps:
Step 4: the silicon-base compound substrate keeping Preset Time at preset temperature is cooled in the middle of the first cooling by preset temperature
Temperature also keeps the first cooling Preset Time；
Step 5: continue that silicon-base compound substrate is cooled to the second cooling medium temperature and keep the second cooling Preset Time；
Step 6: repeat step 5, until being down to room temperature.
7. epitaxy method as claimed in claim 1, it is characterised in that described in the chamber of molecular beam epitaxy system, at tellurium
Under the protection of line, described silicon-base compound substrate is carried out high/low temperature annealing and specifically includes following steps:
Described temperature-rise period and temperature-fall period are alternately.
8. epitaxy method as claimed in claim 7, it is characterised in that described temperature-rise period and temperature-fall period are the most concrete
Comprise the following steps:
Being a cycle with a temperature-rise period and a temperature-fall period, the annealing of described high/low temperature includes multiple cycle, wherein, one
The individual cycle particularly as follows: described silicon-base compound substrate is warming up to 350～600 DEG C, be incubated 0～30min, be then cooled to 200～
400 DEG C, it is incubated 0～30min.
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| CN201610539789.7A CN106098847A (en) | 2016-07-11 | 2016-07-11 | A kind of epitaxy method of silicon-base compound substrate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108998830A (en) * | 2018-08-06 | 2018-12-14 | 中国电子科技集团公司第十研究所 | A kind of passivating method of mercury cadmium telluride |
| CN111755578A (en) * | 2020-07-13 | 2020-10-09 | 福建晶安光电有限公司 | Substrate and processing method thereof, and light-emitting diode and manufacturing method thereof |
| CN111755566A (en) * | 2020-06-15 | 2020-10-09 | 中国电子科技集团公司第十一研究所 | Pretreatment method of silicon-based cadmium telluride composite substrate |
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| CN103236396A (en) * | 2013-04-16 | 2013-08-07 | 中国电子科技集团公司第十一研究所 | Method for treating surfaces of epitaxial InSb substrates |
| CN104746143A (en) * | 2015-03-05 | 2015-07-01 | 中国电子科技集团公司第十一研究所 | Molecular beam epitaxy process method for silicon-based zinc telluride buffer layer |
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| CN103236396A (en) * | 2013-04-16 | 2013-08-07 | 中国电子科技集团公司第十一研究所 | Method for treating surfaces of epitaxial InSb substrates |
| CN104746143A (en) * | 2015-03-05 | 2015-07-01 | 中国电子科技集团公司第十一研究所 | Molecular beam epitaxy process method for silicon-based zinc telluride buffer layer |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108998830A (en) * | 2018-08-06 | 2018-12-14 | 中国电子科技集团公司第十研究所 | A kind of passivating method of mercury cadmium telluride |
| CN111755566A (en) * | 2020-06-15 | 2020-10-09 | 中国电子科技集团公司第十一研究所 | Pretreatment method of silicon-based cadmium telluride composite substrate |
| CN111755566B (en) * | 2020-06-15 | 2022-03-11 | 中国电子科技集团公司第十一研究所 | Pretreatment method of silicon-based cadmium telluride composite substrate |
| CN111755578A (en) * | 2020-07-13 | 2020-10-09 | 福建晶安光电有限公司 | Substrate and processing method thereof, and light-emitting diode and manufacturing method thereof |
| CN111755578B (en) * | 2020-07-13 | 2021-11-02 | 福建晶安光电有限公司 | Substrate and processing method thereof, and light-emitting diode and manufacturing method thereof |
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Application publication date: 20161109 |