CN106098792A - The full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage and preparation method - Google Patents
The full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage and preparation method Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 17
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 239000002019 doping agent Substances 0.000 claims abstract description 4
- 239000007924 injection Substances 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims abstract description 4
- 230000015556 catabolic process Effects 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000000465 moulding Methods 0.000 claims description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004899 motility Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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Abstract
The invention discloses the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage and preparation method, comprising: step A: grow one layer of lightly doped n type epitaxial layer at heavily doped P-type silicon substrate；Step B: mask outputs n-type doping regional window with photoresist, carries out n-type doping ion implanting；Step C: mask outputs p-type doped region window with photoresist, carries out p-type dopant ion injection；Step D: the silicon dioxide film of one layer of 1.5 2 μm of deposition is as the hard mask of etching ultra-deep isolated groove；Step E: carry out photoetching and silicon dioxide etching on the hard mask of step D, etches two location isolated groove windows, and this positioning groove window is as the reference position etching ultra-deep isolated groove in step F；Step F: etch ultra-deep isolated groove in extension and extend to P type substrate；Step G: with the ultra-deep isolated groove formed in silicon dioxide film filling step D；Step H: contact hole etching；Step I: metal line.
Description
Technical field
The present invention relates to the full symmetric TVS(TVS with the ultralow electric leakage of ultra-deep groove of a kind of bi-directional voltage, Transient
Voltage Suppressors) device and preparation method.Belong to technical field of semiconductors.
Background technology
Along with constantly increasing of all kinds of ESD circuit integrated level, the live width of integrated circuit reduces the most therewith.With electrostatic in circuit
The most therefore the transient voltage that electric discharge (ESD) or other forms exist is easier to damage electronic device.Two-way TVS bis-pole
Pipe, it is possible to will release from the surge pulse of data wire two ends both positive and negative polarity, thus protect system to protect against various forms of wink
The impact of state high pressure.Comparing with unidirectional protection diode, the two-way equal energy conducting of two-way TVS diode, no matter applied to two ends electricity
Pressure polarity is how, as long as voltage is more than the reverse trigger voltage of Vtrig() all can turn on, owing in this patent, special construction is two-way
TVS voltage is full symmetric, has the most reliable two-way over-voltage protecting function in actual application, protects at EDS device
Application has higher motility and reliability.Structure with ultra-deep groove makes device have ultralow electric leakage, can meet
Current TVS applies in various communication network ports and the requirement of handset port Low dark curient, and when preventing transmitting signal, the phenomenon of packet loss occurs.
Two-way TVS grows one layer of N-type epitaxy layer in P-type silicon substrate, forms the PN junction of diode, then in N-type extension
Doped p-type impurity on layer.
As it is shown in figure 1, the manufacture of existing TVS device is unidirectional TVS structure mostly.Plane TVS diode is in P-type silicon
One layer of N-type epitaxy layer of Grown, forms the PN junction of diode.As it is shown in figure 1, planar diode includes ALsicu metal level
24, SiO2 insulating barrier 23, n-type doping layer 22, P+ silicon substrate 21.The protection of the most a lot of ports all tends to bidirectional protective, now
The occasion of TVS bidirectional applications gets more and more, and a unidirectional TVS is difficult to meet the diversification of two-way different voltage gear, traditional
Unidirectional TVS cannot meet on current market high-end handsets or other portable type electronic product bidirectional applications and higher level packing forms
Requirement.
Summary of the invention
It is full symmetric with the ultralow leakage of ultra-deep groove that the technical problem that present invention mainly solves is to provide a kind of bi-directional voltage
The TVS device of electricity.
Another object of the present invention is to provide the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of described bi-directional voltage
The preparation method of part.
For solving above-mentioned technical problem, the present invention is realized by following step: a kind of bi-directional voltage is full symmetric with super
The TVS device of the ultralow electric leakage of deep trench, utilizes N+/P+ knot to form TVS structure and has reached the full symmetric of voltage, comprising: weight
Doped p-type silicon substrate, N-type epitaxial layer is lightly doped, left, center, right be respectively arranged with the left side being extended down to heavily doped P-type silicon substrate, in,
Right ultra-deep isolated groove, is separated out two identical TVS device districts of structure by left, center, right ultra-deep isolated groove by device, each
Device region has n-type doping district above epitaxial layer, and is all respectively arranged with a p-type doped region above epitaxial layer in n-type doping district, point
P+/N+ knot one, two Z1, Z2 and P+/N-Gou Cheng not tie one, two D1, D2, IO1 interface connects P+/N+ and ties a Z1 and P+/N-knot two
D2, IO2 interface connection P+/N-ties D1 and P+/N+ and ties two Z2, and when interface IO1 making alive, P+/N-ties two D2 Yu P+/N+ knots
One Z1 is forward conduction state, but low owing to N-type epitaxial layer N-extension concentration is lightly doped, and N+/P+ ties two Z2 relatively N-/P+
Tie a D1 first to turn on, now the breakdown voltage of TVS by N+/P+ tie that two Z2 are born the most pressure；Otherwise interface IO2 making alive
Time, N+/P+ ties a Z1 relatively N-/P+ and ties two D2 and first turn on, so no matter from IO1 to IO2, or, from IO2 to IO1, work
TVS is to tie one, two Z1, Z2 with N+/P+, and two-way breakdown voltage is full symmetric.
The present invention utilizes N+/P+ knot formation TVS structure to reach the full symmetric of voltage, utilizes the design of ultra-deep groove,
Realize ultralow electric leakage on electrical property (< 10nA) and high electrostatic protection ability.Make it have ultralow owing to N+ concentration is relatively low
Electric capacity, which greatly enhances the TVS device response speed to signal so that it is protection high-frequency data interface (such as HTMI2.0,
Type-C interface USB3.0) application on circuit is possibly realized.The ultralow leakage current of this structure is to the power consumption of device self and dissipates
Heat is with the obvious advantage.
TVS bi-directional voltage of the present invention is full symmetric, D2 Yu P+/N+ that P+/N-is epitaxially formed when IO1 making alive is formed
Z1 is forward conduction state, but owing to N-extension concentration is the lowest, the D1 that the Z2 that N+/P+ is formed is formed compared with N-/P+ first turns on,
Now the breakdown voltage of TVS by Z2 born the most pressure, otherwise during IO2 making alive N+/P+ formed Z1 relatively N-/P+ formed
D2 first turn on, so no matter from IO1 to IO2 or from IO2 to IO1, the TVS of work is Z1 and Z2 with N+/P+ formation,
Two-way breakdown voltage is full symmetric, and voltage can pass through N+ and P+ adjustment of technology, does not relies on epitaxial wafer specification feelings
Condition, cost is substantially reduced, and the follow-up application demand for different voltages also can quickly be developed.
On the basis of such scheme, described ultra-deep isolation trench is more than 10 μm, and depth-width ratio is between 15:1 and 25:1.
The present invention provides the preparation method of the above-mentioned full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage,
It includes following step:
Step A: grow one layer of lightly doped n type epitaxial layer at heavily doped P-type silicon substrate；
Step B: mask outputs n-type doping regional window with photoresist, carries out n-type doping ion implanting；
Step C: mask outputs p-type doped region window with photoresist, carries out p-type dopant ion injection；
Step D: the silicon dioxide film of one layer of 1.5-2 μm of deposition is as the hard mask of etching ultra-deep isolated groove；
Step E: carry out photoetching and silicon dioxide etching on the hard mask of step D, etches two location isolated groove windows,
This positioning groove window is as the reference position etching ultra-deep isolated groove in step F；
Step F: etch ultra-deep isolated groove on epitaxial layer 32 and extend to P type substrate；
Step G: with the ultra-deep isolated groove formed in silicon dioxide film filling step D；
Step H: contact hole etching；
Step I: metal line, forms D2, Z1 that interface IO1 connects, and D1, Z2 bi-directional voltage that interface IO2 connects is the most right
Claim the TVS device with the ultralow electric leakage of ultra-deep groove.
In step A, lightly doped n type epitaxial layer is 10-25 μm.
In step F, the degree of depth of ultra-deep isolated groove is 15-25 μm.
Include step in step D: the silicon dioxide film of one layer of 1.5-2 μm of deposition is hard as etching ultra-deep isolated groove
Mask, carries out photoetching and silicon dioxide etching on this hard mask, etches two location isolated groove windows, this positioning groove
Window is as the reference position etching ultra-deep isolated groove in step F.
Described silicon dioxide film using plasma strengthens process for chemical vapor deposition of materials with via molding.
The step removing hard mask is also included after step F.
The invention has the beneficial effects as follows: the present invention utilizes N+/P+ knot formation TVS structure to reach the full symmetric of voltage,
Utilize the design of ultra-deep groove, it is achieved ultralow electric leakage on electrical property (< 10nA) and high electrostatic protection ability.Due to N+ concentration
Relatively low make it have ultralow electric capacity, which greatly enhances the TVS device response speed to signal so that it is at protection high-frequency data
Application on interface (such as HTMI2.0, Type-C interface USB3.0) circuit is possibly realized.The ultralow leakage current of this structure is to device
The power consumption of part self and heat radiation are with the obvious advantage.Another one advantage of the present invention is that TVS bi-directional voltage is full symmetric, the TVS of work
Being all to tie one, two Z1, Z2 with N+/P+, two-way breakdown voltage is full symmetric, and voltage can be adjusted by N+ and P+ process conditions
Whole, do not rely on epitaxial wafer specification conditions, cost is substantially reduced.
Accompanying drawing explanation
Unidirectional TVS structural representation in Fig. 1 prior art；
Fig. 2, fundamental diagram of the present invention；
Fig. 3, present configuration schematic diagram；
Fig. 4, is the structural representation of the present embodiment step A；
Fig. 5, is the structural representation of the present embodiment step B；
Fig. 6, is the structural representation of the present embodiment step C；
Fig. 7, is the structural representation of the present embodiment step D；
Fig. 8, is the structural representation of the present embodiment step E；
Fig. 9, is the structural representation of the present embodiment step F；
Figure 10, is the structural representation of the present embodiment step G；
Figure 11, is the structural representation of the present embodiment step H；
Figure 12, is the structural representation of the present embodiment step I.
Detailed description of the invention
As shown in Figures 2 and 3, the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of a kind of bi-directional voltage, utilize
N+/P+ knot forms TVS structure and has reached the full symmetric of voltage, including: heavily doped P-type silicon substrate 31, N-type extension is lightly doped
Layer 32, be respectively arranged with in left, center, right a left, center, right ultra-deep isolated groove being extended down to heavily doped P-type silicon substrate 31 371,372,
373, left, center, right ultra-deep isolated groove 371,372,373 device is separated out two identical TVS device districts of structure, each
Device region has n-type doping district 33 above epitaxial layer 32, and is all respectively arranged with a p-type above epitaxial layer 32 in n-type doping district 33
Doped region 341,342, respectively constitutes P+/N+ knot one, two Z1, Z2 and P+/N-and ties one, two D1, D2, and IO1 interface connects P+/N+ knot
One Z1 and P+/N-ties two D2, and IO2 interface connection P+/N-ties D1 and P+/N+ and ties two Z2, when interface IO1 making alive, and P+/N-
Tying two D2 Yu P+/N+ and tying a Z1 is all forward conduction state, but low owing to N-type epitaxial layer N-extension concentration is lightly doped, N+/P
+ tie two Z2 relatively N-/P+ and tie a D1 and first turn on, now the breakdown voltage of TVS by N+/P+ tie that two Z2 are born the most pressure；Instead
Interface IO2 making alive time, N+/P+ ties a Z1 relatively N-/P+ and ties two D2 and first turn on, so no matter from IO1 to IO2, or, from
IO2 to IO1, the TVS of work are to tie one, two Z1, Z2 with N+/P+, and two-way breakdown voltage is full symmetric.
Ultra-deep isolated groove 371,372,373 degree of depth described in the present embodiment left, center, right is more than 10 μm, and depth-width ratio is at 15:1
And between 25:1.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of described bi-directional voltage, it includes following
Step:
Step A: as shown in Figure 4, grows one layer of lightly doped n type epitaxial layer 32, this lightly doped n type at heavily doped P-type silicon substrate 31
Epitaxial layer is 10-25 μm；
Step B: as it is shown in figure 5, mask outputs n-type doping regional window with photoresist, carries out n-type doping ion implanting, forms N
Type doped region 33；
Step C: as Fig. 6 mask with photoresist outputs p-type doped region window 34, carry out p-type dopant ion injection, mix in N-type
Miscellaneous district 33 p-type is formed and forms p-type doped region 342 above doped region 341 and epitaxial layer 32；
Step D: as it is shown in fig. 7, the silicon dioxide film of one layer of 1.5-2 μm of deposition is as the hard mask of etching ultra-deep isolated groove
35；
Step E: as shown in Figure 8, carries out photoetching and silicon dioxide etching on the hard mask 35 of step D, etches two location
Isolated groove window 36, this positioning groove window 36 is as the reference position etching ultra-deep isolated groove 37 in step F；
Step F: as it is shown in figure 9, this positioning groove window 36 is as the reference position of etching ultra-deep isolated groove, at isolated groove
Etch ultra-deep isolated groove 37 on epitaxial layer 32 at window 36 and extend to P type substrate 31, ultra-deep isolated groove 37 deep
Degree is 15-25 μm；
Step G: as shown in Figure 10, with the left side as shown in Figure 3 formed in silicon dioxide film filling step D, the isolation of middle right ultra-deep
Groove 371,372,373；
Step H: as shown in figure 11, etches contact hole 39；
Step I: as shown in figure 12, metal line 40, form D2, Z1 that interface IO1 connects, and D1, Z2 that interface IO2 connects are double
To the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of voltage, the product shown in pie graph 3.
Described silicon dioxide film using plasma strengthens process for chemical vapor deposition of materials with via molding.
The step removing hard mask is also included after step F.
Claims (8)
1. the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage, utilizes N+/P+ knot to form TVS knot
Structure has reached the full symmetric of voltage, it is characterised in that: including: heavily doped P-type silicon substrate, N-type epitaxial layer is lightly doped, left,
In, the right side be respectively arranged with a left, center, right ultra-deep isolated groove being extended down to heavily doped P-type silicon substrate, by left, center, right ultra-deep isolated groove
Device is separated out two identical TVS device districts of structure, and each device region has n-type doping district above epitaxial layer, mixes in N-type
In miscellaneous district and all it is respectively arranged with a p-type doped region above epitaxial layer, respectively constitutes P+/N+ knot one, two Z1, Z2 and P+/N-knot one, two
D1, D2, IO1 interface connection P+/N+ ties Z1 and P+/N-and ties two D2, and IO2 interface connects P+/N-and ties a D1 and P+/N+ knot two
Z2, when interface IO1 making alive, P+/N-ties two D2 Yu P+/N+ and ties a Z1 is all forward conduction state, but owing to being lightly doped
N-type epitaxial layer N-extension concentration is low, and N+/P+ ties two Z2 relatively N-/P+ and ties a D1 and first turn on, and now the breakdown voltage of TVS is N+/P
+ tie that two Z2 are born the most pressure；Otherwise during interface IO2 making alive, N+/P+ ties a Z1 relatively N-/P+ and ties two D2 and first turn on, this
Sample no matter from IO1 to IO2, or, from IO2 to IO1, the TVS of work is to tie one, two Z1, Z2, two-way breakdown potential with N+/P+
Press full symmetric.
Full symmetric its feature of TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 1
Being, described ultra-deep isolation trench is more than 10 μm, and depth-width ratio is between 15:1 and 25:1.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 1,
It includes following step:
Step A: grow one layer of lightly doped n type epitaxial layer at heavily doped P-type silicon substrate；
Step B: mask outputs n-type doping regional window with photoresist, carries out n-type doping ion implanting；
Step C: mask outputs p-type doped region window with photoresist, carries out p-type dopant ion injection；
Step D: the silicon dioxide film 35 of one layer of 1.5-2 μm of deposition is as the hard mask of etching ultra-deep isolated groove；
Step E: carry out photoetching and silicon dioxide etching on the hard mask of step D, etches two location isolated groove windows,
This positioning groove window is as the reference position etching ultra-deep isolated groove in step F；
Step F: etch ultra-deep isolated groove on epitaxial layer 32 and extend to P type substrate；
Step G: with the ultra-deep isolated groove formed in silicon dioxide film filling step D；
Step H: contact hole etching；
Step I: metal line, forms D2, Z1 that interface IO1 connects, and D1, Z2 bi-directional voltage that interface IO2 connects is the most right
Claim the TVS device with the ultralow electric leakage of ultra-deep groove.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 3,
It is characterized in that: in step A, lightly doped n type epitaxial layer is 10-25 μm.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 3,
It is characterized in that: in step F, the degree of depth of ultra-deep isolated groove is 15-25 μm.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 3,
It is characterized in that: include step in step D: the silicon dioxide film of one layer of 1.5-2 μm of deposition is as etching ultra-deep isolated groove
Hard mask, this hard mask carries out photoetching and silicon dioxide etching, etch two location isolated groove windows, this location
Trench openings is as the reference position etching ultra-deep isolated groove in step F.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 6,
It is characterized in that: described silicon dioxide film using plasma strengthens process for chemical vapor deposition of materials with via molding.
The preparation method of the full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage the most according to claim 6,
It is characterized in that: after step F, also include removing the step of hard mask.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301995A (en) * | 2017-07-12 | 2017-10-27 | 何春晖 | Transient Voltage Suppressor and preparation method thereof |
| CN107316864A (en) * | 2017-07-12 | 2017-11-03 | 孙丽芳 | Transient Voltage Suppressor and preparation method thereof |
| CN108321185A (en) * | 2017-12-29 | 2018-07-24 | 杭州士兰集成电路有限公司 | Bidirectional low-capacitance TVS device and its manufacturing method |
| CN108428699A (en) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | A kind of TVS device and its manufacturing method with two-way big rapid time SCR characteristic ultra-low capacitance |
| CN108565259A (en) * | 2018-04-08 | 2018-09-21 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor devices and its manufacturing method |
| CN113314616A (en) * | 2021-06-08 | 2021-08-27 | 中国振华集团永光电子有限公司（国营第八七三厂） | Bidirectional conduction EDS diode chip and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867436B1 (en) * | 2003-08-05 | 2005-03-15 | Protek Devices, Lp | Transient voltage suppression device |
| US20050190523A1 (en) * | 2004-02-27 | 2005-09-01 | Microsemi Corporation | Bi-directional pin or nip low capacitance transient voltage suppressors and steering diodes |
| CN206022373U (en) * | 2016-08-27 | 2017-03-15 | 上海长园维安微电子有限公司 | The full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage |
-
2016
- 2016-08-27 CN CN201610735415.2A patent/CN106098792A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867436B1 (en) * | 2003-08-05 | 2005-03-15 | Protek Devices, Lp | Transient voltage suppression device |
| US20050190523A1 (en) * | 2004-02-27 | 2005-09-01 | Microsemi Corporation | Bi-directional pin or nip low capacitance transient voltage suppressors and steering diodes |
| CN206022373U (en) * | 2016-08-27 | 2017-03-15 | 上海长园维安微电子有限公司 | The full symmetric TVS device with the ultralow electric leakage of ultra-deep groove of bi-directional voltage |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301995A (en) * | 2017-07-12 | 2017-10-27 | 何春晖 | Transient Voltage Suppressor and preparation method thereof |
| CN107316864A (en) * | 2017-07-12 | 2017-11-03 | 孙丽芳 | Transient Voltage Suppressor and preparation method thereof |
| CN108428699A (en) * | 2017-11-09 | 2018-08-21 | 上海长园维安微电子有限公司 | A kind of TVS device and its manufacturing method with two-way big rapid time SCR characteristic ultra-low capacitance |
| CN108428699B (en) * | 2017-11-09 | 2023-04-28 | 上海维安半导体有限公司 | TVS device with bidirectional large snapback SCR (selective catalytic reduction) characteristic and ultra-low capacitance and manufacturing method thereof |
| CN108321185A (en) * | 2017-12-29 | 2018-07-24 | 杭州士兰集成电路有限公司 | Bidirectional low-capacitance TVS device and its manufacturing method |
| CN108321185B (en) * | 2017-12-29 | 2023-10-24 | 杭州士兰集成电路有限公司 | Bidirectional low-capacitance TVS device and manufacturing method thereof |
| CN108565259A (en) * | 2018-04-08 | 2018-09-21 | 矽力杰半导体技术(杭州)有限公司 | Semiconductor devices and its manufacturing method |
| CN113314616A (en) * | 2021-06-08 | 2021-08-27 | 中国振华集团永光电子有限公司（国营第八七三厂） | Bidirectional conduction EDS diode chip and manufacturing method thereof |
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Address after: Seven road 201202 Shanghai Pudong New Area Shiwan No. 1001 Applicant after: Shanghai Wei'an Semiconductor Co.,Ltd. Address before: Seven road 201202 Shanghai Pudong New Area Shiwan No. 1001 Applicant before: SHANGHAI CHANGYUAN WAYON MICROELECTRONICS Co.,Ltd. |
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Application publication date: 20161109 |