CN106095392B - Shuffle mode generation method and device - Google Patents
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Abstract
The present invention provides a kind of shuffle mode generation method and device, wherein shuffle mode generation method includes：Obtain the input operand that shuffle mode generates instruction；Shuffle mode generates instruction for generating shuffle mode for shuffle instruction；Input operand includes：Generation pattern and base offset amount；According to generation pattern acquiring offset vector corresponding with the pattern of generation；According in the offset vector each deviant and the base offset amount, generate shuffle mode；Shuffle mode is stored in the register that shuffle mode generates indicated by the output operand of instruction.Shuffle mode generation method provided by the invention can simplify the difficulty of shuffle mode design, improve the flexibility of shuffle mode programming.
Description
Technical field
The present invention relates to field of computer data processing more particularly to a kind of shuffle mode generation method and devices.
Background technology
With the development of multimedia application, the more and more calculating tasks of processor both are from leads in Digital Image Processing
Domain, the application based on image become very important in server, desktop computer, personal mobile device and embedded device
Workload.For the actual conditions of digital imaging processing software, instruction set architecture is updated, in the processor addition pair
The instruction that operation is commonly used in is supported, is a Main way of processor development, while being also that processor is answered for specific
With the simple and efficient way of improving performance therefore single-instruction multiple-data stream (SIMD) is increased in more and more processors
(Single Instruction Multiple Data, abbreviation SIMD) structure, to support the behaviour of the same race in regular data set
Make.
Currently, generally introducing shuffle instruction in SIMD processor, shuffle instruction refers to according to specific image Processing Algorithm
It is required that data format shuffled, then, operation is carried out at the same time to the element in vector registor with an operational order, this
Just the operand set in hardware view greatly optimizes multi-media processing and matrix operation quickly generates sample.Such as：In nothing
Microprocessor (Million Instructions Per Second, abbreviation MIPS) vector instruction framework of interlocked pipeline grade
In, shuffle instruction is specially VSHF.B wd, ws, wt, wherein ws and wt is source register, and wd is both destination register, together
When be also mode control register, wd includes shuffle mode, so-called shuffle mode, refer in result data each element in source number
Location index in.In the case where register is 128, ws, wt and wd include 16 bytes, include 16 in wd
A shuffle mode byte, then after running shuffle instruction VSHF.B wd, ws, wt, newly-generated destination register wd, be according to
The pattern requirement of 16 shuffle mode bytes in wd, from selection 16 in spliced 256 of ws and wt (namely 32 bytes)
The object vector that byte is formed.
But shuffle instruction VSHF.B wd, ws, wt generally require programmer when carrying out shuffle operation to data element
The byte of the even more shuffle mode of designed in advance 1 to 16, process are cumbersome so that shuffle mode programming flexibility by
Limit.
Invention content
A kind of shuffle mode generation method of present invention offer and device are generated by shuffle mode and are instructed as shuffle instruction certainly
It is dynamic to generate shuffle mode, the difficulty of shuffle mode design is simplified, the flexibility of shuffle mode programming is improved.
Shuffle mode generation method provided by the invention, including：
Obtain the input operand that shuffle mode generates instruction；The shuffle mode generates instruction for being given birth to for shuffle instruction
At shuffle mode；The input operand includes：Generation pattern and base offset amount；
According to generation pattern acquiring offset vector corresponding with the generation pattern；
According in the offset vector each deviant and the base offset amount, generate the shuffle mode；
The shuffle mode is stored in the register that the shuffle mode generates indicated by the output operand of instruction.
Shuffle mode generating means provided by the invention, including：
First acquisition module generates the input operand of instruction for obtaining shuffle mode；The shuffle mode generation refers to
It enables for generating shuffle mode for shuffle instruction；The input operand includes：Generation pattern and base offset amount；
Second acquisition module, for according to generation pattern acquiring offset vector corresponding with the generation pattern；
Shuffle mode generation module, for according in the offset vector each deviant and the base offset amount,
Generate the shuffle mode；
Memory module, for the shuffle mode to be stored in the output operand meaning that the shuffle mode generates instruction
In the register shown.
The present invention provides a kind of shuffle mode generation method and device, wherein shuffle mode generation method includes：It obtains mixed
The input operand for washing schema creation instruction, according to pattern acquiring offset vector corresponding with the pattern of generation is generated, according to inclined
Each deviant in the amount of shifting to and base offset amount generate shuffle mode, and shuffle mode, which is stored in shuffle mode generation, to be referred to
In register indicated by the output operand of order.Shuffle mode generation method provided by the invention, by calling shuffle mode
Instruction is generated, shuffle mode corresponding with generation pattern can be got according to generation pattern and base offset amount, significantly
The design complexities of shuffle mode are simplified, while improving the flexibility of shuffle mode generation.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Some bright embodiments for those of ordinary skill in the art without having to pay creative labor, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is the flow chart for the shuffle mode generation method that the embodiment of the present invention one provides；
Fig. 2 is the flow chart of shuffle mode generation method provided by Embodiment 2 of the present invention；
Fig. 3 A are a kind of work flow diagram for the shuffle mode generation method that the embodiment of the present invention three provides；
Fig. 3 B are another work flow diagram for the shuffle mode generation method that the embodiment of the present invention three provides；
Fig. 3 C are another work flow diagram for the shuffle mode generation method that the embodiment of the present invention three provides；
Fig. 4 is the structural schematic diagram for the shuffle mode generating means that the embodiment of the present invention one provides.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Shuffle mode generation method provided in an embodiment of the present invention and device, are mainly used in during Digital Image Processing
The scene of shuffle instruction is called, such as：Estimation generic operation during Computer Vision calls the scene of shuffle instruction,
Certainly, shuffle mode generation method provided in an embodiment of the present invention and device can also be applied in addition to Digital Image Processing
Calling shuffle instruction scene.
Fig. 1 is the flow chart for the shuffle mode generation method that the embodiment of the present invention one provides, provided in this embodiment to shuffle
Pattern creating method, executive agent can be shuffle mode generating means, and shuffle mode generating means can be central processing unit
(Central Processing Unit, abbreviation CPU), or the circuit, etc. that is integrated in CPU.As shown in Figure 1, this reality
The shuffle mode generation method that example provides is applied, may include：
Step 101 obtains the input operand that shuffle mode generates instruction.
Wherein, shuffle mode generates instruction for generating shuffle mode for shuffle instruction.
Wherein, input operand includes：Generation pattern and base offset amount.
In the present embodiment, it defines shuffle mode and generates instruction, instruction is generated to be mixed by executing shuffle mode
It washes instruction and generates shuffle mode.Specifically, the input operand that shuffle mode generates instruction includes generation pattern and base offset
Amount, generates the index value that pattern is shuffle mode generating mode, and base offset amount is the basis in source register in shuffle instruction
The location index value of offset data.
Such as：Base offset amount is 5, then the location index value of the base offset data in shuffle instruction in source register is
5, shuffle mode, which will generate instruction, to generate shuffle mode according to base offset amount 5.
In the present embodiment, the input operand that shuffle mode generates instruction is obtained, can be there are many realization method, example
Such as：It can obtain, can also be given birth to by shuffle mode newly-generated in calculating process in such a way that upper layer software (applications) parameter is transmitted
Obtained at the mode of the input operand of instruction, etc..
It should be noted that the present embodiment generates shuffle mode title, the class of the instruction name and operand of instruction
Type is not particularly limited.Such as：In MIPS vector instruction frameworks, shuffle mode generates instruction and can be defined as：
VMEPATMSK.V wd,mode,u5
Wherein, VMEPATMSK.V indicates that shuffle mode generates the instruction name of instruction, and mode and u5 are input operand,
Wd is output operand.Wherein, mode indicates that generation pattern, u5 indicate that base offset amount, wd are used to indicate shuffle mode generation
The number of the destination register of instruction.Wherein, mode and u5 can be immediate, and wd can be register.
Shuffle mode is described in detail by taking concrete numerical value as an example below and generates instruction, such as：
VMEPATMSK.V 1,9,13
Then above-mentioned shuffle mode generates instruction and indicates, with the position of the base offset data in source register in shuffle instruction
Based on index value 5, the shuffle mode generating mode indicated by the index value 9 according to generating mode generates shuffle mode, wherein
Destination register number is 1.
It should be noted that the present embodiment generates the input operand in instruction for shuffle mode and exports operand
Digit is not particularly limited, and the size of digit determines input operand and exports the quantity of operand, is set as needed
It sets.
Optionally, generation pattern and base offset amount are 5 bits.At this point, the pattern of generation is 32 kinds, value can be 0
Arbitrary integer between~31, base offset amount are 32 kinds, and value can be the arbitrary integer between 0~31.
Optionally, output operand can be 5 bits.
Step 102, according to generating pattern acquiring and the corresponding offset vector of generation pattern.
Wherein, the element in offset vector is deviant, and deviant refers to relative to base in source register in shuffle instruction
The index value of the location index offset of plinth offset data.
Optionally, offset vector may include：Basic displacement amount and motion vector.Basic displacement amount refers to relative to shuffling
In instruction in source register the location index overall offset of base offset data index value, the element in motion vector is displacement
Value, shift value refers to the position relative to base offset data in source register in shuffle instruction on the basis of basic displacement amount
Set the index value of index offset.
It should be noted that the present embodiment is for the deviant in offset vector, basic displacement amount, the position in motion vector
The value of shifting value is not particularly limited, and is configured as needed.
Step 103, according to each deviant and base offset amount in offset vector, generate shuffle mode.
Specifically, shuffle mode generation method provided in this embodiment, by obtaining the life in shuffle mode generation instruction
At pattern and base offset amount, offset vector corresponding with generation pattern can be obtained, according to each inclined in offset vector
Shifting value and base offset amount, so that it may to generate shuffle mode, that is, before executing shuffle instruction, shuffle mode generation is called to refer to
It enables, does not need programmer by complicated cumbersome calculating designed in advance shuffle mode, only generated in instruction by shuffle mode
Generation pattern and base offset amount can get shuffle mode corresponding with generation pattern, be shuffled to enormously simplify
The design complexities of pattern, while the flexibility of shuffle mode generation is improved, reduce the overhead of processor.
Optionally, in a kind of concrete implementation mode, step 103, according to each deviant and base in offset vector
Plinth offset generates shuffle mode, may include：
Each deviant in offset vector is added with base offset amount successively, generates shuffle mode.
The step of generating shuffle mode is described in detail by taking concrete numerical value as an example below.
It is assumed that base offset amount is 10, each deviant in offset vector is respectively：0、1、2、3、0、1、2、3、0、1、
2、3、0、1、2、3。
The shuffle mode then generated is：10+0、10+1、10+2、10+3、10+0、10+1、10+2、10+3、10+0、10+1、
10+2,10+3,10+0,10+1,10+2,10+3, i.e., 10,11,12,13,10,11,12,13,10,11,12,13,10,11,12,
13。
Optionally, if offset vector includes basic displacement amount and motion vector, according to each offset in offset vector
Value and base offset amount generate shuffle mode, may include：
Each shift value in motion vector is added with basic displacement amount and base offset amount successively, mould is shuffled in generation
Formula.
The step of generating shuffle mode is described in detail by taking concrete numerical value as an example below.
It is assumed that base offset amount is 6, basic displacement amount is 8, and each shift value in motion vector is respectively：0、1、2、
3、1、2、3、4、0、1、2、3、1、2、3、4。
The shuffle mode then generated is：6+8+0、6+8+1、6+8+2、6+8+3、6+8+1、6+8+2、6+8+3、6+8+4、6+
8+0,6+8+1,6+8+2,6+8+3,6+8+1,6+8+2,6+8+3,6+8+4, i.e., 14,15,16,17,15,16,17,18,14,
15、16、17、15、16、17、18。
Shuffle mode is stored in the register that shuffle mode generates indicated by the output operand of instruction by step 104.
Specifically, shuffle mode generates the output operand of instruction, it is used to indicate the purpose that shuffle mode generates instruction and posts
Shuffle mode is stored in the register indicated by output operand by the number of storage.
Optionally, shuffle mode generation method provided in this embodiment can also include：
Shuffle instruction is executed according to shuffle mode.
A kind of shuffle mode generation method is present embodiments provided, including：Obtain the input behaviour that shuffle mode generates instruction
Count, according to generating pattern acquiring and the corresponding offset vector of the pattern of generation, according in offset vector each deviant with
Base offset amount generates shuffle mode, and shuffle mode, which is stored in shuffle mode, to be generated indicated by the output operand of instruction
In register.Shuffle mode generation method provided in this embodiment, by calling shuffle mode to generate instruction, according to the pattern of generation
Shuffle mode corresponding with generation pattern can be got with base offset amount, the design for enormously simplifying shuffle mode is multiple
Miscellaneous degree, while the flexibility of shuffle mode generation is improved, reduce the overhead of processor.
Fig. 2 is the flow chart of shuffle mode generation method provided by Embodiment 2 of the present invention, and the present embodiment is in embodiment one
On the basis of, provide another realization method of shuffle mode generation method.As shown in Fig. 2, provided in this embodiment shuffle
Pattern creating method in embodiment one before step 101, can also include：
Step 201, the data shuffling obtained in application software are regular.
Specifically, for specific application software, in data processing, carrying out shuffle operation to data would generally abide by
Certain rule is followed, which is known as data shuffling rule.
Wherein, the present embodiment is not particularly limited the concrete type of application software, such as：Application software can be video
Processing software or image processing software, etc..
Wherein, the data shuffling rule in application software is obtained, can be the data for obtaining specific operation in application software
Rule is shuffled, such as：Obtain the data shuffling rule of estimation generic operation in Video processing software, wherein estimation is
Widely used technology in Video coding and video processing, for removing interframe redundancy so that the bit number of transmission of video is big
It is big to reduce.
This step is described in detail with specific example below.
Such as：For the estimation generic operation in video processing, usually image is divided into according to the size of 4*4 pixels
Multiple images sub-block carries out data shuffling operation, in data processing, for each figure to the pixel in image subblock
As the data shuffling of sub-block, 4 pixels of the 1st row of image subblock are usually only taken, then, for the movement in video processing
Estimate generic operation, data shuffling rule is 4 pixels of the 1st row for obtaining each image subblock.
Step 202 generates offset vector and generation pattern corresponding with offset vector according to data shuffling rule.
Specifically, the data shuffling operation due to application software has data shuffling rule, then it can be mixed according to the data
It washes rule and generates offset vector, and corresponding generation pattern is generated for the offset vector, in this way, referring in shuffle mode generation
In order, specific generation pattern is obtained, then corresponds to an offset vector that can reflect data shuffling rule, and then according to mixed
The generation pattern and base offset amount washed in schema creation instruction generate shuffle mode, to enormously simplify setting for shuffle mode
Complexity is counted, the flexibility of shuffle mode generation is improved.
This step is described in detail with specific example below.
Such as：For the estimation generic operation in video processing, data shuffling rule is to obtain each image subblock
4 pixels of the 1st row, then according to the data shuffling rule can generate offset vector be 0,1,2,3,1,2,3,4,0,1,2,
3,1,2,3,4, generation pattern definition corresponding with the offset vector is 1.
A kind of shuffle mode generation method is present embodiments provided, by obtaining the data shuffling rule in application software,
Offset vector and generation pattern corresponding with offset vector are generated according to data shuffling rule, by calling shuffle mode life
Shuffle mode can be generated at instruction.Shuffle mode generation method provided in this embodiment, enormously simplifies setting for shuffle mode
Complexity is counted, while improving the flexibility of shuffle mode generation.
It, will be with specific example specifically on the basis of embodiment one and embodiment two as the embodiment of the present invention three
Bright shuffle mode generation method provided in this embodiment.
Fig. 3 A are a kind of work flow diagram for the shuffle mode generation method that the embodiment of the present invention three provides, and Fig. 3 A are shown
It calls shuffle mode to generate instruction and shuffle instruction, generates a kind of workflow for shuffling result.
As shown in Figure 3A, it can be VMEPATMSK.V wt1 that shuffle mode, which generates instruction, 1,0, shuffle instruction can be
VSHF.B wt1,wr1,wr1。
Wherein, generate pattern be 1, base offset amount be 0, generate 1 corresponding offset vector of pattern be 0,1,2,3,1,2,
3,4,2,3,4,5,3,4,5,6, then it is 0+0,0+1,0+2,0+3,0+ to call shuffle mode to generate the shuffle mode that instruction generates
1,0+2,0+3,0+4,0+2,0+3,0+4,0+5,0+3,0+4,0+5,0+6, i.e., 0,1,2,3,1,2,3,4,2,3,4,5,3,4,
5,6, referring to table 1.
Wherein, S1-01 and S1-03 be shuffle instruction in two source operands, S1-02 indicate by two source operands into
Row head and the tail connect, and S1-04 is the register for the output operand instruction that shuffle mode generates instruction and the pattern of shuffle instruction
Vector registor, S1-05 are the object vector register of generation after being shuffled according to pattern vector register.
Table 1
Fig. 3 B are another work flow diagram for the shuffle mode generation method that the embodiment of the present invention three provides, and Fig. 3 B are shown
Calling shuffle mode generates instruction and shuffle instruction, generates another workflow for shuffling result.
As shown in Figure 3B, it can be VMEPATMSK.V wt2 that shuffle mode, which generates instruction, 2,0, shuffle instruction can be
VSHF.B wt2,wr1,wr1。
Wherein, it is 2 to generate pattern, and base offset amount is 0, and it is 4 to generate 2 corresponding basic displacement amount of pattern, generates pattern 2
Corresponding motion vector is 0,1,2,3,1,2,3,4,2,3,4,5,3,4,5,6, then shuffle mode is called to generate what instruction generated
Shuffle mode is 0+4+0,0+4+1,0+4+2,0+4+3,0+4+1,0+4+2,0+4+3,0+4+4,0+4+2,0+4+3,0+4+4,0
+ 4+5,0+4+3,0+4+4,0+4+5,0+4+6, i.e., 4,5,6,7,5,6,7,8,6,7,8,9,7,8,9,10, referring to table 2.
Wherein, S2-01 and S2-03 be shuffle instruction in two source operands, S2-02 indicate by two source operands into
Row head and the tail connect, and S2-04 is the register for the output operand instruction that shuffle mode generates instruction and the pattern of shuffle instruction
Vector registor, S2-05~S2-08 are 4 words for shuffling process generation, and S2-09 is to be mixed according to pattern vector register
After washing, the object vector register of generation.
Table 2
Fig. 3 C are another work flow diagram for the shuffle mode generation method that the embodiment of the present invention three provides, and Fig. 3 C are shown
Calling shuffle mode generates instruction and shuffle instruction, generates another workflow for shuffling result.
As shown in Figure 3 C, it can be VMEPATMSK.V wt3 that shuffle mode, which generates instruction, 0,8, shuffle instruction can be
VSHF.B wt3,wr1,wr1。
Wherein, generate pattern be 0, base offset amount be 8, generate 1 corresponding offset vector of pattern be 0,1,2,3,0,1,
2,3,0,1,2,3,0,1,2,3, then it is 8+0,8+1,8+2,8+3,8+ to call shuffle mode to generate the shuffle mode that instruction generates
0,8+1,8+2,8+3,8+0,8+1,8+2,8+3,8+0,8+1,8+2,8+3, i.e., 8,9,10,11,8,9,10,11,8,9,10,
11,8,9,10,11, referring to table 3.
Wherein, S3-01 and S3-03 be shuffle instruction in two source operands, S3-02 indicate by two source operands into
Row head and the tail connect, and S3-04 is the register for the output operand instruction that shuffle mode generates instruction and the pattern of shuffle instruction
Vector registor, S3-05 are the object vector register of generation after being shuffled according to pattern vector register.
Table 3
Fig. 4 is the structural schematic diagram for the shuffle mode generating means that the embodiment of the present invention one provides, provided in this embodiment
Shuffle mode generating means, the shuffle mode generation method provided for executing any embodiment shown in Fig. 1~Fig. 3 C.Such as figure
Shown in 4, shuffle mode generating means provided in this embodiment may include：
First acquisition module 11 generates the input operand of instruction for obtaining shuffle mode.Shuffle mode generates instruction
For generating shuffle mode for shuffle instruction.Input operand includes：Generation pattern and base offset amount.
Second acquisition module 12, for according to generation pattern acquiring offset vector corresponding with the pattern of generation.
Shuffle mode generation module 13, according to each deviant and base offset amount in offset vector, mould is shuffled in generation
Formula.
Memory module 14 generates posting indicated by the output operand of instruction for shuffle mode to be stored in shuffle mode
In storage.
Optionally, shuffle mode generation module 13 is specifically used for：
Each deviant in offset vector is added with base offset amount successively, generates shuffle mode.
Optionally, shuffle mode generating means further include：Third acquisition module.
Third acquisition module is used for：
Obtain the data shuffling rule in application software.
Offset vector and generation pattern corresponding with offset vector are generated according to data shuffling rule.
Optionally, offset vector includes：Basic displacement amount and motion vector.
Shuffle mode generation module 13 is specifically used for：
Each shift value in motion vector is added with basic displacement amount and base offset amount successively, mould is shuffled in generation
Formula.
Optionally, generation pattern and base offset amount are 5 bits.
Optionally, shuffle mode generating means further include：Shuffle module.
Shuffle module is used to execute shuffle instruction according to shuffle mode.
Shuffle mode generating means provided in this embodiment are provided for executing either method embodiment shown in Fig. 1-Fig. 3 C
Shuffle mode generation method, technical principle is similar with technique effect, and details are not described herein again.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (8)
1. a kind of shuffle mode generation method, which is characterized in that including：
Obtain the input operand that shuffle mode generates instruction；It is mixed for being generated for shuffle instruction that the shuffle mode generates instruction
Mold cleaning formula；The input operand includes：Generation pattern and base offset amount；
According to generation pattern acquiring offset vector corresponding with the generation pattern；
According in the offset vector each deviant and the base offset amount, generate the shuffle mode；
The shuffle mode is stored in the register that the shuffle mode generates indicated by the output operand of instruction；
Before the acquisition shuffle mode generates the input operand of instruction, further include：
Obtain the data shuffling rule in application software；
The offset vector and generation pattern corresponding with the offset vector are generated according to the data shuffling rule.
2. according to the method described in claim 1, it is characterized in that, the offset vector includes：Basic displacement amount and displacement to
Amount；
Each deviant according in the offset vector and the base offset amount, generate the shuffle mode, including：
Each shift value in the motion vector is added with the basic displacement amount and the base offset amount successively, it is raw
At the shuffle mode.
3. method according to claim 1 or 2, which is characterized in that the generation pattern and the base offset amount are 5
Bit.
4. method according to claim 1 or 2, which is characterized in that further include：
The shuffle instruction is executed according to the shuffle mode.
5. a kind of shuffle mode generating means, which is characterized in that including：
First acquisition module generates the input operand of instruction for obtaining shuffle mode；The shuffle mode generates instruction and uses
In for shuffle instruction generate shuffle mode；The input operand includes：Generation pattern and base offset amount；
Second acquisition module, for according to generation pattern acquiring offset vector corresponding with the generation pattern；
Shuffle mode generation module, for according in the offset vector each deviant and the base offset amount, generate
The shuffle mode；
Memory module is generated for the shuffle mode to be stored in the shuffle mode indicated by the output operand of instruction
In register；
Described device further includes：Third acquisition module；
The third acquisition module is used for：
Obtain the data shuffling rule in application software；
The offset vector and generation pattern corresponding with the offset vector are generated according to the data shuffling rule.
6. device according to claim 5, which is characterized in that the offset vector includes：Basic displacement amount and displacement to
Amount；
The shuffle mode generation module is specifically used for：
Each shift value in the motion vector is added with the basic displacement amount and the base offset amount successively, it is raw
At the shuffle mode.
7. device according to claim 5 or 6, which is characterized in that the generation pattern and the base offset amount are 5
Bit.
8. device according to claim 5 or 6, which is characterized in that further include：Shuffle module；
The shuffle module, for executing the shuffle instruction according to the shuffle mode.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104011643A (en) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | Packed data rearrangement control indexes generation processors, methods, systems, and instructions |
| CN104011645A (en) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset |
| CN104126168A (en) * | 2011-12-22 | 2014-10-29 | 英特尔公司 | Packed data rearrangement control indexes precursors generation processors, methods, systems and instructions |
| CN105022609A (en) * | 2015-08-05 | 2015-11-04 | 浪潮(北京)电子信息产业有限公司 | Data shuffling method and data shuffling unit |
-
2016
- 2016-06-20 CN CN201610443245.0A patent/CN106095392B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104011643A (en) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | Packed data rearrangement control indexes generation processors, methods, systems, and instructions |
| CN104011645A (en) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset |
| CN104126168A (en) * | 2011-12-22 | 2014-10-29 | 英特尔公司 | Packed data rearrangement control indexes precursors generation processors, methods, systems and instructions |
| CN105022609A (en) * | 2015-08-05 | 2015-11-04 | 浪潮(北京)电子信息产业有限公司 | Data shuffling method and data shuffling unit |
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