CN106095338A - The erasable implementation method of a kind of memory chip and realize system - Google Patents
The erasable implementation method of a kind of memory chip and realize system Download PDFInfo
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- CN106095338A CN106095338A CN201610410343.4A CN201610410343A CN106095338A CN 106095338 A CN106095338 A CN 106095338A CN 201610410343 A CN201610410343 A CN 201610410343A CN 106095338 A CN106095338 A CN 106095338A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses the erasable implementation method of a kind of memory chip and realize system, method includes: when data memory to be stored inputs memory chip, then judge to divide in the many sub spaces obtained the most all have write data according to data memory size to be stored in memory chip；Wherein, the memory headroom of each subspace is all higher than or equal to data memory size to be stored；When there being subspace not write data, then by data memory write to be stored, and it is marked.Present invention achieves all of memory space in average use memory chip, erasable number of times is shared, in order to avoid individually a certain memory space number of operations to memory chip too much causes chip data read-write abnormal.
Description
Technical field
The present invention relates to memory chip technical field of memory, the erasable implementation method of a kind of memory chip
And realize system.
Background technology
At present, the outer machine of air-conditioning equipment has memory, and in part, machine also has memory function, some memory in the data of memory
Number of times can related frequency.The master chip of mainboard is all that the fixing lowest address page from memory chip starts to write data.If should
Secondary write data only occupy memory headroom less in memory chip, when needing next time memory chip write data, then again
Write data into again after needing first to be wiped by the low address page of memory chip.Be equivalent to all erase memory core during the write of every secondary data
The low address page of sheet, which results in the frequency that the memory space of low address page is wiped free of higher, and other ground in memory chip
The frequency that the memory space of location page is written into data and erasing is relatively low.Owing to memory chip itself writes the number of times upper limit, therefore
The most erasable rear memory chip has arisen that storage data record not or has made mistakes, and even breaks down.
Therefore, prior art has yet to be improved and developed.
Summary of the invention
In view of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide the erasable implementation method of a kind of memory chip
And realize system, it is intended to solving the master chip of mainboard in prior art is all that the fixing lowest address page from memory chip starts to write
Enter data, all erase the low address page of memory chip during the write of every secondary data, which results in the memory space of low address page
The frequency being wiped free of is higher, thus causes memory chip storage corrupt data or the defect broken down.
Technical scheme is as follows:
A kind of erasable implementation method of memory chip, wherein, including step:
When data memory to be stored inputs memory chip, then judge in memory chip according to data memory size to be stored
Divide in the many sub spaces obtained and the most all have write data；Wherein, the memory headroom of each subspace is all higher than or is equal to
Data memory size to be stored；
When there being subspace not write data, then by data memory write to be stored, and it is marked.
The erasable implementation method of described memory chip, wherein, when described data memory to be stored inputs memory chip, then
Judge memory chip divides in the many sub spaces obtained the most all have write number according to data memory size to be stored
According to step specifically include:
When data memory to be stored inputs memory chip, read the maximum operating sequence number in subspace, and judge to operate sequence
Number the maximum block number whether aliquot memory headroom is bisected into；Described operation sequence number be written in subspace to be stored
Data memory time arrange；
When aliquot, then without the writable data in subspace；
When aliquant, then there are the writable data in subspace.
The erasable implementation method of described memory chip, wherein, described when there being subspace not write data, then will wait to deposit
The data memory of storage writes, and the step being marked specifically includes:
If during the block number that the aliquant memory headroom of maximum of operation sequence number is bisected into, then positioning and operation sequence number not being set
Subspace in one of；
By data memory write to be stored, and the maximum that the operation sequence number of this subspace is set to operate sequence number adds 1, and returns
Receipt row judges to operate the maximum block number whether aliquot memory headroom is bisected into of sequence number.
The erasable implementation method of described memory chip, wherein, also includes:
If during the block number that the maximum aliquot memory headroom of operation sequence number is bisected into, then positioning action serial number is specified initial
The subspace of sequence number, after wiping the operation sequence number of data and all subspaces in this subspace, writes data memory to be stored
Enter this subspace, and be still set to the operation sequence number of this subspace specify initial sequence number.
The erasable implementation method of described memory chip, wherein, also includes:
If during the block number that the maximum aliquot memory headroom of operation sequence number is bisected into, then by subspace each in memory chip
Data and operation sequence number all wipe, location be not set operation sequence number subspace in one of, in this subspace
Write data memory to be stored, and be set to the operation sequence number of this subspace specify initial sequence number.
The erasable implementation method of described memory chip, wherein, when described data memory to be stored inputs memory chip, then
Judge memory chip divides in the many sub spaces obtained the most all have write number according to data memory size to be stored
According to step before also include:
Obtain data memory size to be stored；
The memory headroom of memory chip is divided into polylith subspace；Wherein, the total block data of subspace is less than or equal to memory core
The storage total capacity of sheet is divided by data memory size to be stored, and the memory headroom of each subspace is all higher than or equal to be stored
Data memory size, each subspace is provided with storage operation sequence number region.
The erasable of a kind of memory chip realizes system, wherein, and including:
Judge module, when data memory input memory chip to be stored, then judges in memory chip according to be stored
Data memory size and divide in the many sub spaces obtained and the most all have write data；Wherein, the internal memory of each subspace is empty
Between be all higher than or equal to data memory size to be stored；
Write and mark module, for when there being subspace not write data, then by data memory write to be stored, go forward side by side
Line flag.
The erasable of described memory chip realizes system, and wherein, described judge module specifically includes:
Sequence number acquiring unit, when data memory input memory chip to be stored, reads and operates sequence number in subspace
Big value, and judge to operate the maximum block number whether aliquot memory headroom is bisected into of sequence number；Described operation sequence number be
Subspace is arranged when being written into data memory to be stored；
Divide exactly control unit, for when aliquot, then without the writable data in subspace；
Non-divide exactly control unit, for when aliquant, then have the writable data in subspace.
The erasable of described memory chip realizes system, and wherein, said write and mark module include:
Positioning unit, if for operation sequence number the aliquant memory headroom of maximum be bisected into block number time, then position not
Be set in the subspace of operation sequence number is one of；
Write control unit, for being write by data memory to be stored, and is set to the operation sequence number of this subspace operate sequence
Number maximum add 1, and start sequence number acquiring unit.
The erasable of described memory chip realizes system, wherein, also includes:
Write full control module, if for operation sequence number maximum aliquot memory headroom be bisected into block number time, then position
Operation serial number specifies the subspace of initial sequence number, after wiping the operation sequence number of data and all subspaces in this subspace, and will
Data memory to be stored writes this subspace, and is still set to the operation sequence number of this subspace specify initial sequence number.
Beneficial effect: the present invention, will note by data memory size to be stored when writing data in memory chip
Recalling the memory space of chip to divide equally and obtain polylith subspace, write data use one piece every time, are automatically shifted to next block next time and enter
Row is erasable, and the subspace jumping back to during to last block specify initial sequence number corresponding is the most erasable, or all subspace is all wiped,
Circulate successively, averagely utilize all subspaces of memory chip, thus increase the service life of memory chip.
Accompanying drawing explanation
Fig. 1 is the flow chart of the erasable implementation method preferred embodiment of memory chip of the present invention；
Fig. 2 is the particular flow sheet of step before step S100 in method shown in Fig. 1 of the present invention；
Fig. 3 is the erasable structured flowchart realizing system the first preferred embodiment of memory chip of the present invention；
Fig. 4 is the erasable structured flowchart realizing system the second preferred embodiment of memory chip of the present invention.
Detailed description of the invention
The present invention provides the erasable implementation method of a kind of memory chip and realizes system, for making the purpose of the present invention, technology
Scheme and effect are clearer, clear and definite, and the present invention is described in more detail below.Should be appreciated that described herein specifically
Embodiment only in order to explain the present invention, is not intended to limit the present invention.
Refer to the flow chart of the erasable implementation method preferred embodiment that Fig. 1, Fig. 1 are memory chip of the present invention.As
Shown in Fig. 1, it comprises the following steps:
During S101, data memory to be stored input memory chip, then judge in memory chip according to data memory to be stored
Size and divide in the many sub spaces obtained and the most all have write data；Wherein, the memory headroom of each subspace is all higher than
Or equal to data memory size to be stored；
S102, when there being subspace not write data, then by data memory write to be stored, and be marked.
In embodiments of the invention, when subspace is written into data, then can be added labelling, take turns note to represent at this
Recalling in the use of chip, this subspace has been used.More specifically, it is assumed that memory chip is divided into N number of subspace, from initially
Blank memory chip begins to use as initial point, when N number of subspace is all written into and is only written one time, represents that this takes turns note
The use recalling chip is complete.And every sub spaces is when being written into data, all can add a labelling (such as sequence number 1,2,3 ...,
N, in this use taken turns, this subspace is i-th when being written into data, then give numbering i, when the numbering of certain sub spaces
During i=N, then it represents that it is complete that this of memory chip takes turns use).
As the preferred embodiments of the present invention, in the erasable implementation method of described memory chip, described step S101 has
Body includes:
During S201, data memory to be stored input memory chip, read the maximum operating sequence number in subspace, and judge behaviour
Make the maximum block number whether aliquot memory headroom is bisected into of sequence number；Described operation sequence number is to be written in subspace to treat
Arrange during the data memory stored；
S202, when aliquot, then without the writable data in subspace；
S203, when aliquant, then have the writable data in subspace.
As the preferred embodiments of the present invention, in the erasable implementation method of described memory chip, described step S102 has
Body includes:
If during the block number that the aliquant memory headroom of maximum of S301 operation sequence number is bisected into, then positioning and behaviour not being set
That makees in the subspace of sequence number is one of；
S302, by data memory write to be stored, and the maximum that the operation sequence number of this subspace is set to operation sequence number adds
1, and return execution S201.
Prior art is directly the fixing lowest address page from memory chip starts to write data, low by memory chip
Write data into again after address page erasing, result in the frequency that the memory space of low address page is wiped free of higher, and memory chip
In the memory space of other address pages to be written into the frequency of data and erasing relatively low.
And in embodiments of the invention, for same memory chip, its storage total capacity C(C is positive integer) it is fixing
, and the data memory size that data memory size Dm(to be stored is to be stored, it is simply that the data of data memory to be stored are big
Little, Dm is positive integer) also can obtain in real time.By in data memory input to be stored to the memory headroom of memory chip
Time, owing to the memory space division of memory chip being obtained polylith subspace according to data memory size to be stored.Example
As, if the result of the block number n(C/Dm being bisected into according to the memory headroom of n=C/Dm acquisition memory chip is integer, then n takes
Integer；If the result of C/Dm is not integer, then result is rounded up).Now, operation sequence in many sub spaces only need to first be read
Number maximum, and judge operate sequence number the maximum block number n whether aliquot memory headroom is bisected into.
In step S301, when there being subspace not write data, i.e. the operation sequence number of memory chip sub-spaces
The block number that maximum can not be divided by memory headroom is divided exactly, then it represents that this take turns erasable in, also subspace not by
Data are re-write again after taking turns to data erasing.Now, need to position be not set operation sequence number subspace in one of,
Wipe in this subspace and after data, data memory to be stored is write, and be set to the operation sequence number of this subspace operate sequence number
Maximum add 1.
In order to clearer understand subspace is operated the setting up procedure of sequence number by embodiments of the invention, below by
One specific embodiment illustrates.
Assume that memory chip A is bisected into 5 sub spaces, be designated as 1-subspace, subspace 5 respectively, at N wheel (due to note
Recall chip A and be bisected into 5 sub spaces, therefore each wheel of memory chip A can use 5 times) erasable in, if it is empty first to erase son
Between initial data in 1 when writing data memory to be stored, then subspace 1 is arranged simultaneously operation sequence number 1.Now operate
The maximum of sequence number is 1,1 can not to be divided exactly by 5, thus location be not set in the subspace of operation sequence number one of, example
Such as subspace 2, by data memory write to be stored after data in erasing subspace 2, and the operation sequence number of subspace 2 is set to
2(now, is equivalent to appointment numerical value is taken 1), by that analogy, until there being the operation sequence number of subspace to be set to 5, then it represents that this is taken turns
Erasable complete.For the ease of labelling, the data only come when Central Plains, subspace are wiped free of and re-write memory to be stored
During data, this subspace just can be set an operation sequence number.
As first preferred embodiment of the present invention, the erasable implementation method of described memory chip, also include:
If during the block number that the maximum aliquot memory headroom of S1031 operation sequence number is bisected into, then positioning action serial number refers to
Determine the subspace of initial sequence number, after wiping the operation sequence number of data and all subspaces in this subspace, by memory to be stored
Data write this subspace, and are still set to the operation sequence number of this subspace specify initial sequence number.
Obviously, when not writing data without subspace, namely when the maximum of operation sequence number can be by memory headroom institute quilt
Divide block number divide exactly, then it represents that this take turns erasable in, all subspaces the most taken turns to data erasing after re-write again
Data.Now, positioning action serial number specifies the subspace of initial sequence number, wipes data and all subspaces in this subspace
Operation sequence number after, data memory to be stored is write this subspace, and is still set to the operation sequence number of this subspace specify
Initial sequence number.So, when subspace each in the memory headroom of memory chip complete one take turns use time, then be repositioned onto operation sequence
Number for specify initial sequence number subspace, restart the use of a new round.
Such as, 5 sub spaces in memory chip A re-write number after the most having been taken turns to data erasing in same wheel again
According to, now can navigate to operate the subspace 1 of serial number 1.Data in subspace 1 are wiped, simultaneously also by subspace 1-
The operation sequence number the stored erasing of each subspace in space 5.After completing erasing, data memory the most to be stored is write
Enter this subspace, and be still set to the operation sequence number of this subspace specify initial sequence number (such as 1).When being embodied as, described finger
Determine the block number remainder that memory headroom is bisected into by initial sequence number and be not equal to 0, specify the initial sequence number can not the most in the above example
Take 5.
As second preferred embodiment of the present invention, the erasable implementation method of described memory chip, also include: also include:
If during the block number that the maximum aliquot memory headroom of S1032 operation sequence number is bisected into, then by each in memory chip
Data and the operation sequence number of subspace are all wiped, and it is one of, at this son that location is not set in the subspace of operation sequence number
Space writes data memory to be stored, and is set to the operation sequence number of this subspace specify initial sequence number.
Different from the first preferred embodiment are, in the second preferred embodiment, when not writing data without subspace
Time, namely when the block number that the maximum operating sequence number can be divided by memory headroom is divided exactly, disposably by memory chip
All subspaces data and operation sequence number all wipe.Random position one sub spaces the most again, writes in this subspace
Enter data memory to be stored, and be set to the operation sequence number of this subspace specify initial sequence number.With the first preferred embodiment phase
Ratio, the second preferred embodiment only changes when the block number that the maximum operating sequence number can be divided by memory headroom is divided exactly
Erasing mechanism, be no longer subdividing erasing, but the memory headroom of whole memory chip is all wiped.
Owing to the size needing the data memory to be stored re-write in memory chip is big with the data write last time
It is little that to compare change less, therefore without the most again the memory space of memory chip being carried out piecemeal.Therefore in execution of step
After S1031 or step S1032, then return and perform step S101.
It is also preferred that the left as in figure 2 it is shown, also include before described step S101:
Step S11, obtain data memory size to be stored；
Step S12, the memory headroom of memory chip is divided into polylith subspace；Wherein, the total block data of subspace less than or etc.
In the storage total capacity of memory chip divided by data memory size to be stored, the memory headroom of each subspace be all higher than or etc.
In data memory size to be stored, each subspace is provided with the region of storage operation sequence number.
Visible, in the present invention, all of memory space in average use memory chip, shares erasable number of times, in order to avoid individually
Too much cause chip data read-write abnormal a certain memory space number of operations of memory chip.
Based on said method, the present invention also provides for the erasable of a kind of memory chip and realizes system, as shown in Figure 3 and Figure 4, and its
Including:
Judge module 100, when data memory input memory chip to be stored, then judges in memory chip according to be stored
Data memory size and divide in the many sub spaces obtained and the most all have write data；Wherein, the internal memory of each subspace
Space is all higher than or equal to data memory size to be stored；
Write and mark module 200, for when there being subspace not write data, then by data memory write to be stored,
And be marked.
Further, as the erasable System Preferred embodiments that realizes of memory chip of the present invention, described judge module
100 specifically include:
Sequence number acquiring unit, when data memory input memory chip to be stored, reads and operates sequence number in subspace
Big value, and judge to operate the maximum block number whether aliquot memory headroom is bisected into of sequence number；Described operation sequence number be
Subspace is arranged when being written into data memory to be stored；
Divide exactly control unit, for when aliquot, then without the writable data in subspace；
Non-divide exactly control unit, for when aliquant, then have the writable data in subspace.
Further, as the erasable System Preferred embodiments that realizes of memory chip of the present invention, said write and mark
Note module 200 specifically includes:
Positioning unit, if for operation sequence number the aliquant memory headroom of maximum be bisected into block number time, then position not
Be set in the subspace of operation sequence number is one of；
Write control unit, for being write by data memory to be stored, and is set to the operation sequence number of this subspace operate sequence
Number maximum add 1, and start sequence number acquiring unit.
Further, refer to Fig. 3, the erasable system first that realizes as memory chip of the present invention is preferably implemented
Example, the erasable of described memory chip realizes system, also includes:
Write full control module 310, if the block number that the maximum aliquot memory headroom being used for current operation sequence number is bisected into, then
Positioning action serial number specifies the subspace of initial sequence number, wipes the operation sequence number of data and all subspaces in this subspace
After, data memory to be stored is write this subspace, and is still set to the operation sequence number of this subspace specify initial sequence number.
Further, refer to Fig. 4, the erasable system second that realizes as memory chip of the present invention is preferably implemented
Example, the erasable of described memory chip realizes system, also includes:
Full erasing control module 320, if the block number that the maximum aliquot memory headroom being used for current operation sequence number is bisected into,
Then data and the operation sequence number of subspace each in memory chip all being wiped, location is not set the subspace of operation sequence number
In one of, this subspace writes data memory to be stored, and is set to the operation sequence number of this subspace specify
Initial sequence number.
Further, the erasable realization at described memory chip, in system, also includes:
Size of data acquiring unit, for obtaining data memory size to be stored；
Division unit, for being divided into polylith subspace by the memory headroom of memory chip；Wherein, the total block data of subspace is less than
Or be all higher than divided by data memory size to be stored, the memory headroom of each subspace equal to the storage total capacity of memory chip
Or equal to data memory size to be stored, each subspace is provided with the region of storage operation sequence number.
In sum, the present invention, will note by data memory size to be stored when writing data in memory chip
Recalling the memory space of chip to divide equally and obtain polylith subspace, write data use one piece every time, are automatically shifted to next block next time and enter
Row is erasable, and the subspace jumping back to during to last block specify initial sequence number corresponding is the most erasable, or all subspace is all wiped,
Circulate successively, averagely utilize all subspaces of memory chip, thus increase the service life of memory chip.
It should be appreciated that the application of the present invention is not limited to above-mentioned citing, for those of ordinary skills, can
To be improved according to the above description or to convert, all these modifications and variations all should belong to the guarantor of claims of the present invention
Protect scope.
Claims (10)
1. the erasable implementation method of a memory chip, it is characterised in that include step:
When data memory to be stored inputs memory chip, then judge in memory chip according to data memory size to be stored
Divide in the many sub spaces obtained and the most all have write data；Wherein, the memory headroom of each subspace is all higher than or is equal to
Data memory size to be stored；
When there being subspace not write data, then by data memory write to be stored, and it is marked.
The most erasable implementation method of memory chip, it is characterised in that described data memory to be stored
During input memory chip, then judge memory chip divides the many sub spaces obtained according to data memory size to be stored
In the most all have write data step specifically include:
When data memory to be stored inputs memory chip, read the maximum operating sequence number in subspace, and judge to operate sequence
Number the maximum block number whether aliquot memory headroom is bisected into；Described operation sequence number be written in subspace to be stored
Data memory time arrange；
When aliquot, then without the writable data in subspace；
When aliquant, then there are the writable data in subspace.
The most erasable implementation method of memory chip, it is characterised in that described when there being subspace not write
When entering data, then by data memory write to be stored, and the step being marked specifically includes:
If during the block number that the aliquant memory headroom of maximum of operation sequence number is bisected into, then positioning and operation sequence number not being set
Subspace in one of；
By data memory write to be stored, and the maximum that the operation sequence number of this subspace is set to operate sequence number adds 1, and returns
Receipt row judges to operate the maximum block number whether aliquot memory headroom is bisected into of sequence number.
The most erasable implementation method of memory chip, it is characterised in that also include:
If during the block number that the maximum aliquot memory headroom of operation sequence number is bisected into, then positioning action serial number is specified initial
The subspace of sequence number, after wiping the operation sequence number of data and all subspaces in this subspace, writes data memory to be stored
Enter this subspace, and be still set to the operation sequence number of this subspace specify initial sequence number.
The most erasable implementation method of memory chip, it is characterised in that also include:
If during the block number that the maximum aliquot memory headroom of operation sequence number is bisected into, then by subspace each in memory chip
Data and operation sequence number all wipe, location be not set operation sequence number subspace in one of, in this subspace
Write data memory to be stored, and be set to the operation sequence number of this subspace specify initial sequence number.
The most erasable implementation method of memory chip, it is characterised in that described data memory to be stored
During input memory chip, then judge memory chip divides the many sub spaces obtained according to data memory size to be stored
In the most all have write data step before also include:
Obtain data memory size to be stored；
The memory headroom of memory chip is divided into polylith subspace；Wherein, the total block data of subspace is less than or equal to memory core
The storage total capacity of sheet is divided by data memory size to be stored, and the memory headroom of each subspace is all higher than or equal to be stored
Data memory size, each subspace is provided with storage operation sequence number region.
7. the erasable of a memory chip realizes system, it is characterised in that including:
Judge module, when data memory input memory chip to be stored, then judges in memory chip according to be stored
Data memory size and divide in the many sub spaces obtained and the most all have write data；Wherein, the internal memory of each subspace is empty
Between be all higher than or equal to data memory size to be stored；
Write and mark module, for when there being subspace not write data, then by data memory write to be stored, go forward side by side
Line flag.
The most according to claim 7, the erasable of memory chip realizes system, it is characterised in that described judge module specifically wraps
Include:
Sequence number acquiring unit, when data memory input memory chip to be stored, reads and operates sequence number in subspace
Big value, and judge to operate the maximum block number whether aliquot memory headroom is bisected into of sequence number；Described operation sequence number be
Subspace is arranged when being written into data memory to be stored；
Divide exactly control unit, for when aliquot, then without the writable data in subspace；
Non-divide exactly control unit, for when aliquant, then have the writable data in subspace.
The most according to claim 8, the erasable of memory chip realizes system, it is characterised in that said write and mark module bag
Include:
Positioning unit, if for operation sequence number the aliquant memory headroom of maximum be bisected into block number time, then position not
Be set in the subspace of operation sequence number is one of；
Write control unit, for being write by data memory to be stored, and is set to the operation sequence number of this subspace operate sequence
Number maximum add 1, and start sequence number acquiring unit.
The most according to claim 8, the erasable of memory chip realizes system, it is characterised in that also include:
Write full control module, if for operation sequence number maximum aliquot memory headroom be bisected into block number time, then position
Operation serial number specifies the subspace of initial sequence number, after wiping the operation sequence number of data and all subspaces in this subspace, and will
Data memory to be stored writes this subspace, and is still set to the operation sequence number of this subspace specify initial sequence number.
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| CN201610410343.4A CN106095338A (en) | 2016-06-13 | 2016-06-13 | The erasable implementation method of a kind of memory chip and realize system |
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| CN201610410343.4A CN106095338A (en) | 2016-06-13 | 2016-06-13 | The erasable implementation method of a kind of memory chip and realize system |
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| CN201610410343.4A Pending CN106095338A (en) | 2016-06-13 | 2016-06-13 | The erasable implementation method of a kind of memory chip and realize system |
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