CN106094669B - A kind of principal and subordinate's disk shares the system and method for PCB - Google Patents

Abstract

The present invention provides a kind of system and method for the shared PCB of principal and subordinate's disk, and by welding corresponding component and connector in different positions number, realization principal and subordinate's disk shares PCB.System includes master, from disk；Master includes CPU platform control units, clock unit 1, FPGA peripheral circuit unit 1, connector 1；Include clock unit 2, FPGA peripheral circuit unit 2, connector 2 from disk；CPU platform control units are separately connected with clock unit 1, FPGA peripheral circuit unit 1, connector 1；Connector 1 is connect with connector 2, and connector 2 is separately connected with clock unit 2, FPGA peripheral circuit unit 2；The CPU platform control units complete the configuration of two clock units and two FPGA peripheral circuit units.The present invention can become a PCB design by PCB design twice, save a PCB design cost, become purchasing a kind of material from purchasing two kinds of materials when PCB stocks up, the type of material becomes single and is convenient for management and control, the secondary reduction of cost of material.

Description

A kind of principal and subordinate's disk shares the system and method for PCB

Technical field

The present invention relates to a kind of sides for solving principal and subordinate's disk and sharing PCB in wireless mobile communications product optic-fiber repeater system Method.

Background technology

With the continuous development of the communication technology and the establishment of Chinese steel tower limited liability company, existing optical fiber direct amplification system Uniting, it is impossible to meet the market demands directly to put so multi-standard repeater or even full system type pictorial repeater have a vast market foreground The framework for system product of standing becomes more complicated.

Generally require central processing unit in traditional product, FPGA, clock unit, power supply unit, high-speed AD, high speed D/A, Frequency mixer and modem, frequency converter, low-noise amplifier, power amplifier, and peripheral monitoring unit circuit, with The increase radio frequency link and igh-speed wire-rod production line link of radio frequency standard will constantly increase, and become more multiple so as to cause PCB It is miscellaneous.For product before since standard is single, the area of PCB is small, and single PCB can meet product demand.With the communication technology Continuous development and Chinese steel tower limited liability company establishment, it is impossible to meet markets to need for existing Fiber repeater system It asks, due to being limited to the size and cost of cabinet, so that cabinet is it is not possible that do is too big, it is necessary to do two or more PCB realizes function, but again must only there are one control unit, in order to cost-effective and company is facilitated to stock up demand, A kind of method that PCB is shared using principal and subordinate's disk.

Invention content

The present invention provides a kind of method that solution principal and subordinate's disk shares PCB, and principal and subordinate's disk shares same PCB, by difference Position number weld corresponding component（That is 0 Ohmic resistance）And connector, realize that principal and subordinate's disk shares PCB.

Specific technical solution is as follows：

The system that a kind of principal and subordinate's disk shares PCB, including master, from disk；Master includes CPU platform control units, clock list Member 1, FPGA peripheral circuit unit 1, connector 1；Include clock unit 2, FPGA peripheral circuit unit 2, connector 2 from disk；CPU Platform control unit is separately connected with clock unit 1, FPGA peripheral circuit unit 1, connector 1；Connector 1 connects with connector 2 It connects, connector 2 is separately connected with clock unit 2, FPGA peripheral circuit unit 2；When the CPU platform control units complete two The configuration of clock unit and two FPGA peripheral circuit units.

The master further includes high-speed data processing link module 1, power amplifier state detection module 1, temperature Sensor assembly 1；CPU platform control units realize the monitoring to above-mentioned module；It includes height that high-speed data, which handles link module 1, A/D module 1 and high speed D/A module 1；Clock unit 1 is to high speed AD module 1, the core of high speed D/A module 1, FPGA peripheral circuit unit 1 Heart device fpga1 provides clock signal；The FPGA peripheral circuit unit 1 completes processing and the high speed AD module of digital signal 1 and high speed D/A module 1 interface circuit；

It is described from disk further include high-speed data processing link module 2, power amplifier state detection module 2, temperature Sensor assembly 2；CPU platform control units realize the monitoring to above-mentioned module；It includes height that high-speed data, which handles link module 2, A/D module 2 and high speed D/A module 2；Clock unit 2 is to high speed AD module 2, the core of high speed D/A module 2, FPGA peripheral circuit unit 2 Heart device fpga2 provides clock signal；The FPGA peripheral circuit unit 2 completes processing and the high speed AD module of digital signal 2 and high speed D/A module 2 interface circuit.

A method of principal and subordinate's disk based on above system shares PCB, includes the following steps,

Step 1, mainboard power on, and CPU platform control units complete the startup configuration of itself on mainboard, detect the electricity of periphery The whether normal work in place of the device on road；FPGA peripheral circuit unit 1 and clock unit 1 are detected when detection first, if more than Unit is normal, then detects high-speed data processing link module 1；

The peripheral circuit unit 1 of step 2, the clock unit 1 on mainboard configuration mainboard and FPGA, then pass through the peripheries FPGA Circuit unit 1 goes configuration high speed AD module 1 and high speed D/A module 1；

Step 3, mainboard detect whether to be initially configured from the clock circuit 2 on plate with the presence of from plate if there is from plate existing And FPGA peripheral circuit unit 2, then configuration high speed AD module 2 and high speed D/A module 2 are gone by FPGA peripheral circuit unit 2；

Mainboard and from plate all normally start after, just complete the normal startup of whole system.

Compared with prior art, the present invention has the following advantages and beneficial effect：

Compared with prior art, the present invention can become a PCB design by PCB design twice, save a PCB and set Cost is counted, becomes purchasing a kind of material from two kinds of materials of buying when PCB stocks up, the quantity only purchased becomes 2 times, while same The quantity of kind material procurement is bigger, and the cost of buying can further decrease.Therefore the type of material becomes single and is convenient for management and control, The cost of material secondary can also reduce.

Description of the drawings

Fig. 1 is mainboard and from plate connection diagram.

Fig. 2 is CPU peripheral circuit diagrams.

Fig. 3 is the peripheral circuit diagram of CPU control clocks.

Fig. 4 is the peripheral circuit diagram of CPU configurations FPGA.

Fig. 5 is the circuit diagram of the data interaction and bus extension between CPU and FPGA.

Fig. 6 is to communicate to connect circuit diagram between principal and subordinate's disk.

Specific implementation mode

The technical solution that the present invention will be described in detail with reference to the accompanying drawings and examples.

Master includes CPU platform control units, clock unit 1, FPGA peripheral circuit unit 1, connector 1；Include from disk Clock unit 2, FPGA peripheral circuit unit 2, connector 2；CPU platform control units and clock unit 1, FPGA peripheral circuit list Member 1, connector 1 are separately connected；Connector 1 is connect with connector 2, connector 2 and clock unit 2, FPGA peripheral circuit unit 2 It is separately connected；

The CPU platform control units of master complete two clock units of whole system and two FPGA peripheral circuit lists The each function module of configuration and whole system of member（Including high-speed data processing link module 1, power amplifier shape State detection module 1, temperature sensor module 1, high-speed data processing link module 2, power amplifier state detection module 2, temperature sensor module 2）Monitoring；

Clock unit on two disks gives respective high speed AD module, high speed D/A module, when the devices such as fpga provide respectively Clock signal；High speed AD module, high speed D/A module are included in high-speed data processing link module；

FPGA peripheral circuit unit on two disks, be respectively completed respective digital signal processing and high speed AD module and The interface circuit of D/A module；

Principal and subordinate's disk share PCB method include the following steps,

Step 1, mainboard power on, CPU completed on mainboard itself startup configuration, detect periphery circuit device whether Normal work in place；FPGA peripheral circuit unit 1 and clock unit 1 are detected when detection first, if the above unit is normal, then is examined It surveys high-speed data and handles link module 1.

The peripheral cell circuit 1 of step 2, the clock unit 1 on mainboard configuration mainboard and FPGA, then pass through the peripheries FPGA Element circuit removes the devices such as configuration high speed AD module 1 and high speed D/A module 1；

Step 3, mainboard detect whether to be initially configured from the clock circuit 2 on plate with the presence of from plate if there is from plate existing And FPGA peripheral circuit unit 2, then configuration high speed AD module 2 and high speed D/A module 2 etc. are gone by FPGA peripheral circuit unit 2 Device；

When mainboard and after plate all normally starts, whole equipment just completes the normal startup of equipment.

The first step：According to figure two, corresponding pin attribute is configured to according to hardware connection in CPU programs, PA15 and PA16 is respectively the chip select pin of the spi bus of clock chip, and PA11/PA12/PA13 distinguishes the number of the spi bus of clock chip According to output, data input, clock pins.PA17/PA18 is respectively the reset pin of clock chip.PA4/PA5/PA6/PA7/ PA8 and PA26/PA27/PA28/PA29/PA30 is respectively to configure mainboard FPGA and the configuration pin from plate FPGA.PA25 and PA31 is the reset pin that CPU controls principal and subordinate's disk FPGA.It is connected to two-way spi bus between CPU and principal and subordinate's disk FPGA simultaneously, is drawn Foot PA0/PA1 and PA9/PA10 are the configuration pin of spi bus, and PA21/PA22/PA23 distinguishes the data input of spi bus, number According to output and clock pins.

Second step：（Such as figure one）Shown mainboard directly configures FPGA and clock by CPU, and mainboard is by connector 1 and even Connect low speed line configuration FPGA and the clock between device 2.

Third walks：In figure three, figure four, all labels are without the electricity corresponding to cabling behind the network name of@symbols in figure five Resistance is welded on mainboard, is not welded from plate.Resistance behind all network names of the label with@symbols corresponding to cabling are from plate Upper welding, is not welded on mainboard.

4th step：The solder connector CN8 on mainboard, from plate solder connector CN9, then mainboard and between plate again Using a low speed connecting line, it is achieved that principal and subordinate's disk shares the method that PCB realizes principal and subordinate's function.

Specific embodiment described herein is only an example for the spirit of the invention.Technology belonging to the present invention is led The technical staff in domain can make various modifications or additions to the described embodiments or replace by a similar method In generation, however, it does not deviate from the spirit of the invention or beyond the scope of the appended claims.

Claims (3)

1. a kind of mainboard and the system for using identical PCB typesettings from plate, it is characterised in that：Including master, from disk；Master includes CPU platform control units, clock unit 1, FPGA peripheral circuit unit 1, connector 1；Include clock unit 2, outside FPGA from disk Enclose circuit unit 2, connector 2；CPU platform control units are distinguished with clock unit 1, FPGA peripheral circuit unit 1, connector 1 Connection；Connector 1 is connect with connector 2, and connector 2 is separately connected with clock unit 2, FPGA peripheral circuit unit 2；It is described CPU platform control units complete the configuration of two clock units and two FPGA peripheral circuit units.

2. a kind of mainboard according to claim 1 and the system for using identical PCB typesettings from plate, it is characterised in that：It is described Master further includes high-speed data processing link module 1, power amplifier state detection module 1, temperature sensor module 1； CPU platform control units realize the monitoring to above-mentioned module；It includes high speed AD module 1 and height that high-speed data, which handles link module 1, Fast D/A module 1；Clock unit 1 is to high speed AD module 1, the core devices fpga1 of high speed D/A module 1, FPGA peripheral circuit unit 1 Clock signal is provided；The processing of the completion of FPGA peripheral circuit unit 1 digital signal and high speed AD module 1 and high speed D/A mould The interface circuit of block 1；

It is described from disk further include high-speed data processing link module 2, power amplifier state detection module 2, temperature sensing Device module 2；CPU platform control units realize the monitoring to above-mentioned module；It includes high-speed AD mould that high-speed data, which handles link module 2, Block 2 and high speed D/A module 2；Clock unit 2 is to high speed AD module 2, the core device of high speed D/A module 2, FPGA peripheral circuit unit 2 Part fpga2 provides clock signal；The FPGA peripheral circuit unit 2 completes 2 He of processing and high speed AD module of digital signal The interface circuit of high speed D/A module 2.

3. a kind of mainboard based on system described in claim 2 and the method for using identical PCB typesettings from plate, it is characterised in that： Include the following steps,

Step 1, mainboard power on, and CPU platform control units complete the startup configuration of itself on mainboard, detect the circuit of periphery The whether normal work in place of device；FPGA peripheral circuit unit 1 and clock unit 1 are detected when detection first, if the above unit Normally, then detect high-speed data processing link module 1；

The peripheral circuit unit 1 of step 2, the clock unit 1 on mainboard configuration mainboard and FPGA, then pass through FPGA peripheral circuit Unit 1 goes configuration high speed AD module 1 and high speed D/A module 1；

Step 3, mainboard detect whether with the presence of from plate, if there is existing from plate, be initially configured from plate clock circuit 2 and FPGA peripheral circuit unit 2, then configuration high speed AD module 2 and high speed D/A module 2 are gone by FPGA peripheral circuit unit 2；

Mainboard and from plate all normally start after, just complete the normal startup of whole system.