CN106093981B - GPS based on optimization parallel code phase search captures circuit - Google Patents
GPS based on optimization parallel code phase search captures circuit Download PDFInfo
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- CN106093981B CN106093981B CN201610397137.4A CN201610397137A CN106093981B CN 106093981 B CN106093981 B CN 106093981B CN 201610397137 A CN201610397137 A CN 201610397137A CN 106093981 B CN106093981 B CN 106093981B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/24—Acquisition or tracking or demodulation of signals transmitted by the system
- G01S19/30—Acquisition or tracking or demodulation of signals transmitted by the system code related
Abstract
The present invention discloses a kind of GPS capture circuits based on optimization parallel code phase search, including：Lower frequency changer circuit, downsampling circuit, fast Fourier transform circuit, delay circuit, C/A code generation circuits, inversefouriertransform circuit, coherent integration circuit, mod circuit, non-coherent integration circuit, threshold judgement circuit；It need not reorder to output data in IFFT operations, it is final only to obtain receiving signal C/A code phases, to save the consumption of memory in IFFT modules to maximum peak-to-average force ratio position into line position bit reversal；And this programme can be used for capturing the arbitrary satellite-signal of GPS, in the case where hardware resource is abundant, acquisition speed can be significantly improved under the premise of not changing frequency search step-length, cold start-up capture time is 1.17 seconds, thermal starting capture time is less than 0.5 second, acquisition sensitivity can reach -145dBm simultaneously, to ensure can also to complete to capture when pickup electrode is weak.
Description
Technical field
The invention belongs to GPS global satellite positionings field, more particularly to the parallel code phase search after a kind of optimization
Capture framework.
Background technology
GPS is the abbreviation of global positioning system (Global Positioning System), by U.S. Department of Defense in previous generation
It records and is proposed the seventies, be one and be based on artificial satellite, the round-the-clock radio-positioning towards the whole world, timing system.GPS system
Mainly it is made of three independent sectors：Space constellation part, ground monitoring part and customer equipment part.It rises space constellation part
It is just made of 21 operational satellites and 3 backup satellites, but is currently in the number of satellite of normal operating condition more than 30,
These satellite distributions are on 6 tracks；Ground monitoring part mainly (is located at section of U.S. sieve by 1 master station for being distributed in the whole world
The fields La Duozhouchun city), 4 injection stations and 6 monitoring station compositions are mainly responsible for the monitoring of satellite, the calculating and transmission of ephemeris, number
According to acquisition etc.；The main task of customer equipment part (i.e. GPS receiver) is the visible GPS satellite of tracking, to the satellite received
Radio signal obtains the measured value and navigation information needed for positioning after data processing, finally completes the positioning fortune to user
Calculation and navigation task.
GPS receiver is mainly made of 3 parts：Radio-frequency front-end, base band signal process and user location resolve.Its
In, base band signal process is the core of GPS receiver, and main includes capture and tracking module, capture are one to satellite
Doppler shift and C/A code phases two-dimensional search process, the current visible satellite number of trapping module output, Doppler shift
With C/A code phases；Tracking module completes the follow-up tracing task to satellite, after output navigation information bit and pseudo-range information are used for
Continuous user location resolves.And it captures framework and can be mainly divided into 3 kinds：Serial search framework (SS), parallel frequency search framework
(PFS) and parallel code phase search framework (PCS)：
Serial search framework (SS)：Serial search framework is most traditional framework, including 1) is multiplied with local IF carrier；
2) it is multiplied with local CA codes；3) coherent integration；4) modulus；5) non-coherent integration.The construction characteristic is to realize simple, hardware consumption
It is few, but it carries out serial search to frequency and code phase, and capture time is very long.
Parallel frequency search framework (PFS)：For parallel frequency search framework by frequency search procedure parallelization, which can be with
Simultaneously scan for NBA code phase can obtain N in figure simultaneously every timeBCoherent integration results of a code phase, but FFT is needle
To same multiple coherent integration results all the way, so needing the caching (Ping-pong of a ping-pong structure in the pre-fft
Buffer the function of reordering) is completed.The characteristics of framework, is omitted the process of frequency search, has saved capture time.But
There is also defects for the framework：In the case of frequency deviation is larger, the loss of sensitivity of presence signal, the frequency deviation is lost and sinc (π
fdNch/fs) directly proportional, wherein NchBe coherent integration number (here, the purpose of coherent integration be signal is carried out it is smooth, with
Reduce the points of follow-up FFT), fsIt is the sample rate of signal, fdIndicate Doppler shift；Secondly, the frequency domain resolution of FFT also can
Lead to additional loss of sensitivity.
Parallel code search framework (PCS)：For parallel code search framework by code search process parallelization, the advantages of framework is only
Frequency deviation need to be searched for, eliminate the search process of code phase, saved capture time.The shortcomings that framework is that FFT points must
Must be 2 power, which limits the sample rates of signal, otherwise just need through additional processing (such as average sample circuit)
To meet the limitation of FFT points；In addition, sometimes in order to reduce the points (if signal sampling rate is relatively high) of FFT, it is also desirable to
Average sample circuit is completed down-sampled.The framework can simultaneously scan for NBA frequency point, but the framework needs to consume a large amount of FFT
Unit.
Invention content
The present invention is in order to solve the above technical problems, propose a kind of GPS capture electricity based on optimization parallel code phase search
Road, the search speed for improving GPS trapping modules.
The technical solution adopted by the present invention is：GPS based on optimization parallel code phase search captures circuit, including：Lower change
Frequency circuit, downsampling circuit, fast Fourier transform circuit, delay circuit, C/A code generation circuits, inversefouriertransform circuit,
Coherent integration circuit, mod circuit, non-coherent integration circuit, threshold judgement circuit；
Input of the digital medium-frequency signal as lower frequency changer circuit, the output of the lower frequency changer circuit are defeated as downsampling circuit
Enter, the input of the downsampling circuit exported as fast Fourier transform circuit, the output of the Fast Fourier Transform
As the input of delay circuit, export to obtain the first signal by delay circuit；The output of the delay circuit is generated with C/A codes
Input of the multiplied second signal arrived of the output phase of circuit as inversefouriertransform circuit, the second signal includes several
Road signal, input of the output as coherent integration circuit of the inversefouriertransform circuit, the coherent integration circuit it is defeated
Go out the input as mod circuit, the input of the mod circuit exported as non-coherent integration circuit, the incoherent product
Input of the output of parallel circuit as threshold judgement circuit, the threshold judgement circuit output court verdict；
The lower frequency changer circuit includes：First memory module, data converter, digital frequency synthesizer；In the number
Frequency signal is initially stored in the first memory module, the input of the first memory module exported as data converter, the data
Output of the result that the output of converter is multiplied with the output of digital frequency synthesizer as lower frequency changer circuit；
The downsampling circuit includes：Low-pass filter, 8 times of down sample modules, second memories；The low-pass filter
Input of the output as 8 times of down sample modules, the input of 8 times of down sample modules exported as second memory, institute
State output of the output of second memory as downsampling circuit；
The Fast Fourier Transform Block includes：First Fast Fourier Transform (FFT) unit, the downsampling circuit it is defeated
Go out the output as fast Fourier transform module；
The delay circuit includes several delay units, and several delay units line up array format, each delay
Unit corresponds to the tributary signal in the first signal all the way, the delay for carrying out a clock cycle to the road signal, and described
The input of delay circuit is the output of fast Fourier transform module, and the output of several delay units is together as delay circuit
Output；
The C/A code generation circuits include：C/A code generators, the second Fast Fourier Transform (FFT) unit, code offset compensation list
Member；Input of the C/A codes that the C/A code generators generate as the second fast Fourier transform unit, second quick Fu
Output of the result that the output of vertical leaf transformation unit is multiplied with code offset compensation unit as C/A code generation circuits；
The inversefouriertransform circuit includes several inversefouriertransform units, several inversefouriertransform units
Array format is lined up, each inversefouriertransform unit corresponds to the tributary signal in second signal all the way, for believing the road
Number carry out using 1kHz as the parallelization of the frequency domain search at interval；
The coherent integration circuit includes several coherent integration arithmetic elements, and several coherent integration arithmetic elements are lined up
Permutation form, each coherent integration arithmetic element correspond to an inversefouriertransform unit；
The mod circuit includes several modulus arithmetic elements, and several modulus arithmetic elements line up array format, often
One modulus arithmetic element corresponds to a coherent integration arithmetic element；
The non-coherent integration circuit includes several non-coherent integration arithmetic elements, several non-coherent integration operation lists
Identical permutation corresponds to a modulus arithmetic element at array format, each non-coherent integration arithmetic element；
The threshold judgement circuit includes：Peak-to-average force ratio counting circuit, first peak compare than comparison module, the second peak-to-average force ratio
Module；The peak-to-average force ratio computing module includes several peak-to-average force ratio computing units, and several peak-to-average force ratio computing units line up array
Form, each peak-to-average force ratio computing unit correspond to a non-coherent integration computing unit；The output of the peak-to-average force ratio computing module
As first peak than the input of comparison module, the first peak compares mould than the output of comparison module as the second peak-to-average force ratio
The input of block.
Further, the first memory depth be 1638400, width be 2 bits, write clock 16.386MHz,
Reading clock is 147.456MHz.
Further, the pass band bandwidth is 2.046MHz.
Further, the second memory depth is 204800.
Further, the code offset compensation unit is twiddle factor
Beneficial effects of the present invention：The GPS based on optimization parallel code phase search of the present invention captures circuit, including：Under
Frequency changer circuit, downsampling circuit, fast Fourier transform circuit, delay circuit, C/A code generation circuits, inversefouriertransform electricity
Road, coherent integration circuit, mod circuit, non-coherent integration circuit, threshold judgement circuit；In inversefouriertransform IFFT operations
The application need not reorder to output data, final only to be obtained to maximum peak-to-average force ratio position into line position bit reversal
To signal C/A code phases are received, to save the consumption of memory in IFFT modules；And the technical solution of the application meets
The engineering parameter of GPS general purpose receivers designs, and can be used for capturing the arbitrary satellite-signal of GPS, in the situation that hardware resource is abundant
Under, the speed of capture can be significantly improved under the premise of not changing frequency search step-length, the scheme of the application compares PCS frameworks
Speed improves 10 times, and cold start-up capture time is 1.17 seconds, and thermal starting capture time is less than 0.5 second, while being captured sensitive
Degree can reach -145dBm, to ensure can also to complete to capture when pickup electrode is weak.
Description of the drawings
Fig. 1 is the schematic diagram of modified parallel code phase search framework.
Fig. 2 is relevant or non-coherent integration structure schematic diagram.
Fig. 3 is the schematic diagram of trapping module framework.
Specific implementation mode
For ease of those skilled in the art understand that the present invention technology contents, below in conjunction with the accompanying drawings to the content of present invention into one
Step is illustrated.
It is core of the invention framework modified parallel code phase search PCS* type frame structures as shown in Figure 1, it specifically will be
It is described in detail in the application technical solution as shown in Figure 3 below.
It is illustrated below in conjunction with attached drawing, according to the theory of Digital Signal Processing, goes the process of carrier wave that can pass through frequency domain
Displacement realize.For the FFT of 1ms, frequency domain moves a sampled point and is equivalent to be multiplied by the carrier wave of 1KHz.Then I
Be improved the multidiameter delay PCS structures of type and can be searched simultaneously as shown in Figure 1, the structure saves part FFT module
Rope NBA frequency point ..., fIF-2000,fIF-1000,fIF,fIF+1000,fIF+2000,…}。
The application has carried out search precision to tetra- kinds of frameworks of SS, PFS, PCS, PCS* and hardware complexity compares, such as 1 institute of table
Show：
The comparison of 1 four kinds of capture frameworks of table
Here, the search degree of parallelism N of SS and PFS type frame structureB=200.Since the value of C/A codes is ± 1, so SS and PFS
Multiplier need not be consumed with being multiplied for local C/A codes in type frame structure, only need to do corresponding addition and subtraction in coherent accumulation.
On search precision, SS, PFS, PCS and PCS* type frame structure all use the C/A code phases of 1/2 chip and the frequency deviation search essence of 50Hz
It spends, that is, frequency deviation step-size in search, the search range in the application is ± 10kHz, so, FFT in PCS and PCS* type frame structures
Points are 2048；Three kinds of frameworks all use 10ms coherent integrations and 10 non-coherent integrations.Coherent integration number in PFS type frame structures
Nch=10, so FFT points are also just 2048 points, therefore its frequency domain resolution only has 1000Hz, due to frequency domain parsing spend it is low,
The application does not consider PFS frameworks.In table 1, to the single satellite search time of above-mentioned framework, complex multiplier number and multiple
Number adder number is counted, wherein 2048 point FFT use base 2SDF type frame structure (9 complex multipliers and 11 plural numbers
Adder), 2 single path Time-delayed Feedback structure of base 2SDF type frame structure, that is, base is the current more general realization sides pipeline-type FFT
The structure that the IP kernel of pipeline-type FFT generally uses in case, and current FPGA.For the hardware efficiency of computing architecture, i.e., singly
The hardware complexity of multiplier is pressed 10 by the throughput of plane product:1 ratiometric conversion at adder, i.e. 1 multiplier area=
10 adder areas, and the hardware efficiency of SS type frame structures is normalized, obtain the hardware efficiency estimation of other frameworks.Statistics knot
Fruit is as shown in table 1, and modified parallel code phase search framework has prodigious advantage on hardware efficiency, so the application uses
PCS* type frame structures.
As shown in figure 3, being the application based on optimization parallel code phase search PCS* type frame structures obtained trapping module
The technical solution of Organization Chart, the application is：GPS based on optimization parallel code phase search captures circuit, including：Down coversion electricity
Road, downsampling circuit, fast Fourier transform circuit, C/A code generation circuits, inversefouriertransform circuit, coherent integration circuit,
Mod circuit, non-coherent integration circuit, threshold judgement circuit；
The lower frequency changer circuit includes：First memory module IF_RAM, data converter Data_convert, numerical frequency
Synthesizer DDS；Digital medium-frequency signal is stored in first in first memory IF_RAM, and the depth of IF_RAM is 1638400, wide
Degree is 2 bits, that is, stores the intermediate frequency data of 100ms, and the application uses 10ms coherent integrations and 10 non-coherent integrations, captures mould
The processing clock of block uses 147.456MHz.Since ADC sampling A/D chips MAX2769 has carried out 2 bits of encoded to sampled data, need
Want data converter Data_convert that the intermediate frequency data of 2 bits of encoded is converted to complement of two's two's complement form, then with directly
The local quadrature carrier that digital frequency synthesizer DDS is generated is multiplied, the application frequency deviation search range be set as -10kHz~+
10kHz, frequency domain search step-length is 50Hz, due to using modified parallel code phase search framework PCS*, DDS module only to need to complete
Frequency domain search in 1kHz, i.e. frequency point [2565000,2565050,2565100,2565150,2565200,2565250,
2565300,2565350,2565400,2565450,2565500,2565550,2565600,2565650,2565700,
2565750,2565800,2565850,2565900,2565950]Hz。
The downsampling circuit includes：Low-pass filter LPF, 8 times of down sample modules, second memory RAM；After down coversion
Baseband signal by low-pass filter LPF, the bandwidth of filter is 2.046MHz, which makes an uproar outside for filtering out band
Sound simultaneously does anti-aliased preparation for follow-up down-sampling, and the low-pass filter LPF of the application selects 54 rank FIR filters.By LPF
Afterwards, 8 times of down-samplings are done to signal, to reduce the points of FFT operations below, after 8 times of down-samplings, in 1 C/A code period 1ms
Points be 2048, code phase search precision is about 1/2 chip, since the signal after down-sampling is discontinuous, and assembly line
Type fast Fourier transform module FFT can continuously do FFT operations, so needing to deposit the signal deposit second after down-sampling
In reservoir RAM, second memory depth is 204800, is then continuously read again.
The fast Fourier transform circuit includes：First Fast Fourier Transform (FFT) unit completes 2048 point FFT operations；
The delay circuit includes：Several delay units, several delay units line up array format, each delay unit
Corresponding signal all the way, the delay for carrying out a clock cycle to the road signal, obtains several first branch signals.
The C/A code generation circuits include：C/A code generators, the second Fast Fourier Transform (FFT) unit, code offset compensation list
Member；20 road frequency-region signal is multiplied with the FFT result of the local C/A codes of certain satellite, and the FFT result of local C/A codes needs
A yard migration is done, a corresponding twiddle factor is multiplied by the FFT result of the i-th road C/A codesAfter obtaining yard migration
Local C/A codes frequency-domain result.
Wherein,What time t indicated current FFT processing is t-th millisecond of data,
Int indicates the floor operation to round up.
The inversefouriertransform circuit includes several inversefouriertransform units, several inversefouriertransform units
Array format is lined up, each inversefouriertransform unit corresponds to the output phase of the output and C/A code generation circuits of delay circuit
A tributary signal in 20 tunnel second signals of multiplied Dao, for the IFFT operations to the anti-Fourier's Fast transforms module in 20 tunnels
It completes using 1kHz as the parallelization of the frequency domain search at interval.
The coherent integration circuit includes several coherent integration arithmetic elements, and several coherent integration arithmetic elements are lined up
Permutation form, each coherent integration arithmetic element correspond to an inversefouriertransform unit；The coherent integration arithmetic element
For 10ms coherent integrations, the non-coherent integration arithmetic element is 10 non-coherent integrations.
The mod circuit includes several modulus arithmetic elements, and several modulus arithmetic elements line up array format, often
One modulus arithmetic element corresponds to a coherent integration arithmetic element；
The non-coherent integration circuit includes several non-coherent integration arithmetic elements, several non-coherent integration operation lists
Identical permutation corresponds to a modulus arithmetic element at array format, each non-coherent integration arithmetic element.
The threshold judgement circuit includes：Peak-to-average force ratio counting circuit, first peak compare than comparison module, the second peak-to-average force ratio
Module；The peak-to-average force ratio computing module includes several peak-to-average force ratio computing units, and several peak-to-average force ratio computing units line up array
Form, each peak-to-average force ratio computing unit correspond to a non-coherent integration computing unit；The output of the peak-to-average force ratio computing module
As first peak than the input of comparison module, the first peak compares mould than the output of comparison module as the second peak-to-average force ratio
The input of block.
By the maximum peak-to-average force ratio of integral result compared with detection threshold, if maximum peak-to-average force ratio is more than detection threshold, export
Satellite sat_num, C/A code phase codephase and Doppler shift freq_doppler.It is worth noting that, in anti-Fu
The application need not reorder to output data in leaf transformation unit IFFT operations, and final need to be in place to maximum peak-to-average force ratio institute
It sets into line position bit reversal, obtains receiving signal C/A code phases, to save the consumption of memory in IFFT modules.
The structure of coherent integration and non-coherent integration arithmetic element in the application is as shown in Fig. 2, the application is accumulated with relevant
It is illustrated for point arithmetic element, coherent integration arithmetic element is a multi-accumulator structure, and first C/A code period directly will
Input data is stored in the included memory RAM of coherent integration arithmetic element, and the period later needs present input data with before
The memory RAM that one-accumulate result is carried from relevant integral arithmetic unit is read, and is then added, when accumulative frequency reaches 10 times
(10ms coherent integrations, 10 non-coherent integrations) afterwards, accumulation result is exported.And coherent integration in the application and incoherent
The depth of memory RAM in integral arithmetic unit is 2048.
The acquisition procedure of the application need to do 20 serial frequency deviation search altogether, and each cold start-up includes that 32 the serial of satellite are searched
Rope, acquisition procedure take time 1.17 seconds altogether；And the satellite preserved when last time shutdown is only searched in thermal starting, capture time is less than 0.5
Second, the application uses 8 tracking channels, and most multipotency tracks 8 satellites simultaneously, so trapping module at most needs to search when thermal starting
8 satellites of rope.
Test result
1) performance test
In order to test the present invention to the acquisition speed and accuracy of GPS satellite, we complete the reality of entire GPS receiver
It is existing, including antenna, FPGA plates, rf board and PC, antenna using active GPS antenna, receives frequency ranging from 1575.42 ±
It is Kintex7 XC7K325T that 1MHz, FPGA, which use the KC705 development boards of Xilinx, FPGA models, and rf board is believed using beautiful
(Maxim) the MAX2769 GPS radio frequency chips of company, FPGA plates and rf board use FMC (FPGA Mezzanine Cards)
Interface connects, and is communicated with Ethernet interface between FPGA plates and PC.
Table 2 is that the present invention completes comprehensive (Synthesize) and realized on Xilinx Kintex7 XC7K325T FPGA
(Implement) final resource consumption situation, it is clear that sequential has been restrained, and look-up table (LUT) is in FPGA for patrolling
The basic unit of operation is collected, register (Register) is the basic timing unit in the inside FPGA, and BRAM is FPGA storage insides
Unit is divided into RAMB18E1 and RAMB36E1, and RAMB36E1 is converted to RAMB18E1 here, and DSP48E1 is in FPGA
The DSP operation unit in portion, main to complete to multiply accumulating operation, the percentage in bracket indicates to account for the ratio of FPGA total resources.
Resource consumption of 2 the design of table on Kintex7 XC7K325T FPGA
The GPS receiver of the present invention can not only be accurately positioned the geographical position coordinates of outdoor scene, while in order to accurate
The performance advantage of trapping module is measured, the application completes a large amount of GPS performance tests, occurs by a high performance vector signal
Device generates the satellite air analog signal of GPS, is then input to the development board radio-frequency antenna end of the design.Finally measure cold start-up
Time is 1.17 seconds, and the thermal starting time is less than 0.5 second, while the sensitivity captured can also reach -145dBm, when pickup electrode is weak
Still maintain the search capability inclined to satellite frequency deviation and code.
2) synthesis result
In order to confirm that circuit of the present invention can be executed by FPGA, HDL coded descriptions of the invention carried out it is comprehensive and
Placement-and-routing, and passed through FPGA implementation processes without error.The target devices that FPGA is realized are Kintex7 XC7K325T, but
It is not limited to the fpga chip of the model.Goal time order is the clock frequency of 147.456MHz, which is restrained, practical clock
Frequency can be with higher.Resource consumption situation is 260 DSP48E1,55185 Slice LUTs and 55163 Slice
Registers。
Those of ordinary skill in the art will understand that the embodiments described herein, which is to help reader, understands this hair
Bright principle, it should be understood that protection scope of the present invention is not limited to such specific embodiments and embodiments.For ability
For the technical staff in domain, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made by
Any modification, equivalent substitution, improvement and etc. should be included within scope of the presently claimed invention.
Claims (5)
1. the GPS based on optimization parallel code phase search captures circuit, which is characterized in that including：Lower frequency changer circuit, down-sampling electricity
Road, fast Fourier transform circuit, delay circuit, C/A code generation circuits, coherent integration circuit, are asked inverse-Fourier transform circuit
Moding circuit, non-coherent integration circuit, threshold judgement circuit；
The output of input of the digital medium-frequency signal as lower frequency changer circuit, the lower frequency changer circuit is inputted as downsampling circuit,
Input of the output of the downsampling circuit as fast Fourier transform circuit, the output of the fast Fourier transform circuit
As the input of delay circuit, export to obtain the first signal by delay circuit；The output of the delay circuit is generated with C/A codes
Input of the multiplied second signal arrived of the output phase of circuit as inverse-Fourier transform circuit, the second signal includes several
Road signal, input of the output as coherent integration circuit of the inverse-Fourier transform circuit, the coherent integration circuit it is defeated
Go out the input as mod circuit, the input of the mod circuit exported as non-coherent integration circuit, the incoherent product
Input of the output of parallel circuit as threshold judgement circuit, the threshold judgement circuit output court verdict；
The lower frequency changer circuit includes：First memory module, data converter, digital frequency synthesizer；The digital intermediate frequency letter
Number it is initially stored in the first memory module, the input of the output of the first memory module as data converter, the data conversion
Output of the result that the output of device is multiplied with the output of digital frequency synthesizer as lower frequency changer circuit；
The downsampling circuit includes：Low-pass filter, 8 times of down sample modules, second memories；The low-pass filter it is defeated
Go out the input as 8 times of down sample modules, the input of the output of 8 times of down sample modules as second memory, described the
Output of the output of two memories as downsampling circuit；
The fast Fourier transform circuit includes：The output of first fast Fourier transform unit, the downsampling circuit is made
For the input of fast Fourier transform circuit；
The delay circuit includes several delay units, and several delay units line up array format, each delay unit
Tributary signal in corresponding first signal all the way, the delay for carrying out a clock cycle to the road signal, and the delay
The input of circuit is the output of fast Fourier transform circuit, and the output of several delay units is together as the defeated of delay circuit
Go out；
The C/A code generation circuits include：C/A code generators, the second fast Fourier transform unit, code offset compensation unit；Institute
Input of the C/A codes of C/A code generators generation as the second fast Fourier transform unit is stated, second fast Flourier becomes
Change the output of result that the output of unit is multiplied with code offset compensation unit as C/A code generation circuits；
The inverse-Fourier transform circuit includes several inverse-Fourier transform units, and several inverse-Fourier transform units are lined up
Array format, each inverse-Fourier transform unit correspond to the tributary signal all the way in second signal, for the road signal into
Row is using 1kHz as the parallelization of the frequency domain search at interval；
The coherent integration circuit includes several coherent integration arithmetic elements, and several coherent integration arithmetic elements line up permutation
Form, each coherent integration arithmetic element correspond to an inverse-Fourier transform unit；
The mod circuit includes several modulus arithmetic elements, and several modulus arithmetic elements line up array format, each
Modulus arithmetic element corresponds to a coherent integration arithmetic element；
The non-coherent integration circuit includes several non-coherent integration arithmetic elements, several non-coherent integration arithmetic element rows
Array format is arranged into, each non-coherent integration arithmetic element corresponds to a modulus arithmetic element；
The threshold judgement circuit includes：Peak-to-average force ratio counting circuit, first peak compare mould than comparison module, the second peak-to-average force ratio
Block；The peak-to-average force ratio computing module includes several peak-to-average force ratio computing units, and several peak-to-average force ratio computing units line up array shape
Formula, each peak-to-average force ratio computing unit correspond to a non-coherent integration computing unit；The output of the peak-to-average force ratio computing module is made
It is first peak than the input of comparison module, the first peak is than the output of comparison module as the second peak-to-average force ratio comparison module
Input.
2. the GPS according to claim 1 based on optimization parallel code phase search captures circuit, which is characterized in that described
First memory module depth is 1638400, and width is 2 bits, and write clock 16.386MHz, reading clock is
147.456MHz。
3. the GPS according to claim 1 based on optimization parallel code phase search captures circuit, which is characterized in that described
Pass band bandwidth is 2.046MHz.
4. the GPS according to claim 1 based on optimization parallel code phase search captures circuit, which is characterized in that described
Second memory depth is 204800.
5. the GPS according to claim 1 based on optimization parallel code phase search captures circuit, which is characterized in that described
Code offset compensation unit is twiddle factor
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| CN106597489B (en) * | 2016-12-14 | 2018-12-07 | 中国人民解放军国防科学技术大学 | A kind of more pilot channel software parallel method of reseptances of satellite navigation |
| CN106772481B (en) * | 2016-12-14 | 2019-05-24 | 中国人民解放军国防科学技术大学 | A kind of software parallel Related Computational Methods based on inner product of vectors |
| CN108802774A (en) * | 2018-05-30 | 2018-11-13 | 北京航空航天大学 | A kind of GPS navigation baseband system grade chip |
| CN109239744B (en) * | 2018-10-19 | 2020-10-09 | 杭州电子科技大学 | Rapid anti-bit-reversal rapid capturing method based on complex signal phase |
| CN109917429B (en) * | 2019-03-07 | 2023-09-12 | 西安开阳微电子有限公司 | Method and device for capturing B1C weak signals and computer storage medium |
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| US7436356B2 (en) * | 2005-07-26 | 2008-10-14 | Mstar Semiconductor, Inc. | Method of cross-correlation and continuous wave interference suppression for GPS signal and associated GPS receiver |
| CN101246210B (en) * | 2008-03-25 | 2011-05-04 | 南京航空航天大学 | GPS locating method |
| CN101308204B (en) * | 2008-05-30 | 2011-05-04 | 北京航空航天大学 | Multisystem satellite navigation correlator |
| CN101625404B (en) * | 2008-07-09 | 2012-02-29 | 杭州中科微电子有限公司 | GPS signal large-scale parallel quick capturing method and module thereof |
| CN102662183B (en) * | 2012-04-27 | 2013-07-24 | 桂林电子科技大学 | Method and system for global position system (GPS) signal capture |
| CN103630916B (en) * | 2013-11-29 | 2017-04-26 | 西安电子科技大学昆山创新研究院 | Code capturing method based on dual-FFT frequency domain filtering |
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