CN106067788B - High-frequency interference filtering circuit - Google Patents
High-frequency interference filtering circuit Download PDFInfo
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- CN106067788B CN106067788B CN201610421360.8A CN201610421360A CN106067788B CN 106067788 B CN106067788 B CN 106067788B CN 201610421360 A CN201610421360 A CN 201610421360A CN 106067788 B CN106067788 B CN 106067788B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Abstract
A high-frequency interference filter circuit comprises a forward charge and discharge circuit, a reverse charge and discharge circuit and a data selector. The high-frequency interference filtering circuit controls and gates one of the forward charging and discharging circuit and the reverse charging and discharging circuit as an output pulse through the data selector. The high-frequency interference filtering circuit can automatically filter the positive narrow pulse in the negative wide pulse period and the negative narrow pulse interference in the positive wide pulse period, and particularly can filter continuous narrow pulse interference signals; the maximum width of the positive narrow pulse to be filtered can be adjusted by changing the magnitude of the outflow driving current of the forward current driver or the magnitude of the forward anti-interference capacitor; the maximum width of the negative narrow pulse to be filtered can be adjusted by changing the size of the outflow driving current of the reverse current driver or the size of the reverse anti-interference capacitor. The high-frequency interference filtering circuit can be applied to all occasions needing to filter narrow-pulse interference signals in a digital signal circuit.
Description
Technical Field
The invention relates to a pulse signal processing circuit, in particular to a high-frequency interference filtering circuit.
Background
In digital signal circuits, it is often desirable to filter both positive and negative narrow pulses in a pulse signal, for example, to filter individual narrow interfering pulses, to filter jittered pulses of mechanical tri-state gates, and so forth. The current common method adopts a filter circuit to filter or adopts MCU to sample and then carry out algorithm processing. When the frequency of narrow pulses to be filtered is high, the filter circuit has a direct-current memory effect, and the front narrow pulses can influence the filtering of the rear narrow pulses. When the algorithm processing is carried out after the sampling by the MCU, the MCU is easily influenced by various interferences, thereby influencing the filtering of the narrow pulse.
Disclosure of Invention
In order to solve the problems of narrow pulse filtering in the existing digital pulse signal circuit, the invention provides a high-frequency interference filtering circuit which comprises a forward charging and discharging circuit, a reverse charging and discharging circuit and a data selector.
The input pulse of the high-frequency interference filtering circuit is input from an input pulse end, and the output pulse is output from an output pulse end.
And the input ends of the forward charge-discharge circuit and the reverse charge-discharge circuit are connected to the input pulse end.
The data selector is an alternative data selector; two data input ends of the data selector are respectively connected to the output ends of the forward charge-discharge circuit and the reverse charge-discharge circuit.
The data output end of the data selector is an output pulse end; the data selector performs data selection control by the output pulse.
The forward charge-discharge circuit comprises a forward current driver, a forward anti-interference capacitor and a forward anti-interference Schmitt circuit; the input end of the forward current driver is the input end of a forward charging and discharging circuit, and the output of the forward current driver is connected to the input end of a forward anti-interference Schmitt circuit; one end of the forward anti-interference capacitor is connected to the input end of the forward anti-interference Schmitt circuit, and the other end of the forward anti-interference capacitor is connected to the public ground of the high-frequency interference filter circuit or a power supply of the forward anti-interference Schmitt circuit.
The reverse charging and discharging circuit comprises a reverse current driver, a reverse anti-interference capacitor and a reverse anti-interference Schmitt circuit; the input end of the reverse current driver is the input end of the reverse charge-discharge circuit, and the output end of the reverse current driver is connected to the input end of the reverse anti-interference Schmitt circuit; one end of the reverse anti-interference capacitor is connected to the input end of the reverse anti-interference Schmitt circuit, and the other end of the reverse anti-interference capacitor is connected to the public ground of the high-frequency interference filtering circuit or a power supply of the reverse anti-interference Schmitt circuit.
The output end of the forward anti-interference Schmitt circuit is the output end of the forward charging and discharging circuit, and the output end of the reverse anti-interference Schmitt circuit is the output end of the reverse charging and discharging circuit.
When the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs driving current; when the input of the forward current driver is at a low level, the output end is driven by voltage and outputs a low level; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs driving current; when the input of the reverse current driver is at a high level, the output end is driven by voltage and outputs a low level.
When the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs constant current driving current; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs constant current driving current.
When the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in the same phase relation, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation system; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship.
The specific method that the data selector carries out data selection control by the output pulse is that when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an in-phase relation and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation relation, the low-level control data selector of the output pulse selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship, the low-level control data selector of the output pulse selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector.
The positive narrow pulse width which can be filtered by the high-frequency interference filtering circuit is controlled by changing the positive charging time; the negative narrow pulse width that the high frequency interference filtering circuit can filter is controlled by changing the reverse charging time.
The forward charging time is controlled by changing the magnitude of the outflow driving current of the forward current driver or the magnitude of the forward anti-interference capacitor; the reverse charging time is controlled by changing the size of the outflow driving current of the reverse current driver or the size of the reverse anti-interference capacitor.
The forward anti-interference Schmitt circuit and the reverse anti-interference Schmitt circuit both have high input impedance characteristics.
The invention has the beneficial effects that: the high-frequency interference filtering circuit allows positive pulse and negative pulse signals with widths larger than a specified value to pass through; the filter can automatically filter positive narrow pulses in the negative wide pulse period, and particularly can quickly recover the filtering capacity to filter continuous positive narrow pulse interference signals; the high-frequency interference filtering circuit can automatically filter negative narrow pulses in a positive wide pulse period, and particularly can quickly recover filtering capacity to filter continuous negative narrow pulse interference signals; the maximum width of the positive narrow pulse to be filtered can be adjusted by changing the magnitude of the outflow driving current of the forward current driver or the magnitude of the forward anti-interference capacitor; the maximum width of the negative narrow pulse to be filtered can be adjusted by changing the size of the flowing-out driving current of the reverse current driver or the size of the reverse anti-interference capacitor; the high-frequency interference filtering circuit can be applied to all occasions needing to filter narrow-pulse interference signals in a digital signal circuit.
Drawings
FIG. 1 illustrates an embodiment of a high frequency interference filter circuit;
FIG. 2 is a waveform of an embodiment of a high frequency interference filter circuit;
FIG. 3 is a circuit of embodiment 1 of a forward current driver and a reverse current driver;
FIG. 4 is a circuit of embodiment 2 of a forward current driver and a reverse current driver;
fig. 5 shows a forward current driver and a reverse current driver embodiment 3 circuit.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Fig. 1 shows an embodiment of the high frequency interference filter circuit. In the embodiment, the forward current driver, the forward anti-interference capacitor and the forward anti-interference Schmitt circuit are respectively a current driver U11, a capacitor C11 and a Schmitt circuit F11, and form a forward charging and discharging circuit; the reverse current driver, the reverse anti-interference capacitor and the reverse anti-interference Schmitt circuit are respectively a current driver U21, a capacitor C21 and a Schmitt circuit F21, and form a reverse charging and discharging circuit. One end of the capacitor C11 is connected with the input end of the Schmitt circuit F11, and the other end is connected to the common ground; one end of the capacitor C21 is connected to the input end of the Schmitt circuit F21, and the other end is connected to the common ground. P1 is the input pulse end, P2 is the output pulse end.
In the embodiment, the data selector T11 is an alternative data selector, the two data input signals and the output signal are in-phase, and the schmitt circuit F11 and the schmitt circuit F21 are in-phase schmitt circuit and anti-phase schmitt circuit, respectively, so that the output of the data selector T11 and the input signal of the schmitt circuit F11 are in-phase, and the output of the data selector T11 and the input signal of the schmitt circuit F21 are in anti-phase. The function of the data selector T11 is: when the control terminal A is selected to be 0, outputting Y to be D1; when the control terminal a is selected to be 1, the output Y is D2. The output terminal Y (i.e. the pulse output terminal P2) of the data selector T11 is directly connected to the selection control terminal a of the data selector T11, and when the output pulse P2 is low, the data selector T11 is controlled to select the output signal a3 of the schmitt circuit F11 to be sent to the output terminal Y of the data selector; when the output pulse P2 is at a high level, the data selector T11 is controlled to select the output signal a4 of the schmitt circuit F21 to be supplied to the output terminal Y of the data selector.
Fig. 2 shows waveforms of an embodiment of the high frequency interference filter circuit, which includes an input pulse P1, a schmitt circuit F11 output A3, a schmitt circuit F21 output a4, and an output pulse P2. In fig. 1, when the input pulse P1 is kept at the low level for a long time, the point a1 is at the low level, and the output A3 of the schmitt circuit F11 is at the low level; when the input pulse P1 remains high for a long time, the point a1 is high, and the point A3 is high. When the input pulse P1 changes from high level to low level, the output a1 of the current driver U11 immediately changes to low level potential, and the output A3 immediately changes from high level to low level. When the input pulse P1 changes from low level to high level, the potential of a1 rises due to the charging of the capacitor C11 by the driving current output by the current driver U11, and when the charging time reaches T1 and the potential of a1 rises to reach and exceed the upper limit threshold voltage of the schmitt circuit F11, the potential of A3 changes from low level to high level; when the positive pulse width of the P1 is less than T1, the charging time is less than T1, the P1 becomes low level when the potential of the A1 does not reach the upper limit threshold voltage of the Schmitt circuit F11, the potential of the A1 immediately becomes low level potential, and the A3 maintains the low level state. In fig. 2, the initial states of P1 and A3 are low. The widths of the positive narrow pulse 11 and the positive narrow pulse 12 are both smaller than T1, the potential of A1 cannot reach or exceed the upper limit threshold voltage of a Schmitt circuit F11 after being charged, and the state of A3 is not influenced; the width of the positive pulse 13 of P1 is greater than T1, and therefore, A3 changes from low to high after the rising edge of the positive pulse 13 of P1 by time T1. The falling edge of the negative pulse 19 of P1 changes A3 from high to low, the width of the positive pulse 14 of P1 is greater than T1, and A3 changes from low to high after the rising edge of the positive pulse 14 is over time T1. The falling edge of the negative pulse 20 of P1 changes A3 from high to low, and the width of the positive pulse 15 of P1 is smaller than T1, so that the positive pulse 15 has no effect on A3, and A3 maintains a low state. The width of the positive pulse 16 of P1 is greater than T1, and A3 goes from low to high after the rising edge of the positive pulse 16 is over a time T1.
In fig. 1, when the input pulse P1 is maintained at the low level for a long time, the point a2 is at the high level, and the output a4 of the schmitt circuit F21 is at the low level; when the input pulse P1 remains high for a long time, the point a2 is low and the point a4 is high. When the input pulse P1 changes from low level to high level, the output a2 of the current driver U21 immediately changes to low level potential, and the output a4 immediately changes from low level to high level. When the input pulse P1 changes from high level to low level, the potential of a2 rises due to the charging of the capacitor C21 by the driving current output by the current driver U21, and when the charging time reaches T2 and the potential of a2 rises to reach the upper limit threshold voltage of the schmitt circuit F21, the potential of a4 changes from high level to low level; when the negative pulse width of the P1 is less than T2, the charging time is less than T2, and the A2 potential does not rise to the upper threshold voltage of the Schmitt circuit F21, the P1 becomes high, the A2 immediately becomes low, and the A4 maintains high. In fig. 2, the initial states of P1 and a4 are low. The rising edge of the positive pulse 11 of P1 changes a4 from low to high, the negative pulse 17 of P1 has a width greater than T2, and a4 changes from high to low after the falling edge of the negative pulse 17 for a time T2. The rising edge of the positive pulse 12 of P1 changes a4 from low to high, and the negative pulse 18 of P1 has a width smaller than T2, so that the negative pulse 18 has no effect on a4, and a4 maintains a low state. The widths of the negative pulse 19 and the negative pulse 20 are both smaller than T2, the potential of A2 cannot reach or be higher than the upper limit threshold voltage of the Schmitt circuit F21 after being charged, and the state of A4 is not influenced; the width of the negative pulse 21 of P1 is greater than T2, and therefore, a4 changes from high to low after the falling edge time T2 of the negative pulse 21 of P1. On the rising edge of the positive pulse 16 of P1, a4 changes from low to high.
The output A3 of the schmitt circuit F11 remains low when the input pulse P1 is low, and becomes high after a time T1 after the input pulse P1 changes from low to high. The output a4 of the schmitt circuit F21 remains high when the input pulse P1 is high, and becomes low after the input pulse P1 changes from high to low for a time T2. Alternatively, when A3 is high, a4 must be high; when a4 is low, A3 is necessarily low.
In fig. 2, the initial states of A3 and a4 are both low, the output Y of the data selector T11 is low, and the data selector T11 selects A3 as the output Y and maintains it while A3 is low. When A3 changes from low to high at edge 30, output Y changes to high, and data selector T11 selects a4 as output Y, at which time a4 is necessarily high, maintaining the high state of output Y. When a4 changes from high to low at edge 31, the output Y changes to low, and the data selector T11 selects A3 as the output Y, at which time A3 is necessarily low, maintaining the low state of the output Y. When A3 changes from low to high on edge 32, output Y changes to high, and data selector T11 selects a4 as output Y, at which time a4 is necessarily high, maintaining the high state of output Y.
The high-frequency interference filtering circuit filters out narrow pulses 11, 12, 19 and 20 in the P1 signal, while positive wide pulses 13 (including positive pulses 13, 14 and 15, negative pulses 19 and 20 being interference pulses in the positive wide pulses) and negative wide pulses 21 can pass through, so that corresponding positive wide pulses 22 and negative wide pulses 23 appear in the P2 signal. The output pulse P2 is in phase with the input pulse P1, and the rising edge of the output wide pulse 22 lags behind the rising edge of the input wide pulse 13 by a time T1 and the falling edge lags by a time T2.
The narrow pulses 11 and 12 are positive narrow pulses, and the time T1 is the maximum positive narrow pulse width that the high-frequency interference filter circuit can filter. T1 is the forward charging time. T1 is affected by the magnitude of the drive current flowing out of the current driver U11, the low level potential of the current driver U11, the magnitude of the capacitor C11, and the upper threshold voltage of the schmitt circuit F11. In general, adjusting the value of T1 can be done by varying the magnitude of the outgoing drive current of current driver U11 and the magnitude of capacitor C11.
The narrow pulses 19 and 20 are negative narrow pulses, and the time T2 is the maximum negative narrow pulse width that the high-frequency interference filter circuit can filter. T2 is the reverse charging time. T2 is affected by the magnitude of the drive current flowing out of the current driver U21, the low level potential of the current driver U21, the magnitude of the capacitor C21, and the upper threshold voltage of the schmitt circuit F21. In general, adjusting the value of T2 can be done by varying the magnitude of the outgoing drive current of current driver U21 and the magnitude of capacitor C21.
In fig. 1, one end of the capacitor C11 connected to the common ground may be connected to the power supply terminals of the schmitt circuit F11 and the schmitt circuit F21; similarly, the end of the capacitor C21 connected to the common ground may be connected to the power supply terminals of the schmitt circuit F11 and the schmitt circuit F21, either alone or together with the capacitor C11.
In fig. 1, the schmitt circuit F11 and the schmitt circuit F21 may also simultaneously or individually select an inverted schmitt circuit, and the inputs D1 and D2 and the output Y of the data selector T11 may also simultaneously or individually have an inverted correlation. When the schmitt circuit F11 and the schmitt circuit F21 simultaneously or individually select the inverse schmitt circuit, and the inputs D1 and D2 and the output Y of the data selector T11 simultaneously or individually have the inverse phase relationship, the following conditions need to be satisfied, that is: when the Y output by the data selector T11 is in-phase relation with the input signal of the Schmitt circuit F11 forward charging and discharging circuit, the Y output by the data selector T11 is in anti-correlation with the input signal of the Schmitt circuit F21; at this time, the output of the Y low-level control selection schmitt circuit F11 is supplied to the output terminal of the data selector T11, and the output of the Y high-level control selection schmitt circuit F21 is supplied to the output terminal of the data selector T11. When the Y output by the data selector T11 is in an inverse correlation with the input signal of the Schmitt circuit F11, the Y output by the data selector T11 is in an in-phase relationship with the input signal of the Schmitt circuit F21; at this time, the output of the Y low-level control selection schmitt circuit F21 is supplied to the output terminal of the data selector T11, and the output of the Y high-level control selection schmitt circuit F11 is supplied to the output terminal of the data selector T11.
Fig. 3 shows a forward current driver and a reverse current driver circuit of embodiment 1. The open-drain output in-phase driver F12 and the resistor R11 form a forward current driver. When P1 is low, the in-phase driver F12 outputs a1 that is low; when P1 is high, the in-phase driver F12 is an open-drain output, and power + VCC flows a driving current through the resistor R11.
The open-drain output inverting driver F22 and the resistor R21 form an inverting current driver. When P1 is high, the output a2 of inverting driver F22 is low; when P1 is low, inverting driver F22 is an open-drain output, and power + VCC flows the driving current through resistor R21.
The non-inverting driver F12 and the inverting driver F22 can be selected from various open collector and open drain integrated circuits.
Fig. 4 shows a forward current driver and a reverse current driver embodiment 2 circuit. The triode V21, the resistor R22 and the resistor R23 form a reverse current driver, when the P1 is at a high level, the triode V21 is in saturated conduction, and the output A2 of the reverse current driver is at a low level; when P1 is low, transistor V21 is turned off, and power + VCC draws driving current through resistor R22.
A forward current driver is composed of the triode V11, the triode V12, the resistor R12, the resistor R13 and the resistor R14, when the P1 is at a low level, the triode V12 is cut off, the triode V11 is in saturated conduction, and the output A1 of the forward current driver is at a low level; when P1 is at a high level, transistor V12 is in saturation conduction, transistor V11 is turned off, and power + VCC flows out a driving current through resistor R12. The inverting circuit formed by the transistor V12 and the resistor R14 in fig. 4 can be replaced by other inverters.
In fig. 4, the forward current driver and the reverse current driver do not provide a constant magnitude drive current for the outgoing drive current.
Fig. 5 shows a forward current driver and a reverse current driver embodiment 3 circuit. The triode V25, the triode V26, the voltage regulator tube D25, the resistor R25 and the resistor R26 form a reverse current driver, wherein the triode V26, the voltage regulator tube D25 and the resistor R25 form a reverse constant current circuit. When the P1 is at a high level, the triode V25 is in saturation conduction, and the reverse current driver output a2 is at a low level; when P1 is low, transistor V25 is turned off, and power supply + VCC draws a constant current drive current through transistor V26.
The triode V15, the triode V16, the triode V17, the voltage regulator tube D15, the resistor R15, the resistor R16 and the resistor R17 form a forward current driver, wherein the triode V16, the voltage regulator tube D15 and the resistor R15 form a forward constant current circuit. When the P1 is at a low level, the transistor V17 is turned off, the transistor V15 is turned on in saturation, and the forward current driver output a1 is at a low level; when the P1 is at a high level, the transistor V17 is in saturation conduction, the transistor V15 is cut off, and the power supply + VCC flows out a constant current driving current through the transistor V16. The inverting circuit formed by the transistor V17 and the resistor R17 in fig. 5 can be replaced by other inverters.
The forward anti-interference Schmitt circuit and the reverse anti-interference Schmitt circuit are both Schmitt circuits, and the input signal is voltage on a capacitor, so that the Schmitt circuit is required to have high input impedance characteristic. The schmitt circuit can select CMOS schmitt inverters CD40106, 74HC14 with high input impedance characteristics, or select CMOS schmitt nand gates CD4093, 74HC24 with high input impedance characteristics. The upper threshold voltage of a CMOS schmitt inverter or CMOS schmitt nand gate is a fixed value associated with the device. A Schmitt inverter or a Schmitt NAND gate is used for forming the same-phase Schmitt circuit, and a stage of inverter is required to be added behind the Schmitt inverter or the Schmitt NAND gate.
The Schmitt circuit can be formed by an operational amplifier, and the upper limit threshold voltage and the lower limit threshold voltage can be flexibly changed by forming the Schmitt circuit by the operational amplifier. Similarly, when the schmitt circuit is configured by using an operational amplifier, it is necessary to use a structure and a circuit having high input impedance characteristics.
The data selector may be an alternative data selector formed by devices such as 74HC151, 74HC152, 74HC153, CD4512, and CD4539, or may be a gate circuit.
Claims (8)
1. A high frequency interference filter circuit, comprising:
the device comprises a forward charge-discharge circuit, a reverse charge-discharge circuit and a data selector;
the input pulse of the high-frequency interference filtering circuit is input from an input pulse end, and the output pulse is output from an output pulse end;
the input ends of the forward charge-discharge circuit and the reverse charge-discharge circuit are connected to the input pulse end;
the data selector is an alternative data selector; two data input ends of the data selector are respectively connected to the output ends of the forward charge-discharge circuit and the reverse charge-discharge circuit;
the data output end of the data selector is an output pulse end; the data selector performs data selection control by the output pulse;
the forward charge-discharge circuit comprises a forward current driver, a forward anti-interference capacitor and a forward anti-interference Schmitt circuit; the input end of the forward current driver is the input end of a forward charging and discharging circuit, and the output of the forward current driver is connected to the input end of a forward anti-interference Schmitt circuit; one end of the forward anti-interference capacitor is connected to the input end of the forward anti-interference Schmitt circuit, and the other end of the forward anti-interference capacitor is connected to the public ground of the high-frequency interference filter circuit or a power supply of the forward anti-interference Schmitt circuit;
the reverse charging and discharging circuit comprises a reverse current driver, a reverse anti-interference capacitor and a reverse anti-interference Schmitt circuit; the input end of the reverse current driver is the input end of the reverse charge-discharge circuit, and the output end of the reverse current driver is connected to the input end of the reverse anti-interference Schmitt circuit; one end of the reverse anti-interference capacitor is connected to the input end of the reverse anti-interference Schmitt circuit, and the other end of the reverse anti-interference capacitor is connected to the public ground of the high-frequency interference filter circuit or a power supply of the reverse anti-interference Schmitt circuit;
the output end of the forward anti-interference Schmitt circuit is the output end of the forward charging and discharging circuit, and the output end of the reverse anti-interference Schmitt circuit is the output end of the reverse charging and discharging circuit.
2. The high frequency interference filter circuit according to claim 1, wherein: when the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs driving current; when the input of the forward current driver is at a low level, the output end is driven by voltage and outputs a low level; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs driving current; when the input of the reverse current driver is at a high level, the output end is driven by voltage and outputs a low level.
3. The high frequency interference filter circuit according to claim 2, wherein: when the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs constant current driving current; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs constant current driving current.
4. The high frequency interference filter circuit according to claim 1, wherein: when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in the same phase relation, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation system; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship.
5. The high frequency interference filter circuit according to claim 4, wherein: the specific method that the data selector carries out data selection control by the output pulse is that when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an in-phase relation and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation relation, the low-level control data selector of the output pulse selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship, the low-level control data selector of the output pulse selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector.
6. The high frequency interference filter circuit according to any one of claims 1 to 4, wherein: the positive narrow pulse width that can filter is controlled through changing the positive charge time, and the negative narrow pulse width that can filter is controlled through changing the reverse charge time.
7. The high frequency interference filter circuit according to claim 6, wherein: the forward charging time is controlled by changing the magnitude of the outflow driving current of the forward current driver or the magnitude of the forward anti-interference capacitor; the reverse charging time is controlled by changing the size of the outflow driving current of the reverse current driver or the size of the reverse anti-interference capacitor.
8. The high frequency interference filter circuit according to claim 6, wherein: the forward anti-interference Schmitt circuit and the reverse anti-interference Schmitt circuit both have high input impedance characteristics.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353504A (en) * | 2000-11-10 | 2002-06-12 | 日本电气株式会社 | Clock interruption detection circuit |
| CN101093983A (en) * | 2006-06-21 | 2007-12-26 | 夏普株式会社 | Comparing circuit and infrared receiver |
| CN103312130A (en) * | 2013-07-01 | 2013-09-18 | 湖南工业大学 | Bidirectional thyristor trigger circuit and method |
| CN104113326A (en) * | 2013-09-29 | 2014-10-22 | 西安电子科技大学 | Multiphase clock generation circuit with programmable function |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7944245B2 (en) * | 2008-12-18 | 2011-05-17 | Stmicroelectronics Pvt. Ltd. | Pulse filtering module circuit, system, and method |
| US9960620B2 (en) * | 2014-09-16 | 2018-05-01 | Navitas Semiconductor, Inc. | Bootstrap capacitor charging circuit for GaN devices |
-
2016
- 2016-06-15 CN CN201610421360.8A patent/CN106067788B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353504A (en) * | 2000-11-10 | 2002-06-12 | 日本电气株式会社 | Clock interruption detection circuit |
| CN101093983A (en) * | 2006-06-21 | 2007-12-26 | 夏普株式会社 | Comparing circuit and infrared receiver |
| CN103312130A (en) * | 2013-07-01 | 2013-09-18 | 湖南工业大学 | Bidirectional thyristor trigger circuit and method |
| CN104113326A (en) * | 2013-09-29 | 2014-10-22 | 西安电子科技大学 | Multiphase clock generation circuit with programmable function |
Non-Patent Citations (2)
| Title |
|---|
| "Evaluation on State of Charge Estimation of Batteries With Adaptive Extended Kalman Filter by Experiment Approach";Rui Xiong等;《IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY》;20130131;第62卷(第1期);108-117 * |
| "一种模/数混合型FIR噪声滤波器设计";易鸿;《现代电子技术》;20110915;第34卷(第18期);165-169 * |
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| CN106067788A (en) | 2016-11-02 |
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Effective date of registration: 20230118 Address after: 518000 201, No. 52, Xinyuan Industrial Zone, Guxing Community, Xixiang Street, Bao'an District, Shenzhen, Guangdong Province Patentee after: Shenzhen Sanzhou Electronics Co.,Ltd. Address before: 230000 Room 203, building 2, phase I, e-commerce Park, Jinggang Road, Shushan Economic Development Zone, Hefei City, Anhui Province Patentee before: Hefei Jiuzhou Longteng scientific and technological achievement transformation Co.,Ltd. Effective date of registration: 20230118 Address after: 230000 Room 203, building 2, phase I, e-commerce Park, Jinggang Road, Shushan Economic Development Zone, Hefei City, Anhui Province Patentee after: Hefei Jiuzhou Longteng scientific and technological achievement transformation Co.,Ltd. Address before: 412007 Hunan University of Technology Taishan 88 West Road, Hunan University of Technology, Hunan Institute of industry, education and research Patentee before: HUNAN University OF TECHNOLOGY |