CN106066837B - A kind of BISS-C agreement general purpose controller based on FPGA - Google Patents
A kind of BISS-C agreement general purpose controller based on FPGA Download PDFInfo
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- CN106066837B CN106066837B CN201610364762.9A CN201610364762A CN106066837B CN 106066837 B CN106066837 B CN 106066837B CN 201610364762 A CN201610364762 A CN 201610364762A CN 106066837 B CN106066837 B CN 106066837B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention discloses a kind of BISS-C protocol interface controller based on FPGA, it include: frame receiver/transmitter, register file, the First Input First Output SCDA_FIFO memory of storage control, monocycle actuator data, monocycle sensing data First Input First Output SCDS_FIFO memory, the storage control includes external channel information read-only memory NDT_ROM interface, external channel information read-only memory NDT_ROM is connected, the NDT_ROM stores multiple multiple channel description informations from equipment.
Description
[technical field]
The present invention relates to the controller fields for supporting BISS-C agreement.
[background technique]
For a long time, encoder manufacturers transmit location information by analog signal or simple digital increment signal interface.With
The passage of time and the development of encoder techniques allow encoder to generate high-resolution position with new processing method and high integration
Data are set, and increases advanced function and for example orders, register communication etc..Therefore need to realize a new interface,
Band can be suitble to the characteristic of this high-end devices.SSI is an out-of-date industrial standard, and the speed and function for being unable to satisfy manufacturer are wanted
It asks.A few manufacturers are proposed the agreement of oneself, but closure is very strong, and there are incompatibility for different brands.2002
IC-Haus releases BiSS open interface.BiSS purpose is available to the two-way high-speed traffic standard of sensor and actuator, and
Retain and SSI (Synchronous Serial Interface) standard interface hardware compatibility.In the time more than 10 years
BiSS is developed using continuous, leading such as Baruch husband (Balluff) presently more than 300 authorisation device manufacturers, including industry,
Fort alliance (Baumer), Danaher (Danaher Motion), Ku Baile (K ü bler), Heng Shile (Hengstler),PEPPERL FUCHS (Pepperl+Fuchs), Reinshaw (Renishaw), Schneider Electric Devices (Schneider
Electric), pacify river motor (Yaskawa), Yu Heng optics (Yuheng Optics) and it is other use BiSS interface.
BiSS interface is dedicated real time sensor and actuator interface, have open (Open source), connection it is simple,
Bandwidth is high, (one-way bus and bidirectional bus can be used) flexible in application, Support Line delay compensation and farthest 100m Distance Transmission,
It supports security function, networking function, support electronic device description.There are mainly three types of implementations for BISS-C controller at present: 1.
Implementation based on dedicated IC chip, iC-Haus provide iC-MB3 and iC-MB4 integrated circuit, comprising all
This chip of BiSS protocol function passes through the serial or parallel Interface Controller of single-chip microcontroller；The semiconductor companies such as TI are also by BISS controller
It is integrated into its DSP or singlechip chip.2. the implementation based on FPGA, iC-Haus also provides VHDL IP kernel, includes
BiSS protocol function can be simply integrated in FPGA the or CPLD hardware of manufacturer.Also there are many engineers to be based on both at home and abroad
FPGA realizes simple BICC controller.3. realizing that BISS is assisted by way of software based on the realization of single-chip microcontroller GPIO
View.
But the problem that the existing generally existing integrated level of controller implementation is not high.For example, iC-MB3 is only supported
3 from equipment；And iC-MB4 only support 8 from equipment.The IP kernel and this two chip that iC-Haus is provided are supported from equipment
Ability is suitable.And if the scheme based on single-chip microcontroller GPIO to support largely to need to pay from equipment costly at
This.In some special occasions (such as controller of tens mechanical arms of control, multiple channel PLC etc.), these BISS-C
Bus control unit is no longer satisfied extension largely from the requirement of node.Why existing controller only supports a small amount of slave section
Point, be since BISS-C equipment is few in the market in early days, to support it is largely unobvious from the controller demand of node.However, by
In the protrusion technical advantage of BISS-C agreement, more and more manufacturers is attracted to support BISS-C agreement, more and more equipment
Support BISS-C agreement, therefore, support largely will have bigger demand from the BISS-C controller of equipment.
[summary of the invention]
The invention solves the problems that the slave number of devices of existing BISS-C controller support is limited.To reach this purpose,
The BISS-C controller based on FPGA is devised, 128 can be could support up from equipment.In addition, it is also proposed that Yi Zhongjian
The method of incorrect channel parameters ROM, it is ensured that the safety that the BISS-C controller as main equipment is connect with from equipment.
BISS-C protocol interface controller proposed by the present invention, comprising: frame receiver/transmitter, register file, storage control, list
The First Input First Output SCDA_FIFO memory of period actuator data, monocycle sensing data First Input First Output SCDS_
FIFO memory, storage control,
Wherein, register file has the register access interface for outside access, and the register file and the frame are received and dispatched
Device, storage control connection store the frame receiver/transmitter, the state of storage control and control information；
The storage control includes executing data with external channel information read-only memory NDT_ROM interface, monocycle
Random access memory SCDA_RAM interface, monocycle sensing data random access memory SCDS_RAM interface, respectively with external channel
Information read-only memory NDT_ROM, monocycle actuator data random access memory SCDA_RAM and monocycle sensing data with
Machine memory SCDS_RAM connection, wherein the NDT_ROM stores multiple multiple channel description informations from equipment, described
SCDA_RAM stores the actuator data that will be transmitted for storing all channels in next frame, and the SCDS_RAM storage is all
The sensing data that channel is acquired in a frame end of transmission；
The storage control is connect with the SCDA_FIFO memory, and the SCDA_FIFO memory and the frame are received
Device connection is sent out, the storage control stores the actuator data obtained from SCDA_RAM interface by the SCDA_FIFO
Device sends frame receiver/transmitter to, and received sensing data is sent to by the SCDS_FIFO memory and deposited by the frame receiver/transmitter
Controller is stored up, and the SCDS_RAM is sent to by SCDS_RAM interface by storage control.
Preferably, the protocol interface controller is realized with FPGA.
Preferably, the frame receiver/transmitter further include: wire delay compensating unit, frame transmission unit and frame receiving unit.
Preferably, the storage control further include: channel parameters resolution unit, channel parameters pushup storage,
It sends data stream element and receives data stream element.
Preferably, further include that green indicating lamp and a safety detection enable pin, counted when needing to detect in the NDT_ROM
According to safety when, safety detection is enabled into pin and connects high level, so that the protocol interface controller enters safety detection mould
Formula specifically further includes following step:
(1) channel parameters resolution unit reads the security parameter of designated position storage in NDT_ROM；
(2) if the security parameter is not present, the working condition for reading NDT_ROM is exited, and send out by green indicating lamp
Alarm signal out, prompting the NDT_ROM not is safe memory；
(3) it if successfully reading the security parameter, is flashed by green indicating lamp, frequency and the security parameter phase of flashing
Deng；Judge whether lamp flicker frequency meets user-defined frequency；If met, safety detection is enabled into pin and accesses low electricity
It is flat, security parameter is no longer read, safety detection mode is exited, continues to read other data in NDT_ROM；If do not met,
Safety detection enables pin and continues to access high level, keeps safety detection mode, repeats step (1)-(3), continues to read safety
Parameter and detection function.Using safety detection mode, can help user identify the channel parameters in NDT_ROM whether with conduct
The protocol controller of main equipment and match with as from the sensor of equipment.
Preferably, the NDT_ROM is external ROM memory, and the external ROM memory storage is multiple from equipment
Multiple channel description informations, each channel description information occupies 8 bytes, including channel data payload length, CRC multinomial
The first address of formula, CRC initial value, actuator data in the SCDA_RAM, sensing data is on the first ground of the SCDA_RAM
Location.
Preferably, the multiple channel is up to 128 channels.
Preferably, the NDT_ROM interface, SCDA_RAM interface and SCDS_RAM interface are integrated in the Interface Controller
In device, and realized with FPGA.
Preferably, the register file is by one group of register group at each register stores 8bit information, described each to post
Storage is used to finely control the operating mode of entire controller or the inner workings of the reflection interface controller.
Preferably, the data bits of the SCDA_FIFO memory is 1bit, and depth is to be sent for storing up to 32
Data bit stream；The data bits of the SCDS_FIFO memory is 1bit, and depth is up to 32, for storing the biography received
Sensor data code flow.
Preferably, the storage control is started to work after every frame starts, and until a frame is transmitted, the channel is joined
Number resolution unit is responsible for reading the information in each channel from the NDT_ROM sequence, and the channel parameters first in, first out is arrived in storage
In memory, the information is used to instruct to send the actuator data that data stream element reads channel from the SCDA_RAM, and
It calculates and generates CRC and be pressed into the SCDA_FIFO memory, the reception data stream element is from channel parameters pushup storage
The parameter information in a channel is read, and receives the sensing data in the channel from the SCDS_FIFO memory, carries out CRC
It verifies and stores in the SCDS_RAM.
Preferably, the frame receiver/transmitter can work in ad hoc mode or mode bus, and the frame receiver/transmitter includes following
External interface: main device data output interface BISS_MO, main device clock output interface BISS_MA connect from device data input
Mouth BISS_SL.
Preferably, under the ad hoc mode, the BISS_MO drives 0 level of output always.
Preferably, under the mode bus, actuator data are exported from BISS_MO to from equipment.
Preferably, under the ad hoc mode or mode bus, the BISS_MA is used as bus clock signal,
The BISS_SL is used as sensing data input signal.
Preferably, the wire delay compensating module is used for detection line transmission delay, compensates FPGA timing, and to described
BISS_SL signal synchronizes and samples registration process, it is ensured that internal sample to the BISS_SL signal do not have metastable state and
The error value that hopping edge nearby samples.
Preferably, the frame transmission unit is responsible for sending actuator data, when the frame receiving unit is responsible for generating bus
Clock and reception sensing data.
Preferably, the protocol interface controller is realized in the form of IP kernel, is configured and is supported by register access interface
Number of channels, frame period, bus clock cycle information.
[Detailed description of the invention]
Described herein the drawings are intended to provide a further understanding of the invention, constitutes part of this application, but
It does not constitute improper limitations of the present invention, in the accompanying drawings:
Fig. 1 is the system construction drawing with BISS-C protocol interface controller proposed by the present invention；
Fig. 2 is a point-to-point connection mode of the invention；
Fig. 3 is a bus connection mode of the invention.
[specific embodiment]
Come that the present invention will be described in detail below in conjunction with attached drawing and specific embodiment, illustrative examples therein and says
It is bright to be only used to explain the present invention, but it is not intended as inappropriate limitation of the present invention.
Controller whole design of the present invention is compact-sized, powerful, flexible in application.Can be convenient be integrated into xlinx,
It in the FPGA device of the mainstreams such as Altera, Lattice, can both be directly integrated into verilog circuit, can also further seal
The peripheral hardware IP kernel for dressing up processor uses.The sheet realized with Lattice FPGA (model are as follows: LCMXO2-1200HC-4TG100C)
The BISS-C protocol controller of invention, wherein the occupation rate of the register resources of FPGA is the utilization rate of 28%, SLICE resource
Utilization rate for 58%, LUT4 resource is 57%, meets design requirement.
It is system architecture diagram of the invention, including frame receiver/transmitter, register file, storage control, monocycle referring to Fig. 1
The First Input First Output SCDA_FIFO memory of actuator data, monocycle sensing data First Input First Output SCDS_FIFO
Memory, storage control, wherein register file have for outside access register access interface, the register file with
The frame receiver/transmitter, storage control connection store the frame receiver/transmitter, the state of storage control and control information；It is described
Storage control includes executing data random access memory with external channel information read-only memory NDT_ROM interface, monocycle
SCDA_RAM interface, monocycle sensing data random access memory SCDS_RAM interface, respectively with external channel information is read-only deposits
Reservoir NDT_ROM, monocycle actuator data random access memory SCDA_RAM and monocycle sensing data random access memory
SCDS_RAM connection, wherein the NDT_ROM stores multiple multiple channel description informations from equipment, and the SCDA_RAM is deposited
The actuator data that will be transmitted for storing all channels in next frame are put, the SCDS_RAM stores all channels in a frame
The sensing data acquired when the end of transmission；The storage control is connect with the SCDA_FIFO memory, the SCDA_
FIFO memory is connect with the frame receiver/transmitter, and the storage control leads to the actuator data obtained from SCDA_RAM interface
It crosses the SCDA_FIFO memory and sends frame receiver/transmitter to, the frame receiver/transmitter will be received by the SCDS_FIFO memory
Sensing data send storage control to, and the SCDS_ is sent to by SCDS_RAM interface by storage control
RAM。
Its described frame receiver/transmitter includes: wire delay compensating unit, frame transmission unit and frame receiving unit.The storage control
Device includes: channel parameters resolution unit, channel parameters pushup storage, sends data stream element and receive data flow list
Member.
The NDT_ROM can an external ROM memory, external ROM memory can store multiple from the multiple of equipment
Channel description information, each channel description information occupy 8 bytes, including channel data payload length, at the beginning of CRC multinomial, CRC
Value, first address of the actuator data in the SCDA_RAM, first address of the sensing data in the SCDA_RAM.Port number
Amount can be up to 128 by user setting.
In practical applications, it is often necessary to it replaces different from equipment, thus needs to configure different channel parameters, these
Channel parameters are pre-stored in NDT_ROM, but with more and more from equipment, adapt to the different NDT_ROM's from equipment
Version is also more and more, and it is required that this, which just will appear bad which NDT_ROM version of judgement,.Although can be by storing
The surface of device labelled mode is distinguished, but often since label is lost, or the label that do not timely update, so that mark
The case where information in the information and NDT_ROM of label mismatches, and still will appear the NDT_ROM version of selection mistake generation.For solution
Certainly above-mentioned technical problem, with present invention also adds the functions of the safety detection mode of protocol controller, by NDT_ROM
The NDT_ROM that security parameter is detected and shown to help user's identification required.On the BISS-C protocol interface controller
One green indicating lamp is set and a safety detection enables pin, when needing to detect the safety of data in the NDT_ROM,
Safety detection can be enabled pin and connect high level, so that BISS-C protocol interface controller enters safety detection mode, it is specific to wrap
Include following step:
(1) channel parameters resolution unit reads the security parameter of designated position storage in NDT_ROM；
(2) if the security parameter is not present, the working condition for reading NDT_ROM is exited, and send out by green indicating lamp
Alarm signal out, prompting the NDT_ROM not is safe memory；
(3) it if successfully reading the security parameter, is flashed by green indicating lamp, frequency and the security parameter phase of flashing
Deng；Judge whether lamp flicker frequency meets user-defined frequency；If met, safety detection is enabled into pin and accesses low electricity
It is flat, safety detection mode is exited, no longer reading security parameter, and continue to read other data in NDT_ROM；If be not inconsistent
It closes, safety detection enables pin and continues to access high level, keeps safety detection mode, repeats step (1)-(3), continues to read peace
Population parameter and execution detection function.
The register file is by one group of register group at each register stores 8bit information, and each register is used
In the inner workings of the operating mode or the reflection interface controller that finely control entire controller.BISS-C is assisted
It, being capable of control interface control by the numerical value being arranged and read in register when view interface controller is linked into computer system
The operating mode of device processed, and understand the state of interface controller.
The data bits of the SCDA_FIFO memory is 1bit, and depth is up to 32, for storing data bit to be sent
Stream；The data bits of the SCDS_FIFO memory is 1bit, and depth is up to 32, for storing the sensing data received
Code stream.The memory uses the buffering method of the 1bit of first in, first out, it can be ensured that the input/output of data is not in congestion.
Storage control is started to work after every frame starts, and until a frame is transmitted, channel parameters resolution unit is responsible for
The information that each channel is read from the NDT_ROM sequence, stores into the channel parameters pushup storage, channel letter
Breath calculates generation cyclic redundancy for instructing to send data stream element the actuator data from SCDA_RAM reading channel
Check code CRC is pressed into the SCDA_FIFO memory, and the reception data stream element is read from channel parameters pushup storage
The parameter information in a channel is taken, and receives the sensing data in the channel from the SCDS_FIFO memory, carries out the school CRC
It tests and stores in the SCDS_RAM.
The frame receiver/transmitter includes main device data output interface BISS_MO, main device clock output interface BISS_MA,
It from device data input interface BISS_SL, can work in ad hoc mode or mode bus, wherein the BISS_MA all conducts
Bus clock signal, the BISS_SL are used as sensing data input signal.Under ad hoc mode, BISS_MO drives always
Export 0 level, under the mode bus, actuator data are exported from BISS_MO to from equipment.
The wire delay compensating module is used for detection line transmission delay, compensates FPGA timing, and to the BISS_SL signal
Synchronize and sample registration process, it is ensured that internal sample to the BISS_SL signal do not have near metastable state and hopping edge
The error value sampled.
The frame transmission unit is responsible for sending actuator data, and the frame receiving unit is responsible for generating bus clock and reception
Sensing data.
The protocol interface controller can also be realized in the form of IP kernel, be supported by the configuration of register access interface logical
Road quantity, frame period, bus clock cycle information.
The protocol interface controller can complete BISS-C agreement frame data transmission, can also cooperate microcontroller or
Other programmable logic realize multiframe agreement, support point-to-point transmission function, and supporting bus networking transfer function supports sensor
The transmission at same frame of data and actuator data, Support Line delay compensation support the CRC check of sensing data and execute data
CRC is generated, support configurable frame period and, support configurable network structure, support the configurable BISS clock cycle, prop up
Hold configurable waiting time parameter.Register access interface is used to control the work shape inside internal operating mode and access
State, such as configuration frame period, configuration BISS clock cycle, the point-to-point operating mode of configuration or bus operation mode, configuration are from setting
Standby number of channels, reset controller start or stop frame loop cycle etc..By register access interface, the control can be made
Device is more flexible and general.The external ROM of NDT_ROM interface stores lacquerware, can realize inside FPGA, which stores net
Multiple multiple channel description informations (at least one channel, up to 128 channels) from equipment on network.Each channel information occupies
8 bytes, including channel data payload length, CRC multinomial, CRC initial value execute data in the first address of SCDA_RAM, pass
Data are felt in information such as the first address of SCDA_RAM.Channel number is recorded in some register of register file.SCDA_RAM
Interface connects SCDA_RAM, can realize in FPGA.SCDA_RAM is for storing what all channels will be transmitted in next frame
Actuator data.Data are stored in advance before can be considered by microcontroller or fpga logic transmitting every frame in SCDA_RAM.
The storage address in each channel should be consistent with the first address of corresponding channel in NDT_ROM.For point-to-point application or do not have
The application of actuator data can not realize SCDA_RAM, and the data/address bus of SCDA_RAM is simply only all connected to 0
Level.SCDA_RAM maximum can be configured to 2Kbyte, calculates according to maximum 8 Byte in each channel, can accommodate 256
Channel, SCDS_RAM interface connect SCDS_RAM, can realize in FPGA.SCDS_RAM is for storing all channels in a frame
The sensing data acquired when the end of transmission.SCDA_RAM can be considered by microcontroller or FPGA in every frame end of transmission into
Row access and analysis.The storage address in each channel should be consistent with the first address of corresponding channel in NDT_ROM.SCDS_RAM is most
It can be configured to 2Kbyte greatly, calculated according to most 10 Byte (including up to 8Byte data, 2ByteCRC) in each channel, it can
Accommodate 204 channels.
Referring to fig. 2, by the BISS_MA interface of BISS-C interface controller (including MA+ and MA- both threads) and BISS_SL
Interface (including SL+ and SL- both threads) is connected on the corresponding interface line (such as SLO+, SLO-) of sensor.NDT_ROM interface can
To connect external ROM or 8 8bit register of 8 bytes, the information of storage sensor in external ROM.SCDA_RAM can be saved
Slightly, therefore, 0 is driven to the data bus interface perseverance of SCDA_RAM.SCDS_RAM can be configured according to the frame length of sensor
The RAM or register of most 10 bytes.
After the reset, wait 40ms, allow sensor enter correct bus state, then by register port configuration and
Sensor related frame period, total current order parameter, finally start frame periodic transfer.
After starting frame periodic transfer, BISS-C protocol interface controller periodically initiates bus timing, reads sensor
Sensing data carries out CRC check, and SCDA_RAM is written together with the CRC of local computing in the data of sensor together, then leads to
Extra pulse signal notifier processes logic or single-chip microcontroller handle sensing data.
Referring to Fig. 3, the MA (including MA+ and MA- both threads) of configuration association BISS-C interface controller, MO (including MO+ and
MO- both threads) it is connect with SL (including SL+ and SL- both threads) with second from the corresponding interface of equipment, second from the MA of equipment
(including MO+ and MO- both threads), SLO (including SLO+ and SLO- both threads) and SL (including SL+ and SL- both threads) and first
A to connect from equipment, first as end connect cyclization from the end SLO and SL of device.The bus mould constituted in this way
Formula may make BISS-C interface controller to connect multiple sensors.
Can not only there be sensing data channel from equipment, but also there can be execution data channel.NDT_ROM interface can connect most
The ROM of big 1KB (Byte) capacity, wherein sequentially storage first from equipment, second from equipment ..., N is from the institute of equipment
There is channel configuration information.In the case where being not carried out device data, SCDA_RAM be can be omitted；Otherwise, maximum 2KB is needed to configure
The SCDA_RAM of capacity.SCDS_RAM can be according to the RAM of network configuration maximum 2Kbyte capacity.
After the reset, first wait at least 40ms, allow it is all from equipment enter correct bus state, then pass through register
Port configures frame period, total current order parameter, finally starts frame periodic transfer.After starting frame periodic transfer, BISS-C control
Device periodically initiates bus timing.In each frame period, BISS controller first sends pulse signal notifier processes logic or external single
SCDA_RAM is written in actuator data by piece machine.After one configurable time, BISS controller is accessed from SCDA_RAM
Data, and start bus transfer timing.Controller data and sensing data are by simultaneous transmission.The sensing data received connects
CRC with its local computing is stored in SCDS RAM together.After the completion of bus transfer, BISS controller by pulse signal notice at
It manages logic or single-chip microcontroller handles sensing data.
Those of ordinary skill in the art will appreciate that computer journey can be used in all or part of the steps of above-described embodiment
Sequence process realizes that the computer program can be stored in a computer readable storage medium, the computer program exists
(such as system, unit, device) executes on corresponding hardware platform, when being executed, include the steps that embodiment of the method it
One or combinations thereof.Optionally, integrated circuit can be used also to realize in all or part of the steps of above-described embodiment, these steps
It can be fabricated to integrated circuit modules one by one respectively, or maked multiple modules or steps in them to single integrated
Circuit module is realized.Device/functional module/functional unit in above-described embodiment can be using general computing device come real
Existing, they can be concentrated on a single computing device, and can also be distributed over a network of multiple computing devices.It is above-mentioned
Device/functional module/functional unit in embodiment is realized in the form of software function module and is sold as independent product
Or it in use, can store in a computer readable storage medium.Computer-readable storage medium mentioned above
It can be read-only memory, disk or CD etc..
Claims (16)
1. a kind of BISS-C protocol interface controller, characterized by comprising: frame receiver/transmitter, register file, storage control, list
The First Input First Output SCDA_FIFO memory of period actuator data, monocycle sensing data First Input First Output SCDS_
FIFO memory, wherein register file has the register access interface for outside access, and the register file and the frame are received
Device, storage control connection are sent out, for storing the state and control information of the frame receiver/transmitter, storage control；
The storage control include external channel information read-only memory NDT_ROM interface, the monocycle execute data deposit at random
Reservoir SCDA_RAM interface, monocycle sensing data random access memory SCDS_RAM interface, these interfaces are logical with outside respectively
Road information read-only memory NDT_ROM, monocycle actuator data random access memory SCDA_RAM and monocycle sensing data
Random access memory SCDS_RAM connection, wherein the NDT_ROM stores multiple multiple channel description informations from equipment, described
SCDA_RAM stores the actuator data that will be transmitted for storing all channels in next frame, and the SCDS_RAM storage is all
The sensing data that channel is acquired in a frame end of transmission；
The storage control is connect with the SCDA_FIFO memory, the SCDA_FIFO memory and the frame receiver/transmitter
Connection, the storage control pass the actuator data obtained from SCDA_RAM interface by the SCDA_FIFO memory
Frame receiver/transmitter is given, the frame receiver/transmitter sends received sensing data to storage by the SCDS_FIFO memory
Controller, and the SCDS_RAM is sent to by SCDS_RAM interface by storage control；
It further, further include that a green indicating lamp and a safety detection enable pin, the storage control further include: channel
Parameter analysis of electrochemical unit, channel parameters pushup storage send data stream element and receive data stream element；When needing to detect
In the NDT_ROM when safety of data, the safety detection is enabled into pin and connects high level, so that the protocol interface control
Device processed enters safety detection mode, specifically include the following steps:
(1) channel parameters resolution unit reads the security parameter of specified location storage in NDT_ROM；
(2) if the security parameter is not present, the working condition for reading NDT_ROM is exited, and issue and report by green indicating lamp
Alert signal, prompting the NDT_ROM not is safe memory；
(3) it if successfully reading the security parameter, is flashed by green indicating lamp, the frequency of flashing is equal with security parameter；With
Family judges whether lamp flicker frequency meets user-defined frequency；If met, safety detection is enabled into pin access low level,
Safety detection mode is exited, no longer reading security parameter, continues to read other data in NDT_ROM；If do not met, safety
It detects enabled pin to continue to access high level, keeps safety detection mode, repeat step (1)-(3), continue to read security parameter
With execution detection function.
2. BISS-C protocol interface controller as described in claim 1, it is characterised in that the frame receiver/transmitter further include: line prolongs
Slow compensating unit, frame transmission unit and frame receiving unit.
3. BISS-C protocol interface controller as claimed in claim 2, which is characterized in that the protocol interface controller is used
FPGA is realized.
4. BISS-C protocol interface controller as claimed in claim 3, it is characterised in that the NDT_ROM is external ROM
Memory, the external ROM memory store multiple multiple channel description informations from equipment, and each channel description information accounts for
With 8 bytes, including channel data payload length, CRC multinomial, CRC initial value, actuator data are in the SCDA_RAM
First address, first address of the sensing data in the SCDA_RAM.
5. BISS-C protocol interface controller as claimed in claim 4, it is characterised in that the multiple channel is up to 128
Channel.
6. BISS-C protocol interface controller as claimed in claim 4, it is characterised in that the NDT_ROM interface, SCDA_
RAM Interface and SCDS_RAM interface are integrated in the interface controller, and are realized with FPGA.
7. such as the described in any item BISS-C protocol interface controllers of claim 5-6, it is characterised in that the register file by
One group of register group is at each register stores 8bit information, and each register is for finely controlling entire controller
The inner workings of operating mode or the reflection interface controller.
8. BISS-C protocol interface controller as claimed in claim 7, it is characterised in that the number of the SCDA_FIFO memory
It is 1bit according to digit, depth is up to 32, for storing data bit stream to be sent；The data bit of the SCDS_FIFO memory
Number is 1bit, and depth is up to 32, for storing the sensing data code stream received.
9. BISS-C protocol interface controller as claimed in claim 8, it is characterised in that the storage control is in every frame number
According to starting to work after beginning, until a frame data are transmitted, the channel parameters resolution unit is responsible for suitable from the NDT_ROM
Sequence reads the information in each channel, stores into the channel parameters pushup storage, and the information is sent for instructing
Data stream element reads the actuator data in channel from the SCDA_RAM, and calculates and generate cyclic redundancy check code CRC indentation
The SCDA_FIFO memory, the data stream element that receives is from one channel of channel parameters pushup storage reading
Parameter information, and receive from the SCDS_FIFO memory sensing data in the channel carries out CRC check and simultaneously stores to arrive institute
It states in SCDS_RAM.
10. BISS-C protocol interface controller as claimed in claim 9, it is characterised in that the frame receiver/transmitter can work in point
To dot pattern or mode bus, the frame receiver/transmitter includes following external interfaces: main device data output interface BISS_MO, main
Device clock output interface BISS_MA, from device data input interface BISS_SL.
11. BISS-C protocol interface controller as claimed in claim 10, it is characterised in that when in the ad hoc mode
Under, the BISS_MO drives 0 level of output always.
12. BISS-C protocol interface controller as claimed in claim 10, it is characterised in that under the mode bus,
Actuator data are exported from BISS_MO to from equipment.
13. the BISS-C protocol interface controller as described in claim 11 or 12, it is characterised in that the BISS_MA makees
For bus clock signal, the BISS_SL is used as sensing data input signal.
14. BISS-C protocol interface controller as claimed in claim 13, it is characterised in that the wire delay compensating unit is used
In detection line transmission delay, FPGA timing is compensated, and synchronizes and sample registration process to the BISS_SL signal, it is ensured that
Internal sample to the BISS_SL signal error value that does not have metastable state and hopping edge nearby to sample.
15. BISS-C protocol interface controller as claimed in claim 14, it is characterised in that the frame transmission unit is responsible for hair
Actuator data are sent, the frame receiving unit is responsible for generating bus clock and receives sensing data.
16. BISS-C protocol interface controller as claimed in claim 15, the protocol interface controller is in the form of IP kernel
It realizes, passes through the number of channels of register access interface configuration support, frame period, bus clock cycle information.
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| TWI708149B (en) * | 2018-11-28 | 2020-10-21 | 聚晶半導體股份有限公司 | Tranasmission interface module and signal transmission method |
| CN111162984B (en) * | 2019-12-27 | 2022-02-01 | 常州节卡智能装备有限公司 | Control method, device and communication system based on BISS-C |
| CN112947163B (en) * | 2021-02-01 | 2022-08-05 | 贵州航天林泉电机有限公司 | DSP-based BISS-C protocol sensor data analysis and extraction method |
| CN114116552B (en) * | 2021-10-20 | 2024-02-06 | 中国航空工业集团公司洛阳电光设备研究所 | Data acquisition and transmission device from multi-channel Biss-C data to universal serial port |
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