CN106059310B - Power reduction output circuit of power conversion device for high-voltage super capacitor - Google Patents
Power reduction output circuit of power conversion device for high-voltage super capacitor Download PDFInfo
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- CN106059310B CN106059310B CN201610491586.5A CN201610491586A CN106059310B CN 106059310 B CN106059310 B CN 106059310B CN 201610491586 A CN201610491586 A CN 201610491586A CN 106059310 B CN106059310 B CN 106059310B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
- H02M1/092—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the control signals being transmitted optically
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Abstract
The invention provides a power reduction output circuit of a power conversion device for a high-voltage super capacitor, which comprises an input voltage detection unit, a voltage comparison detection hysteresis unit, a current loop unit, a PWM (pulse width modulation) main control unit and an output current detection unit, wherein the input voltage detection unit is connected with the output current detection unit; the PWM main control unit and the input voltage detection unit receive direct current input voltage; the voltage comparison detection hysteresis unit transmits the output signal to the current loop unit in an isolation optocoupler switch mode; the circuit loop unit transmits the output signal to the PWM main control unit in a linear mode through the isolation optocoupler; the output current detection unit collects the output current of the output loop and inputs the output current to the current loop unit. Compared with the prior art, the power reduction output circuit for the power conversion device of the high-voltage super capacitor, provided by the invention, can realize control on output limit power when the input voltage is too low, effectively protect a main power switch device and a circuit on the low-voltage side of the power conversion device, and improve the safety and reliability of the power conversion device.
Description
Technical Field
The invention relates to the technical field of control over a power conversion device of a vehicle-mounted high-voltage super capacitor, in particular to a power reduction output circuit of the power conversion device for the high-voltage super capacitor.
Background
The super capacitor is widely applied due to the characteristics of short charging time, long service life, good temperature characteristic, energy conservation, environmental protection and the like, for example, the super capacitor is used as a vehicle starting power supply, the starting efficiency and the reliability are higher than those of a traditional storage battery, and the super capacitor can be used as a vehicle traction energy source to produce an electric automobile, replace a traditional internal combustion engine and transform the existing trolley bus. The vehicle-mounted high-voltage super capacitor can provide high-voltage direct current, and a power conversion device in the vehicle-mounted high-voltage super capacitor can convert low voltage into high voltage. However, when the input voltage of the power converter is lower than the low-voltage threshold, if the high-voltage output power of the power converter is kept unchanged, the operating current of the main power switch tube at the low-voltage input end of the power converter is increased, and further, if the input voltage is continuously reduced, the main power switch tube at the low-voltage input end of the power converter is finally damaged due to long-time overcurrent heating. For example, the power conversion device is used for realizing the conversion from low voltage 28V to high voltage 270V, the low voltage input threshold of the power conversion device is 20V, and the low voltage input voltage of the vehicle ranges from 22V to 30V, when the low voltage input voltage of the vehicle is lower than 20V, if the high voltage output power of the power conversion device is kept unchanged, the operating current of the main power switch tube at the low voltage input end of the power conversion device is increased, and further if the input voltage is continuously reduced, the main power switch tube at the low voltage input end of the power conversion device is finally damaged due to long-time overcurrent heating.
Disclosure of Invention
In order to realize overcurrent protection on a main power device and voltage of a low-voltage input end of a power conversion device when the low-voltage input voltage of a vehicle is lower than a low-voltage input threshold value of the power conversion device and improve the safety and reliability of the power conversion device, the invention provides a power reduction output circuit of the power conversion device for a high-voltage super capacitor.
The technical scheme of the invention is as follows:
the input side of the power conversion device comprises a direct current input end and a main power switch tube, the output side comprises a transformer and an output loop, the main power switch tube, the transformer and the output loop are sequentially connected, and the power reduction output circuit comprises an input voltage detection unit, a voltage comparison detection hysteresis unit, a current loop unit, a PWM (pulse width modulation) main control unit and an output current detection unit;
the input end of the input voltage detection unit is connected with the direct current input end, and the output end of the input voltage detection unit, the voltage comparison detection hysteresis unit, the current loop unit and the PWM main control unit are sequentially connected;
the other input end of the PWM main control unit is connected with the direct current input end, and the output end of the PWM main control unit is connected with the main power switch tube;
the input end of the output current detection unit is connected with the output loop, and the output end of the output current detection unit is connected with the current loop unit.
The invention further provides a preferable technical scheme that:
the input voltage detection unit is used for collecting the direct current input voltage of the direct current input end and sending the direct current input voltage to the comparison detection hysteresis unit;
the output current detection unit is used for collecting the output current of the output loop and sending the output current to the current loop unit;
the voltage comparison detection hysteresis unit compares the direct current input voltage with a voltage threshold value and outputs a comparison point control signal to the current loop unit according to a comparison result;
the current loop unit outputs a COMP signal to the PWM main control unit according to the comparison point control signal and the output signal of the output current detection unit;
the PWM main control unit judges whether to adjust the duty ratio of PWM modulation pulse according to the COMP signal and outputs PWM modulation pulse to a main power switch tube; the main power switch tube changes rated output current under the control of the PWM modulation pulse, and further changes output power of an output side and input power of an input side in the power supply conversion device.
The invention further provides a preferable technical scheme that: the voltage comparison detection hysteresis unit comprises a signal comparison circuit, a diode and a first optical coupling isolation circuit which are connected in sequence;
the signal comparison circuit comprises a first operational amplifier, the inverting input end of the first operational amplifier is connected with the input voltage detection unit, and the first operational amplifier receives the direct current input voltage of the direct current input end; the non-inverting input end of the diode receives a voltage threshold signal, and the output end of the diode is connected with the anode of the diode;
and the primary side of the first optical coupling isolation circuit is connected with the cathode of the diode, and the secondary side of the first optical coupling isolation circuit is connected with the current loop unit.
The invention further provides a preferable technical scheme that: the voltage comparison detection hysteresis unit compares the direct current input voltage with a voltage threshold, if the direct current input voltage is smaller than or equal to the voltage threshold, the first operational amplifier outputs a high level, the diode and the primary side of the first optical coupling isolation circuit are sequentially conducted, and the secondary side of the first optical coupling isolation circuit outputs a comparison point control signal to the current loop unit.
The invention further provides a preferable technical scheme that: the current loop unit comprises a reference signal end, a current feedback signal end, a COMP signal end, a voltage stabilizing circuit, a voltage dividing circuit, a filter circuit and a PI adjusting circuit; the PI regulating circuit comprises a second operational amplifier;
the voltage stabilizing circuit, the voltage dividing circuit and the filter circuit are sequentially connected, one branch of the filter circuit is connected with the non-inverting input end of the second operational amplifier, and the other branch of the filter circuit is connected with the inverting input end of the second operational amplifier;
the reference signal end is arranged between the voltage stabilizing circuit and the voltage dividing circuit and used for receiving a reference voltage signal;
the current feedback signal end is connected with the in-phase input end and receives an output signal of the output current detection loop;
the COMP signal end is connected with the output end of the operational amplifier through a diode, and the cathode of the diode is connected with the output end;
and the secondary side of a first optical coupling isolation circuit in the voltage comparison detection hysteresis unit is connected between the filter circuit and the reverse input end.
The invention further provides a preferable technical scheme that:
the voltage stabilizing circuit comprises a voltage stabilizing device and a first capacitor which are connected in parallel, and one end of the voltage stabilizing device is grounded;
the voltage division circuit comprises a first resistor, a second resistor and a third resistor which are connected in series; two ends of a series branch consisting of the second resistor and the third resistor are connected with a second capacitor in parallel, and the third resistor is connected with the slide rheostat in parallel; a series branch consisting of the first resistor, the second resistor and the third resistor is connected with the voltage stabilizing device in parallel; the reference signal end is arranged between the first resistor and the voltage stabilizing device;
the filter circuit comprises a fourth resistor and a third capacitor; one end of the fourth resistor is connected between the first resistor and the second resistor, and the other end of the fourth resistor is grounded through the third capacitor;
the non-inverting input end of the second operational amplifier comprises two branches, one branch is connected between the fourth resistor and the third capacitor through a fifth resistor and a sixth resistor in sequence, and the other branch is grounded through a seventh resistor, an eighth resistor, a ninth resistor and a fourth capacitor in sequence; the current feedback signal end is arranged between the ninth resistor and the fourth capacitor;
the reverse input end of the second operational amplifier comprises two branches, one branch is grounded through a tenth resistor, and the other branch is connected between the fourth resistor and the third capacitor through an eleventh resistor and a twelfth resistor in sequence; the secondary side of the first optical coupling isolation circuit is connected in parallel with two ends of a series branch consisting of the eleventh resistor and the twelfth resistor;
the output end of the second operational amplifier, the first diode, the second diode and the fourteenth resistor are connected in sequence; the COMP signal end is arranged at the other end of the fourteenth resistor;
the PI adjusting circuit further comprises a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a thirteenth resistor; the fifth capacitor is connected between the non-inverting input end and the inverting input end in parallel; one end of the sixth capacitor is connected between the seventh resistor and the eighth resistor, and the other end of the sixth capacitor is grounded; the seventh capacitor is connected between the inverting input end and the output end in parallel; and the eighth capacitor is connected with the ninth capacitor in parallel and then connected with the thirteenth resistor in series, and a series branch formed by the eighth capacitor and the ninth capacitor is connected with the seventh capacitor in parallel.
The invention further provides a preferable technical scheme that: the PWM main control unit comprises a COMP signal receiving end, a second optical coupling isolation circuit and a pulse width modulation circuit; the pulse width modulation circuit comprises an SG2525A/3525A chip;
one end of the primary side of the second optical coupling isolation circuit is connected with a high level, one end of the primary side of the second optical coupling isolation circuit is grounded through a diode, and the anode of the diode is grounded; the second optical coupling isolation circuit is connected with the SG2525A/3525A chip;
and the COMP signal receiving end is connected with the cathode of the diode and used for receiving a COMP signal output by the COMP signal end in the current loop unit.
Compared with the closest prior art, the invention has the beneficial effects that:
the power reduction output circuit for the power conversion device of the high-voltage super capacitor can realize the control of output limit power when the input voltage is too low, perform overcurrent protection, effectively protect a main power switch device and a circuit on the low-voltage side of the power conversion device, improve the safety and reliability of the power conversion device, and further ensure that the high-voltage super capacitor can stably output high-voltage electric energy.
Drawings
FIG. 1: the structure schematic diagram of the power reducing output circuit of the power conversion device for the high-voltage super capacitor in the embodiment of the invention;
FIG. 2: the circuit diagram of the input detection unit in the embodiment of the invention;
FIG. 3: the circuit diagram of the current detection unit in the embodiment of the invention;
FIG. 4: comparing and detecting a hysteresis unit circuit diagram in the embodiment of the invention;
FIG. 5: the circuit diagram of the current loop unit in the embodiment of the invention;
FIG. 6: the circuit diagram of the PWM main control unit in the embodiment of the invention;
FIG. 7: the chip pin diagram of SG2525A/3525A of the embodiment of the invention;
wherein, 101: an input detection unit; 102: a comparison detection hysteresis unit; :103: a current loop unit; 104: a PWM main control unit; 105: a current detection unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The power down output circuit of the power conversion device for the high-voltage super capacitor provided by the embodiment of the invention is described below with reference to the accompanying drawings. The input side of the power conversion device for the high-voltage super capacitor comprises a direct-current input end and a main power switch tube, the output side of the power conversion device comprises a transformer and an output loop, and the main power switch tube, the transformer and the output loop are sequentially connected. The input side is used for adjusting direct current input voltage, and the output side adjusts low voltage output by the input side to high voltage required by working conditions.
Fig. 1 is a schematic structural diagram of a power down output circuit of a power conversion device for a high-voltage super capacitor according to an embodiment of the present invention, and as shown in the drawing, the power down output circuit in this embodiment includes an input voltage detection unit 101, a voltage comparison detection hysteresis unit 102, a current loop unit 103, a PWM main control unit 104, and an output current detection unit 105. Wherein,
1. the connection relationship of each unit in the power reducing output circuit is as follows:
the input end of the input voltage detection unit 101 is connected with the direct current input end, and the output end of the input voltage detection unit 101, the voltage comparison detection hysteresis unit 102, the current loop unit 103 and the PWM main control unit 104 are sequentially connected;
the other input end of the PWM main control unit 104 is connected with the direct current input end, and the output end of the PWM main control unit 104 is connected with the main power switch tube;
the input terminal of the output current detection unit 105 is connected to the output circuit, and the output terminal thereof is connected to the current loop unit 103.
2. The main functions of each unit in the power-down output circuit are as follows:
the input voltage detection unit 101 is used for acquiring a direct current input voltage of a direct current input end and sending the direct current input voltage to the voltage comparison detection hysteresis unit 102;
the output current detection unit 105 is used for collecting the output current of the output loop and sending the output current to the current loop unit 103;
the voltage comparison detection hysteresis unit 102 compares the direct current input voltage with a voltage threshold value, and outputs a comparison point control signal to the current loop unit 103 according to a comparison result;
a current loop unit 103 outputting a COMP signal to the PWM main control unit 104 according to the comparison point control signal and the output signal of the output current detection unit 105;
the PWM main control unit 104 judges whether to adjust the duty ratio of the PWM modulation pulse according to the COMP signal and outputs the PWM modulation pulse to the main power switch tube; the main power switch tube changes rated output current under the control of the PWM modulation pulse, and further changes output power on an output side and input power on an input side in the power supply conversion device. If the PWM main control unit 104 adjusts the duty ratio of the PWM modulation pulse to decrease according to the COMP signal, the rated output current output by the power switching tube under the control of the PWM modulation pulse becomes small, and further the output power at the output side and the input power at the input side in the power conversion device decrease.
The following describes each unit in the reduced power output circuit of the present invention.
I, input voltage detection unit 101
Fig. 2 is a circuit diagram of an input detection unit according to an embodiment of the present invention, and as shown in the figure, the input voltage detection unit 101 in the embodiment includes a resistor R143, a resistor R144, a capacitor C85, and a capacitor C84. The resistor R143 is connected with the resistor R144 in series, the other end of the resistor R143 is connected with an input power supply, the other end of the resistor R144 is grounded, the capacitor C85 is connected with two ends of a series branch formed by the resistor R143 and the resistor R144 in parallel, and the capacitor C84 is connected with the resistor R144 in parallel. The output terminal VIN-VOLTAGE of the input detection unit 101 is disposed between the resistor R143 and the resistor R144.
Second, voltage comparison detection hysteresis unit
The voltage comparison detection hysteresis unit 102 of the present invention includes a signal comparison circuit, a diode, and a first opto-isolator circuit, which are connected in sequence. The signal comparison circuit comprises a first operational amplifier, the inverting input end of which is connected with the input detection unit 101 and receives the direct current input voltage of the direct current input end; the non-inverting input end of the diode receives a voltage threshold signal, and the output end of the diode is connected with the anode of the diode; the primary side of the first optocoupler isolation circuit is connected with the cathode of the diode, and the secondary side of the first optocoupler isolation circuit is connected with the current loop unit 103.
According to the invention, a voltage comparison detection hysteresis unit 102 compares a direct current input voltage with a voltage threshold, if the direct current input voltage is less than or equal to the voltage threshold, a first operational amplifier outputs a high level, a diode and a primary side of a first optical coupling isolation circuit are sequentially conducted, and a secondary side of the first optical coupling isolation circuit outputs a comparison point control signal to a current loop unit 103.
Fig. 4 is a circuit diagram of a VOLTAGE comparison detection hysteresis unit according to an embodiment of the present invention, and as shown in the drawing, the signal comparison circuit in this embodiment includes a first operational amplifier U21-B, a pin 6 of which is connected to an output terminal VIN-VOLTAGE of the input detection unit 101 to receive a dc input VOLTAGE output from the output terminal VIN-VOLTAGE, a pin 5 of which receives a VOLTAGE threshold REF1, a pin 7 of which is connected to an anode of a diode D14, a cathode of the diode D14 is connected to a primary side Q15-B of a first opto-isolator circuit, and a secondary side Q15-a of the first opto-isolator circuit is connected to the current loop unit 103.
When the direct current input voltage is smaller than or equal to the voltage threshold value, namely the value of the pin 6 is smaller than the value of the pin 5, the pin 7 outputs high potential, and the diode D14 and the first optical coupling isolation circuit are both conducted. The pins P2/P3 of the secondary side Q15-A of the first optical coupler isolation circuit are connected with the pins P2/P3 in the current loop unit shown in fig. 5 in a one-to-one correspondence mode, and comparison point control signals are output to the current loop unit.
Three, current loop unit
The current loop unit 103 of the present invention includes a reference signal terminal, a current feedback signal terminal, a COMP signal terminal, a voltage regulator circuit, a voltage divider circuit, a filter circuit, and a PI regulator circuit. Wherein,
the PI regulating circuit comprises a second operational amplifier; the voltage stabilizing circuit, the voltage dividing circuit and the filter circuit are sequentially connected, one branch of the filter circuit is connected with the non-inverting input end of the second operational amplifier, and the other branch of the filter circuit is connected with the inverting input end of the second operational amplifier;
the reference signal end is arranged between the voltage stabilizing circuit and the voltage dividing circuit and used for receiving a reference voltage signal;
the current feedback signal end is connected with the in-phase input end and receives an output signal of the output current detection loop 105;
the COMP signal end is connected with the output end of the second operational amplifier through a diode, and the cathode of the diode is connected with the output end;
the secondary side of the first optical coupler isolation circuit in the comparison detection hysteresis unit 102 is connected between the filter circuit and the reverse input end.
Fig. 5 is a circuit diagram of a current loop unit according to an embodiment of the present invention, as shown in the figure, in the embodiment:
(1) the voltage stabilizing circuit comprises a voltage stabilizing device U3 and a first capacitor C60 which are connected in parallel, wherein the voltage stabilizing device U3 is a controllable voltage stabilizing device, and one end of the controllable voltage stabilizing device is grounded.
(2) The voltage division circuit comprises a first resistor R102, a second resistor R100 and a third resistor R101 which are connected in series; two ends of a series branch consisting of the second resistor R100 and the third resistor R101 are connected with the second capacitor C61 in parallel, and the third resistor R101 is connected with the sliding rheostat RW2 in parallel; a series branch consisting of the first resistor R102, the second resistor R100 and the third resistor R101 is connected with the voltage stabilizing device U3 in parallel; the reference signal terminal REF5 is disposed between the first resistor R102 and the voltage regulator device U3.
(3) The filter circuit comprises a fourth resistor R98 and a third capacitor C59; one end of the fourth resistor R98 is connected between the first resistor R102 and the second resistor R100, and the other end is grounded through the third capacitor C59.
(4) PI regulating circuit
The non-inverting input terminal 5 of the second operational amplifier comprises two branches, one branch is sequentially connected between the fourth resistor R98 and the third capacitor C59 through a fifth resistor R74 and a sixth resistor R75, and the other branch is sequentially grounded through a seventh resistor R71, an eighth resistor R72, a ninth resistor R73 and a fourth capacitor C53; the current feedback signal terminal IO-is disposed between the ninth resistor R73 and the fourth capacitor C53.
The inverting input end 6 of the second operational amplifier comprises two branches, one branch is grounded through a tenth resistor R76, and the other branch is connected between a fourth resistor R98 and a third capacitor C59 through an eleventh resistor R83 and a twelfth resistor R82 in sequence; and a secondary side Q15-A of the first optical coupler isolation circuit is connected in parallel with two ends of a series branch consisting of an eleventh resistor R83 and a twelfth resistor R82.
The output end 7 of the second operational amplifier, the first diode D15, the second diode D45 and the fourteenth resistor R78 are connected in sequence; the COMP signal end is arranged at the other end of the fourteenth resistor R78.
The PI regulating circuit further comprises a fifth capacitor C68, a sixth capacitor C110, a seventh capacitor C54, an eighth capacitor C55, a ninth capacitor C56 and a thirteenth resistor R77; the fifth capacitor C68 is connected in parallel between the non-inverting input terminal 5 and the inverting input terminal 6; one end of the sixth capacitor C110 is connected between the seventh resistor R71 and the eighth resistor R72, and the other end is grounded; the seventh capacitor C54 is connected in parallel between the inverting input terminal 6 and the output terminal 7; the eighth capacitor C55 is connected in parallel with the ninth capacitor C56 and then connected in series with the thirteenth resistor R77, and the formed series branch is connected in parallel with the seventh capacitor C54.
As shown in the figure, in this embodiment, as the current received by the current feedback signal terminal IO-increases, the current feedback signal terminal IO-is a negative voltage, the potential of the positive voltage at the pin 5 is gradually reduced, when the voltage value of the pin 5 is equal to or less than the voltage value of the pin 6, the PI regulation circuit starts to perform PI feedback regulation, enters a constant current working state, and the pin 7 outputs a fixed value.
The working process of the current loop unit 103 in the invention is as follows:
when the current loop unit 103 works in a constant current state, the output end of the second operational amplifier linearly outputs a control signal, so that the second optical coupling isolation circuit of the PWM main control unit is turned on, and the pulse modulation circuit is controlled to output PWM modulation pulses. Based on the difference of the dc input voltage, the operation state of the current loop unit 103 may include the following two cases:
1. when the direct-current input voltage of the power conversion device is greater than the voltage threshold, the reference voltage value of the reverse input end 6 of the second operational amplifier is not changed, and then the voltage value of the COMP signal output by the COMP signal end is not changed, namely the second optical coupling isolation circuit is in a shallow conduction state, and the pulse modulation chip is controlled to output the PWM pulse signal.
2. When the direct current input voltage of the power conversion device is smaller than or equal to the voltage threshold, the reference voltage value of the reverse input end 6 of the second operational amplifier is increased, and then the voltage value of a COMP signal output by a COMP signal end is reduced, namely the second optical coupling isolation circuit is in a deep conduction state, the pulse modulation circuit is controlled to output PWM modulation pulses, at the moment, the duty ratio of the PWM modulation pulses is smaller than that of the PWM modulation pulses output by the clock pulse modulation circuit in the first working state, so that the rated output current of the main power switch tube is reduced, and the output power and the input power of the power conversion device are reduced.
Four, PWM main control unit
The PWM main control unit comprises a COMP signal receiving end, a second optical coupling isolation circuit and a pulse width modulation circuit. Wherein,
the pulse width modulation circuit comprises an SG2525A/3525A chip; one end of the primary side of the second optical coupling isolation circuit is connected with a high level, one end of the primary side of the second optical coupling isolation circuit is grounded through a diode, and the anode of the diode is grounded; the second optical coupler isolation circuit is connected with the SG2525A/3525A chip.
The COMP signal receiving terminal is connected to the cathode of the diode, and is configured to receive a COMP signal output by the COMP signal terminal in the current loop unit 103.
Fig. 6 is a circuit diagram of a PWM main control unit according to an embodiment of the present invention, as shown in the figure, in the embodiment:
(1) the second optical coupling and isolation circuit comprises a primary side Q13-B and a secondary side Q13-A. The secondary side Q13-A is connected with a pulse width modulation circuit. One end of the primary side Q13-B is connected with high potential, the other end is grounded through a resistor R49 and a diode D13 in sequence, and the anode of a diode D13 is grounded. Two ends of the primary side Q13-B are connected in parallel with a resistor R177, and two ends of a series branch consisting of the primary side Q13-B, the resistor R49 and a diode D13 are connected in parallel with a capacitor C65.
The COMP signal receiving end is arranged between the resistor R49 and the diode D13, and the second signal receiving end is connected with the anode of the diode D13.
(2) Pulse width modulation circuit
As shown, pin 3 of the SG2525A/3525A chip is connected to secondary Q13-A, and pin 15 and pin 11 are pulse output pins.
The working process of the PWM main control unit 104 in the present invention is:
after the COMP signal receiving end receives the COMP signal output by the current loop unit 103, the second optical coupling isolation circuit is switched on; the pulse width modulation circuit outputs PWM modulation pulse according to the secondary side voltage, and the main power switch tube outputs rated current under the control of the PWM modulation pulse.
When the direct-current input voltage of the power conversion device is smaller than or equal to the voltage threshold, the secondary side voltage of the second optical coupling isolation circuit is reduced, the duty ratio of the PWM modulation pulse output by the pulse width modulation circuit is reduced, the rated output current output by the main power switch tube under the control of the PWM modulation pulse is reduced, and then the input power and the output power of the power conversion device are reduced.
As shown in the figure, when the current of the primary side Q13-B in the second optical coupler isolation circuit increases, the voltage of the secondary side Q13-a decreases, that is, the input voltage of the pin 3 decreases, and further the duty ratio of the PWM modulation pulse output by the pin 15 and the pin 11 decreases, the rated output current output by the active rate switching tube according to the PWM modulation pulse after the duty ratio decreases, the input power of the power conversion device decreases, so that the circuit device on the input side is protected from working normally, and the power conversion device stably outputs 270V voltage.
FIG. 7 is a schematic diagram of the leads of the SG2525A/3525A chip according to the embodiment of the present invention, as shown in FIGS. 6 and 7:
pin 1: the gain of the error amplifier, which is nominally 80dB, is determined by the feedback or output load, which may be a pure resistor or a combination of resistive and capacitive elements. The common mode input voltage range of the error amplifier is 1.5-5.2V. This terminal is typically connected to a resistor divider connected to the power supply output voltage. In the negative feedback control, the power supply output voltage is divided and compared with the reference voltage.
And a pin 2: the non-inverting input, which is typically connected to a voltage divider resistor on reference voltage pin 16, takes a reference comparison voltage of 2.5V to compare with the sampled voltage on pin 1.
And a pin 3: and the synchronous end is used for external synchronization. When a plurality of chips are required to work synchronously, each chip has respective oscillation frequency and can be respectively connected with the pin 4 and the pin 3 of the chip, at the moment, the working frequencies of all the chips are synchronous with the fastest working frequency of the chips, and the single chip can work at an external clock frequency.
And a pin 4: and a synchronous output end for outputting the synchronous pulse. The chip is used when a plurality of chips work synchronously. However, the operating frequencies of several chips cannot be different too much, and the frequency of the synchronization pulse should be lower than the oscillation frequency. If a plurality of chips do not need to work synchronously, the pin 4 and the pin 3 are suspended. The output frequency of pin 4 is 2 times the output pulse frequency. The voltage range of the output sawtooth wave is 0.6-3.5V.
And a pin 5: and one end of the oscillation capacitor is connected to the pin 5, and the other end of the oscillation capacitor is directly connected to the ground end. The value range is 0.001-0.1 pF. When the capacitor works normally, a sawtooth wave changing from 0.6 to 3.5V can be obtained at two ends of the capacitor.
And a pin 6: and one end of the oscillation resistor is connected to the pin 6, and the other end of the oscillation resistor is directly connected to the ground end. RTThe resistance value of the capacitor determines the charging efficiency of the internal constant current value. The value range is 2-150 k omega. RTThe larger the charging time is; otherwise, the charging time is short.
The discharge of pin 7, Ct, is determined by the dead zone resistance across 5, 7. The charging and discharging loops are separated, so that dead time can be adjusted through the dead time resistor, the dead time adjusting range is wider, the value range is 0-500 omega, and the discharging resistor RDThe larger the resistance value is, the longer the discharge time is; otherwise, the discharge time is short.
Pin 8: soft start, the inverting terminal of the comparator, i.e. the soft starter control terminal (pin 8), pin 8 can be externally connected to a soft start capacitor which is charged by a 50pA constant current source of the internal UREF.
And a pin 9: and the compensation end is provided with an indirect resistor and a capacitor at an output end pin 9 of the error amplifier and an inverting input end pin 1 of the error amplifier to form a PI regulator, and compensates the amplitude-frequency and phase-frequency response characteristics of the system. The working voltage range of the compensation end is 1.5-5.2V.
Pin 10: the latch terminal, pin 10, is an input terminal of the PWM latch, and is typically provided with an over-current detection signal at that terminal. When the overcurrent detection signal is maintained for a long time, the capacitor C connected to the soft start pin 8 is discharged. When the circuit normally works, the end is in high level, and the potential of the end is higher than the peak potential (3,30V) of the sawtooth wave. When the circuit is abnormal, as long as the voltage of the pin 10 is greater than 0.7V, the triode is conducted, and the voltage of the reverse end is lower than the valley voltage (0.9V) of the sawtooth wave, so that the output PWM signal is closed, and the protection effect (the input of a high-level closing signal) is achieved.
Pin 12: ground, all voltages on the chip relative to pin 12, are both power ground and signal ground. In practical circuits, the ground terminals of the main loop and the control loop should be connected, since the feedback voltage to the inverting input of the error amplifier is also relative to pin 12.
Pin 13: the voltage input end of the push-pull output circuit is used as a voltage source of the push-pull output stage, and the output power of the output stage is improved. The power supply can be shared by the pin 15, and a power supply with higher voltage can be used, wherein the voltage range is 18-34V.
Pin 15: chip power end, direct current power is divided into two from pin 15 introduction: one path is used as the working voltage of an internal logic and analog circuit; the other path is sent to the input end of the reference voltage stabilizer to generate 5.1V +/-1 internal reference voltage. If the pin voltage is below the threshold voltage (8V), the internal circuitry of the chip locks out and stops (except for the reference source and necessary circuitry) causing the current consumed to drop to a small value (about 2 mA). In addition, the pin voltage cannot exceed 35V at most, and the capacitor should be used to bypass the ground pin 12 directly.
Pin 16: the voltage of the reference voltage terminal, the reference voltage terminal pin 16, is internally controlled at 5.1V + -1, and can be used as the reference voltage of the error amplifier after voltage division.
The power reduction output circuit for the power conversion device of the high-voltage super capacitor can realize the control of output limit power when the input voltage is too low, perform overcurrent protection, effectively protect a main power switch device and a circuit on the low-voltage side of the power conversion device, improve the safety and reliability of the power conversion device, and further ensure that the high-voltage super capacitor can stably output high-voltage electric energy.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (3)
1. A power reduction output circuit of a power conversion device for a high-voltage super capacitor is characterized in that the power reduction output circuit comprises an input voltage detection unit, a voltage comparison detection hysteresis unit, a current loop unit, a PWM (pulse width modulation) main control unit and an output current detection unit;
the input end of the input voltage detection unit is connected with the direct current input end, and the output end of the input voltage detection unit, the voltage comparison detection hysteresis unit, the current loop unit and the PWM main control unit are sequentially connected;
the other input end of the PWM main control unit is connected with the direct current input end, and the output end of the PWM main control unit is connected with the main power switch tube;
the input end of the output current detection unit is connected with the output loop, and the output end of the output current detection unit is connected with the current loop unit;
the voltage comparison detection hysteresis unit comprises a signal comparison circuit, a diode and a first optical coupling isolation circuit which are connected in sequence;
the signal comparison circuit comprises a first operational amplifier, the inverting input end of the first operational amplifier is connected with the input voltage detection unit, and the first operational amplifier receives the direct current input voltage of the direct current input end; the non-inverting input end of the diode receives a voltage threshold signal, and the output end of the diode is connected with the anode of the diode;
the primary side of the first optical coupling isolation circuit is connected with the cathode of the diode, and the secondary side of the first optical coupling isolation circuit is connected with the current loop unit;
the voltage comparison detection hysteresis unit compares the direct current input voltage with a voltage threshold, if the direct current input voltage is less than or equal to the voltage threshold, the first operational amplifier outputs a high level, the diode and the primary side of the first optical coupling isolation circuit are sequentially conducted, and the secondary side of the first optical coupling isolation circuit outputs a comparison point control signal to the current loop unit;
the current loop unit comprises a reference signal end, a current feedback signal end, a COMP signal end, a voltage stabilizing circuit, a voltage dividing circuit, a filter circuit and a PI adjusting circuit; the PI regulating circuit comprises a second operational amplifier;
the voltage stabilizing circuit, the voltage dividing circuit and the filter circuit are sequentially connected, one branch of the filter circuit is connected with the non-inverting input end of the second operational amplifier, and the other branch of the filter circuit is connected with the inverting input end of the second operational amplifier;
the reference signal end is arranged between the voltage stabilizing circuit and the voltage dividing circuit and used for receiving a reference voltage signal; the current feedback signal end is connected with the in-phase input end and receives an output signal of the output current detection unit;
the COMP signal end is connected with the output end of the second operational amplifier through a diode, and the cathode of the diode is connected with the output end;
the secondary side of a first optical coupling isolation circuit in the voltage comparison detection hysteresis unit is connected between the filter circuit and the reverse input end;
the PWM main control unit comprises a COMP signal receiving end, a second optical coupling isolation circuit and a pulse width modulation circuit; the pulse width modulation circuit comprises an SG2525A or 3525A chip;
one end of the primary side of the second optical coupling isolation circuit is connected with a high level, one end of the primary side of the second optical coupling isolation circuit is grounded through a diode, and the anode of the diode is grounded; the second optical coupler isolation circuit is connected with the SG2525A or 3525A chip;
and the COMP signal receiving end is connected with the cathode of the diode and used for receiving a COMP signal output by the COMP signal end in the current loop unit.
2. The power conversion device power down output circuit for high voltage super capacitor as claimed in claim 1,
the input voltage detection unit is used for collecting the direct current input voltage of the direct current input end and sending the direct current input voltage to the voltage comparison detection hysteresis unit;
the output current detection unit is used for collecting the output current of the output loop and sending the output current to the current loop unit;
the voltage comparison detection hysteresis unit compares the direct current input voltage with a voltage threshold value and outputs a comparison point control signal to the current loop unit;
the current loop unit outputs a COMP signal to the PWM main control unit according to the comparison point control signal and the output signal of the output current detection unit;
the PWM main control unit adjusts the duty ratio of PWM modulation pulse according to the COMP signal and outputs PWM modulation pulse to a main power switch tube; the main power switch tube changes rated output current under the control of the PWM modulation pulse, and further changes output power of an output side and input power of an input side in the power supply conversion device.
3. The power conversion device power down output circuit for high voltage super capacitor as claimed in claim 1,
the voltage stabilizing circuit comprises a voltage stabilizing device and a first capacitor which are connected in parallel, and one end of the voltage stabilizing device is grounded;
the voltage division circuit comprises a first resistor, a second resistor and a third resistor which are connected in series; two ends of a series branch consisting of the second resistor and the third resistor are connected with a second capacitor in parallel, and the third resistor is connected with the slide rheostat in parallel; a series branch consisting of the first resistor, the second resistor and the third resistor is connected with the voltage stabilizing device in parallel; the reference signal end is arranged between the first resistor and the voltage stabilizing device;
the filter circuit comprises a fourth resistor and a third capacitor; one end of the fourth resistor is connected between the first resistor and the second resistor, and the other end of the fourth resistor is grounded through the third capacitor;
the non-inverting input end of the second operational amplifier comprises two branches, one branch is connected between the fourth resistor and the third capacitor through a fifth resistor and a sixth resistor in sequence, and the other branch is grounded through a seventh resistor, an eighth resistor, a ninth resistor and a fourth capacitor in sequence; the current feedback signal end is arranged between the ninth resistor and the fourth capacitor;
the reverse input end of the second operational amplifier comprises two branches, one branch is grounded through a tenth resistor, and the other branch is connected between the fourth resistor and the third capacitor through an eleventh resistor and a twelfth resistor in sequence; the secondary side of the first optical coupling isolation circuit is connected in parallel with two ends of a series branch consisting of the eleventh resistor and the twelfth resistor;
the output end of the second operational amplifier, the first diode, the second diode and the fourteenth resistor are connected in sequence; the COMP signal end is arranged at the other end of the fourteenth resistor;
the PI adjusting circuit further comprises a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a thirteenth resistor;
the fifth capacitor is connected between the non-inverting input end and the inverting input end of the second operational amplifier in parallel; one end of the sixth capacitor is connected between the seventh resistor and the eighth resistor, and the other end of the sixth capacitor is grounded; the seventh capacitor is connected in parallel between the inverting input end and the output end of the second operational amplifier; and the eighth capacitor is connected with the ninth capacitor in parallel and then connected with the thirteenth resistor in series, and a series branch formed by the eighth capacitor and the ninth capacitor is connected with the seventh capacitor in parallel.
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| CN106531255B (en) * | 2016-12-27 | 2017-12-08 | 四川英杰电气股份有限公司 | Comparison point method to set up and device |
| CN108738192B (en) * | 2017-04-19 | 2020-03-06 | 赤多尼科两合股份有限公司 | Light modulation circuit |
| CN107612106A (en) * | 2017-10-10 | 2018-01-19 | 深圳前海云霸智谷科技有限公司 | The application system of shared power circuit and the circuit |
| CN111585541B (en) * | 2020-06-03 | 2021-02-09 | 深圳市昊源建设监理有限公司 | Building construction remote monitoring system based on thing networking |
| CN118249290A (en) * | 2021-07-19 | 2024-06-25 | 杭州先途电子有限公司 | Control circuit and controller |
| CN115712270B (en) * | 2022-10-18 | 2024-08-06 | 国能信控互联技术(河北)有限公司 | PLC circuit for detecting balance among super capacitor groups and operation method |
| CN116735936B (en) * | 2023-08-15 | 2023-10-13 | 北京交通大学 | Closed-loop control circuit for frequency response flatness of broadband resistor divider |
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