CN106058836B - High current surge suppressor - Google Patents
High current surge suppressor Download PDFInfo
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- CN106058836B CN106058836B CN201610529191.XA CN201610529191A CN106058836B CN 106058836 B CN106058836 B CN 106058836B CN 201610529191 A CN201610529191 A CN 201610529191A CN 106058836 B CN106058836 B CN 106058836B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention discloses a kind of high current surge suppressors, including power supply circuit, for output voltage signal after input voltage progress steady pressure treatment；Square wave generation circuit, for receiving the voltage signal of power supply circuit output to generate the square-wave signal of fixed frequency；Booster circuit, for receiving square-wave signal and by output voltage signal after amplifier；NMOS tube grid voltage suppression circuit, the voltage signal for exporting booster circuit are suppressed in preset range and export supply external circuit again, including the concatenated NMOS tube group of at least two groups, and every group of NMOS tube group includes at least two NMOS tubes in parallel.The present invention takes the structure design that connection in series-parallel combines due to the NMOS tube in NMOS tube grid voltage suppression circuit, when surge voltage is come temporarily, the grid voltage of each NMOS tube in NMOS tube grid voltage suppression circuit is suppressed to different voltage respectively, each NMOS tube undertakes a part of load respectively, solves the problems, such as that single NMOS tube is easily damaged because undertaking excessive power consumption in existing NMOS tube parallel-connection structure.
Description
Technical field
The present invention relates to aviation power system technical field more particularly to a kind of high current surge suppressors.
Background technology
As the continuous promotion of people's levels of substance and the requirement to going out line efficiency, airplane trip receive people's
Favor.In aviation power system aboard, power supply system may will produce high-voltage pulse in load and unloading, with power generation
For machine exports 28V voltages, 80V may be up to there are one voltage when power supply system loads and unloads, the time is up to number
Ten milliseconds of high-voltage pulse.To protect the safety of subsequent conditioning circuit, one need to be added between generator output end and DC/DC power modules
A surge suppressor module, with inhibit it is possible that maximum 80V/100ms pulse, ensure DC/DC power modules it is defeated
Enter voltage within the safe range of permission.
Currently, in the market in similar surge suppressor product, surge suppressor of the usual electric current within 7A takes list
A NMOS tube scheme, but when electric current is more than 8A, can be handled using multiple NMOS tube parallel ways, at this point, because device
The power consumption that part inner parameter is inconsistent and some NMOS tube can be caused to undertake is far longer than other NMOS tubes and occurs being easy impaired
The problem of.
Invention content
The technical problem to be solved in the present invention is, provides a kind of high current surge suppressor, and solution is deposited in the prior art
NMOS tube parallel-connection structure in the single NMOS tube problem easily damaged because undertaking excessive power consumption.
To solve the above problems, the technical solution adopted by the present invention is：A kind of high current surge suppressor is provided, including：
Power supply circuit, for output voltage signal after input voltage progress steady pressure treatment；
Square wave generation circuit, the voltage signal for receiving the power supply circuit output are believed with the square wave for generating fixed frequency
Number, the square wave occurs circuit inner structure and is specially：Including Schmidt trigger IC, eleventh resistor R11, the 14th resistance
R14, the 8th capacitance C8 and the 9th capacitance C9, the Schmidt trigger IC include the 1st ~ the 14th pin, the 14th pin with
The output end VCC connections of the power supply circuit and the 14th pin is also by the 8th capacitance C8 ground connection, the 7th pin connects
Ground, the 1st pin and the 2nd pin are connected to the 10th pin and the 10th pin also pass sequentially through the 14th resistance R14 and
9th capacitance C9 ground connection, the 3rd pin are connected to booster circuit, and the 8th pin and the 9th pin are connected to the 14th resistance
On circuit between R14 and the 9th capacitance C9, the 5th pin and the 6th pin are connected to one end of eleventh resistor R11, institute
The other end for stating eleventh resistor R11 is connected to the output end VCC of the power supply circuit, and the 12nd pin and the 13rd pin connect
It is connected to the 4th pin, the 11st pin is connected to NMOS tube grid voltage suppression circuit；The ground terminal of the 8th capacitance C8 connects
It is connected to the third leading foot of this suppressor, the 5th pin is additionally coupled to the 4th leading foot of this suppressor；
Booster circuit, square-wave signal for receiving side's wave generation circuit are simultaneously believed by output voltage after amplifier
Number；
NMOS tube grid voltage suppression circuit, the voltage signal for exporting the booster circuit are suppressed to preset range
Supply external circuit, including the concatenated NMOS tube group of at least two groups are inside exported again, and every group of NMOS tube group includes at least two in parallel
NMOS tube.
Further, the power supply circuit includes the first resistor R1 being sequentially connected in series, second resistance R2 and the first voltage stabilizing two
The outer end of pole pipe D1, the first resistor R1 are additionally coupled to external input terminal VIN, and the anode of the first zener diode D1 connects
Ground, the power supply circuit further include that the base stage of the first emitter follower Q1, the first emitter follower Q1 is connected to the second electricity
It hinders on the circuit between R2 and the first zener diode D1, collector is connected to the line between first resistor R1 and second resistance R2
On the road, emitter is connect with the output end VCC of the power supply circuit and the emitter is also by the first capacitance C1 ground connection；It is described
Input terminal VIN is connected to first leading foot of this suppressor, the second leading foot, first leading foot and the second leading foot conduct
The external power supply input pin of this suppressor.
Further, the booster circuit includes：Be sequentially connected in series from external input terminal VIN to external delivery point Vout
12 resistance R12, the 6th capacitance C6, the 6th zener diode D6 and the 4th capacitance C4, the electricity of the twelfth resistor R12 and the 6th
Hold the circuit between C6 also by one the 8th zener diode D8 ground connection, the plus earth of the 8th zener diode D8；It is described
Booster circuit further include the seventh zener diode D7 in parallel with the 6th zener diode D6 and the concatermer of the 4th capacitance C4 with
And the 7th triode Q7, the anode of the 7th zener diode D7 is connected to external delivery point Vout and cathode is connected to the 6th
The cathode of the anode of zener diode D6, the 6th zener diode D6 is additionally coupled to the output end T of booster circuit；Described
The emitter of seven triode Q7 is grounded, and collector is connected to the circuit between twelfth resistor R12 and the 8th zener diode D8
On, the 3rd pin that base stage passes through the sides of being connected to thirteenth resistor R13 wave generation circuit.
Further, the NMOS tube group of the NMOS tube grid voltage suppression circuit includes two groups of NMOS tube groups, wherein
First NMOS tube group includes the first NMOS tube Q2 and the second NMOS tube Q4, and the second NMOS tube group includes third NMOS tube Q3 and the 4th
The drain electrode of NMOS tube Q5, the first NMOS tube Q2 and the second NMOS tube Q4 are connected to external input terminal VIN, the third
The source electrode of NMOS tube Q3 and the 4th NMOS tube Q5 be connected to external delivery point Vout, the 4th zener diode D4 anode and
7th leading foot of this suppressor and the 8th leading foot；The grid of the grid of the first NMOS tube Q2 and the second NMOS tube Q4
Pole is connected to the first end of 3rd resistor R3, the first NMOS tube Q2 and by the 5th resistance R5 and the 6th resistance R6 respectively
The source electrode of two NMOS tube Q4 is connected to drain electrode and the third zener diode D3 of third NMOS tube Q3 and the 4th NMOS tube Q4
Anode, the cathode of the third zener diode D3 are connected to the moon of the first end and the second zener diode D2 of 3rd resistor R3
Pole, the plus earth of the second zener diode D2；The grid of the third NMOS tube Q3 and the 4th NMOS tube Q5 leads to respectively
The first end that the 7th resistance R7 and the 8th resistance R8 is connected to the 4th resistance R4 is crossed, the first end of the 4th resistance R4 is also connected with
To the cathode of the 4th zener diode D4, the second end of the second end of the 3rd resistor R3 and the 4th resistance R4 are and institute
State the output end T connections of booster circuit；The first end of the 4th resistance R4 is additionally coupled to the collector of the 6th triode Q6, institute
The base stage for stating the 6th triode Q6 passes through the 11st pin of the tenth sides of being connected to resistance R10 wave generation circuit, the six or three pole
The emitter of pipe Q6 is grounded；The first end of the 4th resistance R4 is also connected by the doublet of the second capacitance C2 and the 9th resistance R9
It is connected to the 6th leading foot of this suppressor；Inversely conducting is connected with the 5th voltage stabilizing two between 5th leading foot and ground of this suppressor
Pole pipe D5.
By using above-mentioned technical proposal, the present invention at least has the advantages that：The present invention by power supply circuit and
The voltage signal of circuit output fixed frequency occurs for square wave, then is carried out after boosting processing by NMOS tube grid electricity via booster circuit
Suppression circuit is pressed to carry out voltage inhibition processing, since the NMOS tube in NMOS tube grid voltage suppression circuit is combined using connection in series-parallel
Structure design, when surge voltage carrys out interim, the grid voltage difference of each NMOS pipes in NMOS tube grid voltage suppression circuit
It is suppressed to different voltage, each NMOS tube undertakes a part of load respectively, solves single in existing NMOS tube parallel-connection structure
The NMOS tube problem easily damaged because undertaking excessive power consumption.
Description of the drawings
Fig. 1 is the structural schematic diagram of high current surge suppressor of the present invention.
Fig. 2 is the power supply circuit internal structure schematic diagram of high current surge suppressor of the present invention.
Fig. 3 is that circuit inner structure schematic diagram occurs for the square wave of high current surge suppressor of the present invention.
Fig. 4 is the booster circuit internal structure schematic diagram of high current surge suppressor of the present invention.
Fig. 5 is the NMOS tube grid voltage suppression circuit internal structure schematic diagram of high current surge suppressor of the present invention.
Fig. 6 is the topological structure work flow diagram of high current surge suppressor of the present invention.
Specific implementation mode
Invention is further described in detail in the following with reference to the drawings and specific embodiments.It should be appreciated that the present invention's shows
Meaning property embodiment and its explanation are but not as a limitation of the invention for explaining the present invention.
As shown in Figure 1, the present invention provides a kind of high current surge suppressor, including：
Power supply circuit 1, for external output voltage signal after input voltage progress steady pressure treatment；
Square wave generation circuit 2, for receiving the voltage signal of the output of the power supply circuit 1 to generate fixed frequency
Square-wave signal；
Booster circuit 3, square-wave signal for receiving side's wave generation circuit 2 and by exporting one after an amplifier
A voltage signal；
NMOS tube grid voltage suppression circuit 4, the voltage signal for exporting the booster circuit 3 is suppressed to predetermined model
In enclosing, then output supply external circuit, including the concatenated NMOS tube group of at least two groups, every group of NMOS tube group includes at least two
NMOS tube in parallel.
As shown in Fig. 2, power supply circuit 1 includes first resistor R1, the second resistance R2 being sequentially connected in series and two pole of the first voltage stabilizing
The outer end of pipe D1, the first resistor R1 are additionally coupled to external input terminal VIN, and the anode of the first zener diode D1 connects
Ground, the power supply circuit 1 further include that the base stage of the first emitter follower Q1, the first emitter follower Q1 is connected to the second electricity
It hinders on the circuit between R2 and the first zener diode D1, collector is connected to the line between first resistor R1 and second resistance R2
On the road, emitter is connect with the output end VCC of the power supply circuit 1 and the emitter is also by the first capacitance C1 ground connection；Institute
State the first leading foot, the first leading foot and NMOS tube grid voltage suppression circuit that input terminal VIN is connected to this suppressor, institute
State the external power supply input pin of the first leading foot and the second leading foot as this suppressor.
As shown in figure 3, in one alternate embodiment, square wave generation circuit 2 includes Schmidt trigger IC, the 11st electricity
Hinder R11, the 14th resistance R14, the 8th capacitance C8 and the 9th capacitance C9, the model that the Schmidt trigger IC is selected
The 14th pin of CD4093, the CD4093 are connect with the output end VCC of the power supply circuit 1 and the 14th pin also passes through
8th capacitance C8 ground connection, the 7th pin ground connection of CD4093, the 1st pin of CD4093 and the 2nd pin are connected to the 10th pin and institute
It states the 10th pin and also passes sequentially through the 14th resistance R14 and the 9th capacitance C9 ground connection, the 3rd pin of CD4093 is connected to boosting
Circuit, the 8th pin of CD4093 and the 9th pin are connected on the circuit between the 14th resistance R14 and the 9th capacitance C9,
The 5th pin of CD4093 and the 6th pin are connected to one end of eleventh resistor R11, and the other end of the eleventh resistor R11 connects
The 12nd pin and the 13rd pin for being connected to the output end VCC, CD4093 of the power supply circuit 1 are connected to the 4th pin, CD4093's
11st pin is connected to NMOS tube grid voltage suppression circuit；The ground terminal of the 8th capacitance C8 is connected to the of this suppressor
Three leading foots, the 5th pin are additionally coupled to the 4th leading foot of this suppressor.
As shown in figure 4, booster circuit 3 includes the ten be sequentially connected in series from external input terminal VIN to external delivery point Vout
Two resistance R12, the 6th capacitance C6, the 6th zener diode D6 and the 4th capacitance C4, twelfth resistor R12 and the 6th capacitance C6 it
Between circuit also pass through one the 8th zener diode D8 ground connection, the plus earth of the 8th zener diode D8；The boosting
Circuit 3 further includes the seventh zener diode D7 and in parallel with the concatermer of the 6th zener diode D6 and the 4th capacitance C4
Seven triode Q7, the anode of the 7th zener diode D7 is connected to external delivery point Vout and cathode is connected to the 6th voltage stabilizing
The cathode of the anode of diode D6, the 6th zener diode D6 is additionally coupled to the output end T of booster circuit 3；Described 7th
The emitter of triode Q7 is grounded, and collector is connected on the circuit between twelfth resistor R12 and the 8th zener diode D8,
The 3rd pin that base stage passes through the sides of being connected to thirteenth resistor R13 wave generation circuit 2.
As shown in figure 5, in one alternate embodiment, the NMOS tube group of NMOS tube grid voltage suppression circuit 4 includes two
Group NMOS tube group, wherein the first NMOS tube group includes the first NMOS tube Q2 and the second NMOS tube Q4, and the second NMOS tube group includes the
The drain electrode of three NMOS tube Q3 and the 4th NMOS tube Q5, the first NMOS tube Q2 and the second NMOS tube Q4 are connected to external input
The source electrode of end VIN, the third NMOS tube Q3 and the 4th NMOS tube Q5 are connected to external delivery point Vout, two pole of the 4th voltage stabilizing
The anode of pipe D4 and the 7th leading foot of this suppressor and the 8th leading foot；The grid of the first NMOS tube Q2 and described
The grid of two NMOS tube Q4 is connected to the first end of 3rd resistor R3 by the 5th resistance R5 and the 6th resistance R6 respectively, and described
The source electrode of one NMOS tube Q2 and the second NMOS tube Q4 are connected to drain electrode and the third of third NMOS tube Q3 and the 4th NMOS tube Q4
The cathode of the anode of zener diode D3, the third zener diode D3 is connected to the first end and second of 3rd resistor R3 surely
Press the cathode of diode D2, the plus earth of the second zener diode D2；The third NMOS tube Q3 and
The grid of four NMOS tube Q5 is connected to the first end of the 4th resistance R4 by the 7th resistance R7 and the 8th resistance R8 respectively, and described
The first end of four resistance R4 is additionally coupled to the cathode of the 4th zener diode D4, the second end of the 3rd resistor R3 and described
The second end of four resistance R4 is connect with the output end T of the booster circuit 3；The first end of the 4th resistance R4 is additionally coupled to
The base stage of the collector of 6th triode Q6, the 6th triode Q6 passes through the tenth sides of being connected to resistance R10 wave generation circuit 2
The 11st pin, the 6th triode Q6 emitter ground connection；The first end of the 4th resistance R4 also passes through the second capacitance
The doublet of C2 and the 9th resistance R9 are connected to the 6th leading foot of this suppressor；Between 5th leading foot and ground of this suppressor
Reverse conducting is connected with the 5th zener diode D5.
As shown in fig. 6, in one alternate embodiment, by taking piezoelectric voltage 28V on product as an example, circuit of the invention work is former
Reason includes：
S11 adds 28V voltages to the product of the present invention；
S12, product after the power is turned on, by current-limiting resistance R1 and R2, a 15V voltage signal are generated on zener diode D1,
15V voltages are subjected to Current amplifier by emitter follower Q1, are powered to Schmitt trigger CD4093；
S13,8,9 pins of Schmidt trigger CD4093 are low level when just powering on, therefore the output of 10 pins is high electricity
Flat, which charges by resistance R14 to capacitance C9, after capacitance C9 voltage-to-grounds are more than the threshold voltage of CD4093,10
Pin output is low level by high level saltus step, and capacitance C9 begins through resistance R14 electric discharges again, when capacitance C9 voltage-to-grounds are less than
After the threshold voltage of CD4093, the output of 10 pins, at high level, repeatedly, obtains fixed frequency by low transition
Square wave, input of the output as booster circuit after by a trigger by waveform shaping；
S14, square-wave signal voltage after resistance R13 and triode Q7 are amplified, when triode Q7 exports low level, from
Output of products end charges to capacitance C6 through voltage-stabiliser tube D7, when triode Q7 exports high level, due to the both ends capacitance C6 electricity
Pressure cannot be mutated, and the terminal voltage that capacitance C6 is connected with triode Q7 at this time becomes product input voltage from 0V, then the other end
Voltage also accordingly increase, charge is pumped into capacitance C4 through voltage-stabiliser tube D6.The effect of voltage-stabiliser tube D8 is inhibited when 80V surges come
Capacitance C6 voltage elevation amplitudes reduce component pressure value, reduce element cost；
S15, power supply system will produce a voltage in load and unloading and be up to 80V, and the time is up to several ms
High-voltage pulse；
Whether S16, NMOS tube grid voltage suppression circuit detection input voltage need to inhibit；
S17, if input voltage needs to inhibit, since NMOS tube takes Q2, Q4 in parallel, Q3, Q5 are in parallel, then go here and there again
Connection.The output voltage of booster circuit is through resistance R3 and voltage-stabiliser tube D2, and maximum limit is within 65V, then using resistance R5, electricity
Resistance R6 is added on the grid of Q2, Q4, and gate source voltage difference is limited within 15V by voltage-stabiliser tube D3.Equally, booster circuit is defeated
Go out voltage and pass through resistance R3, resistance R9, voltage-stabiliser tube D5 and external voltage-stabiliser tube are suppressed in 40V or so, then pass through resistance R7, electricity
Resistance R8 is added on the grid of Q3, Q5, and gate source voltage difference is limited within 15V by voltage-stabiliser tube voltage-stabiliser tube D4；
S18, if input voltage need not inhibit, the grid voltage of Q2, Q3, Q4, Q5 are higher 15V than source voltage,
So that Q2, Q3, Q4, Q5 are completely open-minded, conduction voltage drop very little.When 80V surges come temporarily, the grid voltage of Q2, Q4 are limited in
65V, lower than the drain voltage of 80V, Q2, Q4 are operated in linearly interval at this time, are a drain electrode follower, source output voltage quilt
Inhibit in 60V or so, the grid voltage of same Q3, Q5 are limited in 40V, lower than the drain voltage of 60V, at this time Q3, Q5 also work
Make in linearly interval, source output voltage is suppressed within 38V.In this way, during electric current is the 80V/100ms surges of 10A,
The hourglass source electrode pressure drop that Q2, Q4 are born is 20V or so, and it is 20V or so, two groups of NMOS tube difference that Q3, Q5, which bear hourglass source electrode pressure drop also,
It undertakes
200 watts of dissipated power inhibits voltage within claimed range.
The present invention provides a kind of high current surge suppressor, and circuit output fixed frequency occurs by power supply circuit and square wave
Voltage signal, then boosted circuit carries out carrying out voltage inhibition by NMOS tube grid voltage suppression circuit after boosting processing
Reason, since the NMOS tube in NMOS tube grid voltage suppression circuit takes the structure design that connection in series-parallel combines, when surge voltage is come
Temporarily, the grid voltage of each NMOS tube in NMOS tube grid voltage suppression circuit is suppressed to different voltage, each NMOS respectively
Pipe undertakes a part of load respectively, solve in existing NMOS tube parallel-connection structure single NMOS tube due to undertaking excessive power consumption easily by
The problem of damage.Circuit structure of the present invention is simple, of low cost, autgmentability is strong.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
Describe in detail it is bright, it should be understood that the above is only a specific embodiment of the present invention, the guarantor being not intended to limit the present invention
Range is protected, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should be included in this
Within the protection domain of invention.
Claims (4)
1. a kind of high current surge suppressor, it is characterised in that：Including：
Power supply circuit（1）, for external output voltage signal after input voltage progress steady pressure treatment；
Square wave generation circuit（2）, for receiving the power supply circuit（1）The voltage signal of output is to generate the square wave of fixed frequency
Signal, side's wave generation circuit（2）Internal structure is specially：Including Schmidt trigger IC, eleventh resistor R11, the tenth
Four resistance R14, the 8th capacitance C8 and the 9th capacitance C9, the Schmidt trigger IC include the 1st ~ the 14th pin, the described 14th
Pin and the power supply circuit（1）Output end VCC connections and the 14th pin also by the 8th capacitance C8 ground connection, described the
The ground terminal of eight capacitance C8 is additionally coupled to the third leading foot of this suppressor, the 7th pin ground connection, the 1st pin and the 2nd
Pin is connected to the 10th pin and the 10th pin also passes sequentially through the 14th resistance R14 and the 9th capacitance C9 ground connection, described
3rd pin is connected to booster circuit（3）, the 8th pin and the 9th pin are connected to the 14th resistance R14 and the 9th capacitance C9
Between circuit on；5th pin and the 6th pin are connected to one end of eleventh resistor R11, and the 5th pin is also connected with
To the 4th leading foot of this suppressor, the other end of the eleventh resistor R11 is connected to the power supply circuit（1）Output end
VCC, the 12nd pin and the 13rd pin are connected to the 4th pin, and the 11st pin is connected to the inhibition of NMOS tube grid voltage
Circuit（4）；
Booster circuit（3）, for receiving side's wave generation circuit（2）Square-wave signal and believed by output voltage after amplifier
Number；
NMOS tube grid voltage suppression circuit（4）, it is used for the booster circuit（3）The voltage signal of output is suppressed to predetermined model
Export supply external circuit, including the concatenated NMOS tube group of at least two groups in enclosing again, every group of NMOS tube group includes at least two simultaneously
The NMOS tube of connection.
2. high current surge suppressor according to claim 1, it is characterised in that：The power supply circuit（1）Including successively
The outer end of concatenated first resistor R1, second resistance R2 and the first zener diode D1, the first resistor R1 are additionally coupled to outer
Connect input terminal VIN, the plus earth of the first zener diode D1；The power supply circuit（1）It further include the first emitter following
The base stage of device Q1, the first emitter follower Q1 are connected to the circuit between second resistance R2 and the first zener diode D1
On, collector is connected on the circuit between first resistor R1 and second resistance R2, emitter and the power supply circuit（1）It is defeated
Outlet VCC connections and the emitter also pass through the first capacitance C1 and are grounded；The external input terminal VIN is connected to this suppressor
First leading foot, the second leading foot, first leading foot and the second leading foot draw as the external power supply input of this suppressor
Foot.
3. high current surge suppressor according to claim 1, it is characterised in that：The booster circuit（3）Including：From outer
Connect twelfth resistor R12, the 6th capacitance C6, the 6th zener diode that input terminal VIN to external delivery point Vout is sequentially connected in series
D6 and the 4th capacitance C4, the circuit between the twelfth resistor R12 and the 6th capacitance C6 also pass through one the 8th zener diode
D8 is grounded, the plus earth of the 8th zener diode D8；The booster circuit（3）Further include and the 6th zener diode D6
With the 7th zener diode D7 and the 7th triode Q7 of the concatermer parallel connection of the 4th capacitance C4, the 7th zener diode
The anode of D7 is connected to external delivery point Vout and cathode is connected to the anode of the 6th zener diode D6, the 6th voltage stabilizing two
The cathode of pole pipe D6 is connected to booster circuit（3）Output end T, the 7th triode Q7 emitter ground connection, collector connect
It is connected on the circuit between twelfth resistor R12 and the 8th zener diode D8, base stage passes through the sides of being connected to thirteenth resistor R13
Wave generation circuit（2）The 3rd pin.
4. high current surge suppressor according to claim 1, it is characterised in that：The NMOS tube grid voltage inhibits
Circuit（4）NMOS tube group include two groups of NMOS tube groups, wherein the first NMOS tube group includes in parallel the first NMOS tube Q2 and the
Two NMOS tube Q4, the second NMOS tube group include the third NMOS tube Q3 and the 4th NMOS tube Q5 of parallel connection, the first NMOS tube Q2
Drain electrode with the second NMOS tube Q4 is connected to external input terminal VIN, the source of the third NMOS tube Q3 and the 4th NMOS tube Q5
Pole is connected to the 7th leading foot and the 8th of external delivery point Vout, the anode of the 4th zener diode D4 and this suppressor
Leading foot；The grid of the grid of the first NMOS tube Q2 and the second NMOS tube Q4 pass through the 5th resistance R5 and the 6th respectively
Resistance R6 is connected to the first end of 3rd resistor R3, and the source electrode of the first NMOS tube Q2 and the source electrode of the second NMOS tube Q4 connect
It is connected to the anode of the drain electrode and third zener diode D3 of third NMOS tube Q3 and the 4th NMOS tube Q5, two pole of third voltage stabilizing
The cathode of pipe D3 is connected to the cathode of the first end and the second zener diode D2 of 3rd resistor R3, second zener diode
The plus earth of D2；The grid of the third NMOS tube Q3 and the 4th NMOS tube Q5 passes through the 7th resistance R7 and the 8th resistance respectively
R8 is connected to the first end of the 4th resistance R4, and the first end of the 4th resistance R4 is additionally coupled to the moon of the 4th zener diode D4
Pole, the second end of the 4th resistance R4 and the second end of 3rd resistor R3 with the booster circuit（3）Output end T connect
It connects；The first end of the 4th resistance R4 is additionally coupled to the collector of the 6th triode Q6, the base stage of the 6th triode Q6
Pass through the tenth sides of being connected to resistance R10 wave generation circuit（2）The 11st pin, the 6th triode Q6 emitter ground connection；
The first end of the 4th resistance R4 is also connected to the of this suppressor by the doublet of the second capacitance C2 and the 9th resistance R9
Six leading foots；Inversely conducting is connected with the 5th zener diode D5 between 5th leading foot and ground of this suppressor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610529191.XA CN106058836B (en) | 2016-07-06 | 2016-07-06 | High current surge suppressor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610529191.XA CN106058836B (en) | 2016-07-06 | 2016-07-06 | High current surge suppressor |
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| Publication Number | Publication Date |
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| CN106058836A CN106058836A (en) | 2016-10-26 |
| CN106058836B true CN106058836B (en) | 2018-09-21 |
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| CN201610529191.XA Active CN106058836B (en) | 2016-07-06 | 2016-07-06 | High current surge suppressor |
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|---|---|---|---|---|
| CN106655136A (en) * | 2016-12-12 | 2017-05-10 | 成都航天通信设备有限责任公司 | Airborne station lightning protection circuit |
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| CN106058836A (en) | 2016-10-26 |
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Denomination of invention: High current surge suppressor Effective date of registration: 20210208 Granted publication date: 20180921 Pledgee: Shenzhen Branch of China Merchants Bank Co.,Ltd. Pledgor: SHENZHEN ZHENHUA MICROELECTRONICS Co.,Ltd. Registration number: Y2021440020003 |