CN106024899B - A kind of semiconductor field effect transistor and its manufacturing method - Google Patents
A kind of semiconductor field effect transistor and its manufacturing method Download PDFInfo
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- CN106024899B CN106024899B CN201610562559.2A CN201610562559A CN106024899B CN 106024899 B CN106024899 B CN 106024899B CN 201610562559 A CN201610562559 A CN 201610562559A CN 106024899 B CN106024899 B CN 106024899B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 45
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 230000000873 masking effect Effects 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 abstract description 21
- 239000001301 oxygen Substances 0.000 abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses a kind of semiconductor field effect transistor and its manufacturing methods, this method comprises: first part region on a semiconductor substrate forms mask layer；It is to shelter successively formation well region, source area in the semiconductor substrate and grow localized oxidation of silicon layer with mask layer；Remove mask layer；Grid oxide layer and polysilicon layer are sequentially formed, to obtain semiconductor field effect transistor.The present invention efficiently solve it is existing after grid oxygen technique manufacture VDMOS open time delay can be long technical problem, and then reduce the open time delay of rear grid oxygen technique manufacture semiconductor field effect transistor, to effectively increase the quality of the VDMOS of rear grid oxygen technique.
Description
Technical field
The present invention relates to semiconductor field more particularly to a kind of semiconductor field effect transistor and its manufacturing methods.
Background technique
In power semiconductor field, VDMOSFET is known as with the vertical nMOSFET that vertical double diffusion technique is formed, referred to as
VDMOS.It is widely used because VDMOS has the characteristics that switching speed is fast, input impedance is high, frequency characteristic is good.
Conventional VDMOS device application is preceding grid oxygen technique, it may be assumed that grid oxygen technique and polycrystalline formation process are in well region and source
It is completed before polar region injection and diffusion technique.Under this preceding grid oxygen technique, the formation of polysilicon and trap injection, source electrode injection can be certainly
Alignment, the grid source overlap capacitance of the VDMOS device produced is smaller, therefore open time delay is shorter.
But the VDMOS needed for certain special dimensions is higher to the reliability requirement of grid oxygen, this just needs grid oxygen technique and more
Crystal silicon is completed after trap technique, it may be assumed that rear grid oxygen technique.But the sequence for rear grid oxygen technique is on the contrary, polysilicon is formed, trap is infused
Enter, source electrode injection respectively needs a photoetching, therefore formed usually can not be from trap injection, source implantation process for polysilicon
Alignment.In order to guarantee that technological fluctuation situation lower channel can be normally-open under the premise of can not be self aligned, grid after fabrication
Polysilicon border and well region boundary, source area boundary usually guarantee certain overlapping length, overlapping length when the VDMOS of oxygen technique
It is related to the alignment precision of technology room twice, because of prior art equipment it is difficult to ensure that alignment precision, therefore it is existing after grid oxygen technique
The open time delay of VDMOS can be long, affect the performance of VDMOS.
Summary of the invention
The embodiment of the present invention by providing a kind of semiconductor field effect transistor and its manufacturing method, solve it is existing after grid
The open time delay of the VDMOS of oxygen technique can be long technical problem.
In a first aspect, the embodiment of the invention provides a kind of semiconductor field effect transistor manufacturing methods, comprising: partly leading
First part region in body substrate forms mask layer；It is that masking is successively formed in the semiconductor substrate with the mask layer
Well region, source area and grow localized oxidation of silicon layer；Remove the mask layer；Grid oxide layer and polysilicon layer are sequentially formed, to obtain
Obtain the semiconductor field effect transistor.
Preferably, described to sequentially form grid oxide layer and polysilicon layer includes: to grow thickness on the first part region
Degree is less than the grid oxide layer of the thickness of the localized oxidation of silicon layer；It leans on the grid oxide layer and on the localized oxidation of silicon layer
The polysilicon layer is grown on the partial region of the nearly grid oxide layer.
Preferably, the semiconductor substrate and the source area are p-type doping, and the well region is n-type doping；Or described half
Conductor substrate and the source area are n-type doping, and the well region is p-type doping.
Preferably, the first part region on a semiconductor substrate forms mask layer, comprising: serves as a contrast in the semiconductor
Deposit silicon nitride on bottom, to form silicon nitride film；Etch the nitridation in addition to the first part region of the silicon nitride film
Silicon, to form the mask layer.
Preferably, it is described with the mask layer be masking successively in the semiconductor substrate formed well region, source area and
Grow localized oxidation of silicon layer, comprising: be on the semiconductor substrate that masking carries out trap injection and trap pushes away with the mask layer
Into to form the well region；Second part region on the well region forms photoresist layer, wherein the second part area
Domain is separated by with the first part region；It is to be sequestered in the well region to form source electrode with the mask layer and the photoresist layer
Area；Remove the photoresist layer；It is that masking grows localized oxidation of silicon layer with the mask layer.
Second aspect, the embodiment of the invention provides a kind of semiconductor field effect transistors, comprising: semiconductor substrate, trap
Area, localized oxidation of silicon layer, localized oxidation of silicon layer, grid oxide layer, polysilicon layer；The well region is formed in the semiconductor substrate,
The source area is formed in the well region, localized oxidation of silicon layer growth in the semiconductor substrate with the source electrode
The position of area's alignment, wherein the thickness of the localized oxidation of silicon layer is greater than the thickness of the grid oxide layer, and the grid oxide layer is grown in
Between the adjacent source area in the semiconductor substrate, the polysilicon layer is formed on the grid oxide layer and the part
On the partial region of the close grid oxide layer on silicon oxide layer.
Preferably, the semiconductor substrate and the source area are p-type doping, and the well region is n-type doping；Or described half
Conductor substrate and the source area are n-type doping, and the well region is p-type doping.
One or more technical solution provided in an embodiment of the present invention, at least realizes following technical effect or advantage:
Since the embodiment of the present invention is with same mask layer on a semiconductor substrate in the VDMOS manufacture of rear grid oxygen technique
Masking forms well region, source area and grows localized oxidation of silicon layer, so as to make localized oxidation of silicon layer and well region, source area from right
Standard, the oxidation in first part region will receive mask layer limitation when due to oxidation, so as to grow localized oxidation of silicon layer, office
The growth of portion's silicon oxide layer can increase the oxidated layer thickness of grid source overlapping region, to effectively reduce grid source overlap capacitance, from
And be able to solve it is existing after the manufacture of grid oxygen technique VDMOS open time delay can be long technical problem, and then subtract
The open time delay of the semiconductor field effect transistor of rear grid oxygen technique manufacture is lacked, to effectively increase rear grid oxygen technique
The quality of VDMOS.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the structural schematic diagram of semiconductor field effect transistor in the embodiment of the present invention；
Fig. 2 is the flow chart that the present invention applies semiconductor field effect transistor manufacturing method in example；
Fig. 3~Fig. 7 is the substep schematic diagram of semiconductor field effect transistor in the embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Embodiment one:
The embodiment of the invention provides a kind of semiconductor field effect transistor manufacturing methods, with reference to shown in FIG. 1 to FIG. 7, this
The semiconductor field effect transistor manufacturing method that inventive embodiments provide includes the following steps:
S101, first part region on semiconductor substrate 1 form mask layer 7.
Specifically, the material of mask layer 7 can be silicon nitride (Si3N4), SiO can also be used2Instead of film can also be used
The film, the non-Si material that crome metal etc. can bear high-temperature technology replace.
By taking the material of mask layer 7 is silicon nitride as an example: deposit silicon nitride is on semiconductor substrate 1 to form silicon nitride film；
The silicon nitride in addition to first part region of etch nitride silicon fiml is to form mask layer 7.
It S102, is that masking successively forms well region 2, source area 3 and growth local silicon in semiconductor substrate 1 with mask layer 7
Oxide layer 4.
Specifically, S102 includes: Step 1: carrying out trap injection and trap with mask layer 7 on semiconductor substrate 1 for masking
It promotes, to form well region 2.Step 2: the second part region on well region 2 forms photoresist layer 8, wherein second part
Region is separated by with first part region.Specifically, after photoresist layer 8 is resist coating film on semiconductor substrate 1, to photoresist
Photoresist part on film in addition to second part region carries out photoetching, to form photoresist layer 8.Step 3: with mask layer 7
It is to be sequestered in formation source area 3 in well region 2 with photoresist layer 8.Step 4: removal photoresist layer 8.Step 5: being with mask layer 7
Masking grows localized oxidation of silicon layer 4.
S103, removal mask layer 7.
S104, grid oxide layer 5 and polysilicon layer 6 are sequentially formed, to obtain semiconductor field effect transistor.
Specifically, growing grid oxide layer 5 of the thickness less than the thickness of localized oxidation of silicon layer 4 on first part region.?
Polysilicon layer 6 is grown on the partial region of grid oxide layer 5 on grid oxide layer 5 and on local silicon oxide layer 4.It had been embodied
Cheng Zhong, the formation process of grid oxide layer 5, the formation process of polysilicon layer 6 refer to the prior art, in order to illustrate the succinct of book, originally
Text repeats no more.
Specifically, semiconductor substrate 1 and source area 3 are p-type doping, well region 2 is n-type doping, then the embodiment of the present invention
Semiconductor field effect transistor is specially N-channel VDMOS pipe；Semiconductor substrate 1 and source area 3 are n-type doping, and well region 2 is p-type
Doping, then semiconductor field effect transistor provided in an embodiment of the present invention is specially P-channel VDMOS pipe.
Semiconductor field effect transistor manufacturing process after forming polysilicon layer 6 can refer to the prior art, in order to say
Bright book it is succinct, repeat no more herein.
It is brilliant to semiconductor field provided in an embodiment of the present invention by taking P-channel VDMOS pipe as an example below with reference to Fig. 3~Fig. 7
Body pipe manufacturing method is illustrated:
As shown in figure 3, deposit silicon nitride is in the semiconductor substrate 1 of n-type doping to form silicon nitride film, etch silicon nitride
The mask layer 7 for the masking that silicon nitride on the region in addition to first part region of film is injected using being formed as p-well.
As shown in figure 4, being to be sequestered in progress p-well injection and p-well in the semiconductor substrate 1 of n-type doping to push away with mask layer 7
It proceeds to and reaches design object, to form p-well region 2.
As shown in figure 5, second part region on p-well region 2 forms photoresist layer 8, wherein second part region and the
A part of region is separated by.It then is to be sequestered in formation N-type source region 3 in P type trap zone 2 with mask layer 7 and photoresist layer 8.
As shown in fig. 6, removing photoresist layer 8 after forming N-type source region 3.With mask layer 7 after removing photoresist layer 8
Localized oxidation of silicon layer 4 is grown for masking.To which the oxidation in first part region is limited by mask layer 7, thus n-type doping
The oxidation of the exposed region of semiconductor substrate 1 can be greater than the oxidation under mask layer 7, to reach the semiconductor lining to n-type doping
The LOCOS (localized oxidation of silicon, Local Oxidation of Silicon) at bottom 1, to form localized oxidation of silicon layer 4, passes through
The localized oxidation of silicon layer 4 of formation can increase the oxidated layer thickness of grid source overlapping region, so that grid source overlap capacitance is reduced, with optimization
The open time delay of semiconductor field effect transistor.
Refering to what is shown in Fig. 7, removing mask layer 7 and sequentially forming grid oxide layer 5 and polysilicon layer 6 after removing mask layer 7.
Specifically, growth thickness is less than the thickness of localized oxidation of silicon layer 4 on first part region after removal mask layer 7
Grid oxide layer 5.Growing polycrystalline silicon layer 6 on the partial region of close grid oxide layer 5 on grid oxide layer 5 and on local silicon oxide layer 4.Make
Polysilicon layer 6 and p-well region 2,3 boundary both of which of N-type source region guarantee certain overlapping length.
Other semiconductor field effect transistor manufacturing processes after polysilicon layer 6 can refer to the prior art, manufacture shape
At semiconductor field effect transistor as shown in Figure 1, in order to illustrate the succinct of book, herein no longer to forming polysilicon layer 6
Manufacturing process afterwards is described.
Below to semiconductor field effect transistor manufacturing method provided in an embodiment of the present invention by taking N-channel VDMOS pipe as an example
(not shown) is described:
After deposit silicon nitride is in the semiconductor substrate of p-type doping to form silicon nitride film, etch nitride silicon fiml except the
Silicon nitride except a part of region is to form mask layer.
It is to be sequestered in the injection of progress N trap and N trap in p-type dope semiconductor substrates to be advanced into and reach design mesh with mask layer
Mark, to form N well region.Second part region on N well region forms photoresist layer, second part region and first part region
It is separated by.It then, is to be sequestered in formation p-type source area in N-type well region with mask layer and photoresist layer.After forming p-type source area
Remove photoresist layer.Localized oxidation of silicon layer is grown for masking with mask layer after removal photoresist layer.Due to first part region
Oxidation will receive the limitation of mask layer, the oxidation of the exposed region of the semiconductor substrate of p-type doping can be greater than under mask layer
Oxidation, to reach the LOCOS (localized oxidation of silicon) of the semiconductor substrate to p-type doping, the formation of localized oxidation of silicon layer can increase
The oxidated layer thickness of big grid source overlapping region, so that grid source overlap capacitance is reduced, to optimize opening for semiconductor field effect transistor
Logical delay time.
Removal mask layer simultaneously sequentially forms grid oxide layer and polysilicon layer after removing mask layer.Specifically, removal exposure mask
Growth thickness is less than the grid oxide layer of the thickness of localized oxidation of silicon layer on first part region after layer.It is on grid oxide layer and local
Growing polycrystalline silicon layer on the partial region of close grid oxide layer on silicon oxide layer.To ensure that polysilicon layer and N well region, p-type source
Polar region boundary both of which guarantees certain overlapping length.Semiconductor field effect transistor manufacturing process after polysilicon layer is equal
It can refer to the prior art, in order to illustrate the succinct of book, repeat no more herein.
Embodiment two:
Based on the same inventive concept, the embodiment of the invention provides a kind of semiconductor field effect transistors.With reference to Fig. 1, Fig. 3
Shown in~Fig. 7, semiconductor field effect transistor provided in an embodiment of the present invention includes: semiconductor substrate 1, well region 2, local silicon oxygen
Change layer 3, localized oxidation of silicon layer 4, grid oxide layer 5 and polysilicon layer 6.Well region 2 is formed in semiconductor substrate 1；Source area 3 is formed in
In well region 2；The position being aligned with source area 3 of the growth of localized oxidation of silicon layer 4 in semiconductor substrate 1；Grid oxide layer 5 is grown in half
Between adjacent source regions 3 in conductor substrate 1；Polysilicon layer 6 is formed in close on grid oxide layer 5 and on local silicon oxide layer 5
On the partial region of grid oxide layer 5.
Specifically, semiconductor substrate 1 and source area 3 are p-type doping, well region 2 is n-type doping, then the embodiment of the present invention
Semiconductor field effect transistor is specially N-channel VDMOS pipe；Semiconductor substrate 1 and source area 3 are n-type doping, and well region 2 is p-type
Doping, then semiconductor field effect transistor provided in an embodiment of the present invention is specially P-channel VDMOS pipe.
One or more technical solution provided in an embodiment of the present invention, at least realizes following technical effect or advantage:
Since the embodiment of the present invention is with same mask layer on a semiconductor substrate in the VDMOS manufacture of rear grid oxygen technique
Masking forms well region, source area and grows localized oxidation of silicon layer, so as to make localized oxidation of silicon layer and well region, source area from right
Standard, the oxidation in first part region will receive mask layer limitation when due to oxidation, so as to grow localized oxidation of silicon layer, office
The growth of portion's silicon oxide layer can increase the oxidated layer thickness of grid source overlapping region, to effectively reduce grid source overlap capacitance, from
And be able to solve it is existing after the manufacture of grid oxygen technique VDMOS open time delay can be long technical problem, and then subtract
The open time delay of the semiconductor field effect transistor of rear grid oxygen technique manufacture is lacked, to effectively increase rear grid oxygen technique
The quality of VDMOS.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (4)
1. a kind of semiconductor field effect transistor manufacturing method characterized by comprising
First part region on a semiconductor substrate forms mask layer；
It is to shelter successively formation well region, source area in the semiconductor substrate and grow localized oxidation of silicon with the mask layer
Layer；
Remove the mask layer；
Grid oxide layer and polysilicon layer are sequentially formed, to obtain the semiconductor field effect transistor；
It is described to sequentially form grid oxide layer and polysilicon layer includes:
The grid oxide layer of the thickness less than the thickness of the localized oxidation of silicon layer is grown on the first part region；
It is grown on the partial region of the grid oxide layer on the grid oxide layer and on the localized oxidation of silicon layer described more
Crystal silicon layer.
2. semiconductor field effect transistor manufacturing method as described in claim 1, it is characterised in that:
The semiconductor substrate and the source area are p-type doping, and the well region is n-type doping；Or
The semiconductor substrate and the source area are n-type doping, and the well region is p-type doping.
3. semiconductor field effect transistor manufacturing method as described in claim 1, which is characterized in that described in semiconductor substrate
On first part region formed mask layer, comprising:
Deposit silicon nitride on the semiconductor substrate, to form silicon nitride film；
The silicon nitride in addition to the first part region of the silicon nitride film is etched, to form the mask layer.
4. semiconductor field effect transistor manufacturing method as described in claim 1, which is characterized in that described with the mask layer
To shelter successively formation well region, source area in the semiconductor substrate and growing localized oxidation of silicon layer, comprising:
It is on the semiconductor substrate that masking carries out trap injection and trap promotes with the mask layer, to form the well region；
Second part region on the well region forms photoresist layer, wherein the second part region and described first
Subregion is separated by；
It is to be sequestered in the well region to form source area with the mask layer and the photoresist layer；
Remove the photoresist layer；
It is that masking grows localized oxidation of silicon layer with the mask layer.
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| US5966621A (en) * | 1996-11-14 | 1999-10-12 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
| CN1971944A (en) * | 2005-11-24 | 2007-05-30 | 上海华虹Nec电子有限公司 | A MOS FET tube and its manufacturing method |
| JP2012129348A (en) * | 2010-12-15 | 2012-07-05 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing semiconductor device |
| CN102148164B (en) * | 2011-03-10 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | The forming method of VDMOS device |
| JP2015041644A (en) * | 2013-08-20 | 2015-03-02 | 富士電機株式会社 | Method of manufacturing mos type semiconductor device |
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Effective date of registration: 20220824 Address after: Room 108, floor 1, building 4, No. 2 dacuodeng Hutong, Dongcheng District, Beijing 100010 Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |