CN106024805B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN106024805B CN106024805B CN201610384273.XA CN201610384273A CN106024805B CN 106024805 B CN106024805 B CN 106024805B CN 201610384273 A CN201610384273 A CN 201610384273A CN 106024805 B CN106024805 B CN 106024805B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- G02F1/136286—Wiring, e.g. gate line, drain line
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Abstract
The invention discloses an array substrate, a display panel and display equipment, and belongs to the field of display. The first row of the array substrate comprises first pixel structures and second pixel structures which are alternately arranged, each first pixel structure comprises two first sub-pixel electrodes which are arranged in parallel, each first sub-pixel electrode is close to a corresponding target data line, a TFT corresponding to each first sub-pixel electrode is positioned on one side, close to the corresponding target data line, of each first sub-pixel electrode, and each first sub-pixel electrode is electrically connected to the corresponding target data line; the second pixel structure comprises two second seed pixel electrodes which are arranged in parallel, the second seed pixel electrodes are far away from corresponding target data lines, the TFTs corresponding to the second seed pixel electrodes are located on one sides, close to the target data lines, of the second seed pixel electrodes, and the second seed pixel electrodes are electrically connected to the target data lines through wiring, so that the power consumption of the array substrate is reduced.
Description
Technical Field
The invention relates to the field of display, in particular to an array substrate, a display panel and display equipment.
Background
The array substrate is an important component of the liquid crystal display device, and is located between a backlight source and a liquid crystal layer of the liquid crystal display device. The array substrate is used for controlling liquid crystal molecules in the liquid crystal layer to turn, so that the liquid crystal layer transmits partial light emitted by the backlight source, and the transmitted light can form a picture on a screen of the liquid crystal display device.
Each row of the conventional array substrate includes a plurality of pixel structures arranged in parallel, the polarities of two adjacent pixel structures are different, a first data line is arranged on the left side of the pixel structure, a second data line is arranged on the right side of the pixel structure, the polarities of the first data line and the second data line are different, and the polarity of one data line is the same as the polarity of the pixel structure, and the first data line is assumed. The pixel structure comprises a first TFT (Thin Film Transistor), a second TFT, a first sub-pixel electrode and a second sub-pixel electrode which are arranged in parallel; the first TFT is positioned on one side of the first sub-pixel electrode, which is far away from the first data line, the first sub-pixel electrode is connected to the first data line through a routing wire, the second TFT is positioned on one side of the second sub-pixel electrode, which is close to the first data line, and the second sub-pixel electrode is connected to the first data line through the routing wire.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
because each sub-pixel electrode in the array substrate is connected to the data line by the routing, and each routing and the liquid crystal layer of the liquid crystal display device form a capacitor, the display power consumption of the array substrate is improved.
Disclosure of Invention
In order to solve the problems in the prior art, embodiments of the present invention provide an array substrate, a display panel and a display device. The technical scheme is as follows:
in a first aspect, an array substrate is provided, where a first row of the array substrate includes first pixel structures and second pixel structures that are alternately arranged, the first pixel structures are located between a first data line and a second data line, the second pixel structures are located between the second data line and a third data line, and the first row is any row of the array substrate;
the first pixel structure comprises two first sub-pixel electrodes which are arranged in parallel, the first sub-pixel electrodes are close to corresponding target data lines, the polarities of the first sub-pixel electrodes and the corresponding target data lines are the same, the TFT thin film transistors corresponding to the first sub-pixel electrodes are located on one sides, close to the target data lines, of the first sub-pixel electrodes, and the first sub-pixel electrodes are electrically connected to the target data lines;
the second pixel structure comprises two second seed pixel electrodes which are arranged in parallel, the second seed pixel electrodes are far away from corresponding target data lines, the polarity of the second seed pixel electrodes is the same as that of the corresponding target data lines, the TFTs corresponding to the second seed pixel electrodes are located on one sides, close to the target data lines, of the second seed pixel electrodes, and the second seed pixel electrodes are electrically connected to the target data lines through wiring.
Optionally, the first pixel structure includes a first TFT, a second TFT, and a first subpixel electrode and a second subpixel electrode that are arranged in parallel, where the polarity of the first data line and the polarity of the first subpixel electrode are both first polarities, the polarity of the second data line and the polarity of the second subpixel electrode are both second polarities, the first TFT is located on one side of the first subpixel electrode close to the first data line, and connects the first subpixel electrode to the first data line, and the second TFT is located on one side of the second subpixel electrode close to the second data line, and connects the second subpixel electrode to the second data line.
Optionally, an opening is formed at a top corner of one side of the first subpixel electrode, which is close to the first data line, and the first TFT is located at the opening.
Optionally, an opening is formed at a vertex angle of one side of the second subpixel electrode close to the second data line, and the second TFT is located at the opening.
Optionally, the second pixel structure includes a third TFT, a fourth TFT, a third sub-pixel electrode and a fourth sub-pixel electrode that are arranged in parallel, where a polarity of the fourth sub-pixel electrode is a second polarity, a polarity of the third data line and a polarity of the third sub-pixel electrode are both first polarities, the third TFT is located on one side of the third sub-pixel electrode close to the third data line, the third sub-pixel electrode is connected to the third data line through a first routing line, the fourth TFT is located on one side of the fourth sub-pixel electrode close to the second data line, and the fourth sub-pixel electrode is connected to the second data line through a second routing line.
Optionally, a third pixel structure located between the first data line and the second data line in the second row of the array substrate is the same as the second pixel structure, and includes a fifth TFT and a sixth TFT, and a fifth sub-pixel electrode and a sixth sub-pixel electrode are arranged in parallel; the polarity of the fifth sub-pixel electrode is the same as that of the second data line, the polarity of the sixth sub-pixel electrode is the same as that of the first data line, and the second row is a next row adjacent to the first row;
the fifth TFT is positioned on one side of the fifth sub-pixel electrode close to the second data line, and the fifth sub-pixel electrode is connected to the second data line through a third routing line; the sixth TFT is located on one side, close to the first data line, of the sixth sub-pixel electrode, and the sixth sub-pixel electrode is connected to the first data line through a fourth routing line.
Optionally, an opening is formed at a vertex angle of one side of the first subpixel electrode, which is close to the fifth subpixel electrode, and the first TFT is located at the opening; or, an opening is arranged at the top corner of one side of the first sub-pixel electrode, which is far away from the fifth sub-pixel electrode, and the first TFT is located at the opening.
Optionally, a fourth pixel structure located between the second data line and the third data line in a second row of the array substrate is the same as the first pixel structure, and the second row is a next row adjacent to the first row;
the fourth pixel structure comprises a seventh TFT, an eighth TFT, and a seventh sub-pixel electrode and an eighth sub-pixel electrode which are arranged in parallel; the polarity of the seventh sub-pixel electrode is the same as that of the second data line, and the polarity of the eighth sub-pixel electrode is the same as that of the third data line;
the seventh TFT is positioned on one side of the seventh sub-pixel electrode close to the second data line and connects the seventh sub-pixel electrode to the second data line; the eighth TFT is positioned on one side of the eighth sub-pixel electrode close to the third data line and connects the eighth sub-pixel electrode to the third data line.
Optionally, an opening is disposed at a vertex of one side of the seventh subpixel electrode close to the second data line, and the seventh TFT is located at the opening.
Optionally, an opening is formed at a vertex angle of one side of the eighth subpixel electrode close to the third data line, and the eighth TFT is located at the opening.
In a second aspect, a display panel is provided, which includes the array substrate.
In a third aspect, a display device is provided, comprising a display panel as described.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
because half of the pixel structures can exist in each row, the two sub-pixel electrodes included in the pixel structures are respectively close to the data lines with the same polarity as the respective data lines, and the TFTs corresponding to the sub-pixel electrodes are also arranged on one side of the sub-pixel electrodes close to the data lines with the same polarity as the sub-pixel electrodes, so that the sub-pixel electrodes are directly electrically connected to the data lines, and thus, the sub-pixel electrodes can be omitted from being electrically connected to the data lines through wiring, and the power consumption of the array substrate is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic view of another array substrate structure according to an embodiment of the invention;
fig. 3 is a schematic view of another array substrate structure according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
Referring to fig. 1, a first row of the array substrate includes first pixel structures 1 and second pixel structures 2 alternately arranged, the first pixel structures 1 are located between a first data line 3 and a second data line 4, and the second pixel structures 2 are located between the second data line 4 and a third data line 5, where the first row is any row in the array substrate.
The first pixel structure 1 comprises two first sub-pixel electrodes arranged in parallel, the first sub-pixel electrodes are close to corresponding target data lines, the polarities of the first sub-pixel electrodes and the corresponding target data lines are the same, the TFTs corresponding to the first sub-pixel electrodes are positioned on one sides of the first sub-pixel electrodes close to the target data lines, and the first sub-pixel electrodes are electrically connected to the target data lines;
the second pixel structure 2 includes two second seed pixel electrodes arranged in parallel, the second seed pixel electrodes are far away from the corresponding target data lines, the polarity of the second seed pixel electrodes is the same as that of the corresponding target data lines, the TFTs corresponding to the second seed pixel electrodes are located on one side of the second seed pixel electrodes close to the target data lines, and the second seed pixel electrodes are electrically connected to the target data lines through wiring.
Optionally, the first pixel structure 1 includes a first TFT11, a second TFT12, and a first subpixel electrode 13 and a second subpixel electrode 14 arranged in parallel, that is, the first subpixel electrode 13 and the second subpixel electrode 14 are both first subpixel electrodes; the polarity of the first subpixel electrode 13 is different from the polarity of the second subpixel electrode 14, the polarity of the first data line 3 and the polarity of the first subpixel electrode 13 are both the first polarity, and the polarity of the second data line 4 and the polarity of the second subpixel electrode 14 are both the second polarity.
The first polarity may be a positive electrode, and the second polarity may be a negative electrode. For example, as shown in fig. 1, the polarity of the first data line 3 and the polarity of the first subpixel electrode 13 are both positive; the second data line 4 and the second subpixel electrode 14 have the same polarity and are both negative.
The first TFT11 is located on a side of the first sub-pixel electrode 13 close to the first data line 3, connecting the first sub-pixel electrode 13 to the first data line 3, and the second TFT12 is located on a side of the second sub-pixel electrode 14 close to the second data line 4, connecting the second sub-pixel electrode 14 to the second data line 4.
Further, the first row further includes two rows of gate lines, which are a first gate line a and a second gate line b, respectively, and the first gate line a and the second gate line b are located at two sides of the first pixel structure 1 and the second pixel structure 2 included in the first row.
Wherein, an opening is arranged at the top corner of one side of the first sub-pixel electrode 13 close to the first data line 3, and the first TFT11 is arranged at the opening; a gate electrode of the first TFT11 is electrically connected to one of the two rows of gate lines; a first terminal of the first TFT11 is electrically connected to the first data line 3, and a second terminal is electrically connected to the first subpixel electrode 13.
Alternatively, referring to fig. 1, an opening is formed at a top corner of one side of the first subpixel electrode 13 close to the first data line 3 and the second gate line b, the first TFT11 may be disposed at the opening, and the gate electrode of the first TFT11 is electrically connected to the second gate line b; alternatively, referring to fig. 2, the first subpixel electrode 13 may be provided with an opening at a top corner of one side thereof near the first data line 3 and the first gate line a, the first TFT11 may be provided at the opening, and the gate electrode of the first TFT11 may be electrically connected to the first gate line a.
An opening is arranged at the top corner of one side of the second sub-pixel electrode 14 close to the second data line 4, and the second TFT12 is arranged at the opening; the gate electrode of the second TFT12 is electrically connected to the other of the two rows of gate lines, and the first terminal of the second TFT12 is electrically connected to the second data line 4 and the second terminal is electrically connected to the second sub-pixel electrode 14.
Alternatively, referring to fig. 1, an opening is disposed at a top corner of one side of the second subpixel electrode 14 close to the second data line 4 and the first gate line a, the second TFT12 may be disposed at the opening, and the gate electrode of the second TFT12 is electrically connected to the first gate line a; alternatively, referring to fig. 2, the second subpixel electrode 14 may have an opening at a top corner of one side thereof near the second data line 4 and the second gate line b, the second TFT12 may be disposed at the opening, and the gate electrode of the second TFT12 may be electrically connected to the second gate line b.
Optionally, the second pixel structure 2 includes a third TFT21, a fourth TFT22, and a third sub-pixel electrode 23 and a fourth sub-pixel electrode 24 that are arranged in parallel, that is, the third sub-pixel electrode 23 and the fourth sub-pixel electrode 24 are second sub-pixel electrodes, the polarity of the third sub-pixel electrode 23 is different from the polarity of the fourth sub-pixel electrode 24, the polarity of the second data line 4 is the same as the polarity of the fourth sub-pixel electrode 24, and is a second polarity, and the polarity of the third data line 5 is the same as the polarity of the third sub-pixel electrode 23, and is a first polarity; for example, as shown in fig. 1, the polarity of the second data line 4 and the polarity of the fourth subpixel electrode 24 are both negative, and the polarity of the third data line 5 and the polarity of the third subpixel electrode 23 are both positive.
Referring to fig. 1 and 2, the third TFT21 is located on a side of the third sub-pixel electrode 23 close to the third data line 5, the third sub-pixel electrode 23 is connected to the third data line 5 through the first routing line 25, the fourth TFT22 is located on a side of the fourth sub-pixel electrode 24 close to the second data line 4, and the fourth sub-pixel electrode 24 is connected to the second data line 4 through the second routing line 26.
Two top corners of the third sub-pixel electrode 23 close to the third data line 5 are provided with openings, and two top corners of the fourth sub-pixel electrode 24 close to the second data line 4 are also provided with openings; two groups of openings adjacent to the third sub-pixel electrode 23 and the fourth sub-pixel electrode 24 form two opening spaces; the third TFT21 is disposed in one of the open spaces, and has a gate electrically connected to one of the first gate line a and the second gate line b, a first terminal of the third TFT21 is electrically connected to the third data line 5 through the first trace 25, and a second terminal is electrically connected to the third subpixel electrode 23. The fourth TFT22 is disposed in the other open space, and has a gate electrically connected to the other of the first gate line a and the second gate line b, a first end of the fourth TFT22 is electrically connected to the second data line 4 through the second wire 26, and a second end is electrically connected to the fourth subpixel electrode 24.
For example, as shown in fig. 1, the third TFT21 is disposed in an open space near a first gate line a, the gate electrode of the third TFT21 may be electrically connected to the first gate line a, the fourth TFT22 may be disposed in another open space near a second gate line b, and the gate electrode of the fourth TFT22 is electrically connected to the second gate line b; alternatively, as shown in fig. 2 for example, the third TFT21 is disposed in one side of the open space near the second gate line b, the gate electrode of the third TFT21 is electrically connected to the second gate line b, the fourth TFT22 is disposed in the other side of the open space near the first gate line a, and the gate electrode of the fourth TFT22 is electrically connected to the first gate line a.
Optionally, in this embodiment, the polarity of the first data line 3 is the same as the polarity of the third data line 5, and both are the first polarity, the polarity of the first data line 3 is different from the polarity of the second data line 4, and the polarity of the second data line 4 is the second polarity. The polarity of the first data line 3 and the polarity of the third data line 5 may be positive, and the polarity of the second data line 4 may be negative; alternatively, the polarity of the first data line 3 and the polarity of the third data line 5 may be negative, and the polarity of the second data line 4 may be positive. For example, as shown in fig. 1, the polarities of the first data line 4 and the third data line 5 are both positive, and the polarity of the second data line is negative.
Referring to fig. 3 or 4, it should be noted that: the first row may include a plurality of first pixel structures 1 and a plurality of second pixel structures 2, and the plurality of first pixel structures 1 and the plurality of second pixel structures 2 are alternately arranged. Since the first TFT11 and the second TFT12 in each first pixel structure 1 are both directly connected to their respective adjacent data lines, two routing wires are omitted, and the power consumption of the two routing wires is omitted, thereby reducing the power consumption of the array substrate.
The first pixel structures and the second pixel structures included in two adjacent rows of the array substrate are arranged in different alternating sequences. For the next row adjacent to the first row in the array substrate, the next row is referred to as a second row for convenience of description.
Alternatively, still referring to fig. 1, the pixel structure between the first data line 3 and the second data line 4 in the second row of the array substrate is a third pixel structure 6.
The third pixel structure 6 includes a fifth TFT61, a sixth TFT62, a fifth sub-pixel electrode 63, and a sixth sub-pixel electrode 64 arranged in parallel; the polarity of the fifth subpixel electrode 63 is the same as that of the second data line 4, and is the second polarity, and the polarity of the sixth subpixel electrode 64 is the same as that of the first data line 3, and is the first polarity; for example, in the example shown in fig. 1, the polarity of the fifth subpixel electrode 63 and the polarity of the second data line 4 are both negative, and the polarity of the sixth subpixel electrode 64 and the polarity of the first data line 3 are both positive.
The fifth TFT61 is located on one side of the fifth sub-pixel electrode 63 close to the second data line 4, and connects the fifth sub-pixel electrode 63 to the second data line 4 through the third trace 65; the sixth TFT62 is located on a side of the sixth subpixel electrode 64 close to the first data line 3, and connects the sixth subpixel electrode 64 to the first data line 3 via the fourth trace 66.
Further, the second row further includes two rows of gate lines, which are a third gate line c and a fourth gate line d, respectively, and the third gate line c and the fourth gate line d are located at two sides of the third pixel structure 6 included in the second row.
In the third subpixel structure 6, two top corners of the fifth subpixel electrode 63 on the side close to the second data line 4 are both provided with openings, and two top corners of the sixth subpixel electrode 64 on the side close to the first data line 3 are also both provided with openings; two groups of openings adjacent to the fifth sub-pixel electrode 63 and the sixth sub-pixel electrode 64 form two opening spaces; the fifth TFT61 is disposed in one of the open spaces and has its gate electrically connected to one of the third gate line c and the fourth gate line d, e.g., as in the example shown in fig. 1 or 2, the gate of the fifth TFT61 is electrically connected to the third gate line c; a first terminal of the fifth TFT61 is electrically connected to the second data line 4 through the third wire 65, and a second terminal is electrically connected to the fifth subpixel electrode 63. The sixth TFT62 is disposed in the other open space and has its gate electrically connected to the other of the third gate line c and the fourth gate line d, e.g., as in the example shown in fig. 1 or 2, the gate of the sixth TFT64 is electrically connected to the fourth gate line d; a first terminal of the sixth TFT64 is electrically connected to the first data line 3 through the fourth wire 66, and a second terminal is electrically connected to the sixth subpixel electrode 64.
Alternatively, the pixel structure between the second data line 4 and the third data line 5 in the second row of the array substrate is referred to as a fourth pixel structure 7;
the fourth pixel structure 7 includes a seventh TFT71, an eighth TFT72, a seventh sub-pixel electrode 73, and an eighth sub-pixel electrode 74 arranged in parallel; the polarity of the seventh subpixel electrode 71 is the same as the polarity of the second data line 2 and is the second polarity, and the polarity of the eighth subpixel electrode 74 is the same as the polarity of the third data line 5 and is the first polarity; for example, in the example shown in fig. 1, the polarity of the seventh subpixel electrode 73 is the same as the polarity of the second data line 4, and both polarities thereof are negative, and the polarity of the eighth subpixel electrode 74 is the same as the polarity of the third data line 5, and both polarities thereof are positive.
Optionally, the seventh TFT71 is located on a side of the seventh sub-pixel electrode 73 close to the second data line 4, and connects the seventh sub-pixel electrode 73 to the second data line 4; the eighth TFT72 is located on a side of the eighth subpixel electrode 74 near the third data line 5, connecting the eighth subpixel electrode 74 to the third data line 5.
Wherein, an opening is arranged at the top corner of one side of the seventh sub-pixel electrode 73 close to the second data line 4, and the seventh TFT71 is arranged at the opening; a gate electrode of the seventh TFT71 is electrically connected to one of the third gate line c and the fourth gate line d, and as an example shown in fig. 1, the seventh TFT71 is disposed in an open space adjacent to the fourth gate line d, and a gate electrode of the seventh TFT71 is electrically connected to the fourth gate line d. A first terminal of the seventh TFT71 is electrically connected to the second data line 4, and a second terminal is electrically connected to the seventh subpixel electrode 73.
An opening is arranged at the top corner of one side of the eighth sub-pixel electrode 74 close to the third data line 5, and an eighth TFT72 is arranged at the opening; a gate electrode of the eighth TFT72 is electrically connected to another gate line of the third gate line c and the fourth gate line d, and as shown in fig. 1, an eighth TFT72 is disposed in another open space adjacent to the third gate line c, a gate electrode of the eighth TFT72 is electrically connected to the third gate line c, a first terminal of the eighth TFT72 is electrically connected to the third data line 5, and a second terminal is electrically connected to the eighth subpixel electrode 74.
Among them, it should be noted that: referring to fig. 1 to 4, the sub-pixel electrodes of the first polarity and the sub-pixel electrodes of the second polarity are alternately arranged in any one row, for example, in the first row, the polarity of the first sub-pixel electrode is the first polarity, the polarity of the second sub-pixel electrode is the second polarity, the polarity of the third sub-pixel electrode is the first polarity, and the polarity of the fourth sub-pixel electrode is the second polarity; the first polarity sub-pixel electrodes and the second polarity sub-pixel electrodes in any column are also alternately arranged, for example, the polarity of the first sub-pixel electrode between the first data line 3 and the second data line 4 is the first polarity, and the polarity of the fifth sub-pixel electrode is the second polarity; therefore, the sub-pixel electrodes with the first polarity and the sub-pixel electrodes with the second polarity in each row or each column of the array substrate provided by the embodiment of the invention are alternately arranged, so that a dot inversion structure is realized, and an image display effect is provided.
Optionally, as shown in fig. 3 and 4, it should be noted that: the second row may include a plurality of third pixel structures 6 and a plurality of fourth pixel structures 7, and the plurality of third pixel structures 6 and the plurality of fourth pixel structures 7 are alternately arranged. Since the seventh TFT71 and the eighth TFT72 in each fourth pixel structure 7 are directly connected to their respective adjacent data lines, two routing lines are omitted, and the power consumption of the two routing lines is reduced, thereby reducing the power consumption of the array substrate.
The array substrate comprises a plurality of rows, wherein the row next to the second row is called a third row for convenience of description, and the arrangement sequence of each pixel structure in the third row is the same as that in the first row; the next row of the third row, referred to as the fourth row for convenience of description, includes the same arrangement order of the pixel structures as the second row; that is, the first row and the second row are also alternately arranged in the array substrate.
In the embodiment of the present invention, half of the pixel structures may exist in each row, each pixel structure includes two sub-pixel electrodes, which are respectively close to the data lines with the same polarity as the sub-pixel electrodes, and the TFTs corresponding to the sub-pixel electrodes are also disposed on the sub-pixel electrodes close to the data lines with the same polarity as the sub-pixel electrodes, so as to directly electrically connect the sub-pixel electrodes to the data lines, which may eliminate the need of electrically connecting the sub-pixel electrodes to the data lines through wires, thereby reducing the power consumption of the array substrate. In addition, the sub-pixel electrodes with the first polarity and the sub-pixel electrodes with the second polarity in each row or each column of the array substrate are alternately arranged, so that a dot inversion structure is realized, and the image display effect is provided.
Example two
The embodiment of the invention provides a display panel, which comprises any one of the array substrates provided by the first embodiment.
EXAMPLE III
The embodiment of the invention provides display equipment comprising any one display panel provided by the second embodiment.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. An array substrate is characterized in that a first row of the array substrate comprises a first pixel structure and a second pixel structure which are alternately arranged, the first pixel structure is positioned between a first data line and a second data line, the second pixel structure is positioned between the second data line and a third data line, and the first row is any row of the array substrate;
the first pixel structure comprises two first sub-pixel electrodes which are arranged in parallel, the first sub-pixel electrodes are close to corresponding target data lines, the polarities of the first sub-pixel electrodes and the corresponding target data lines are the same, TFTs corresponding to the first sub-pixel electrodes are located on one sides, close to the target data lines, of the first sub-pixel electrodes, and the first sub-pixel electrodes are electrically connected to the target data lines;
the second pixel structure comprises two second seed pixel electrodes which are arranged in parallel, the second seed pixel electrodes are far away from corresponding target data lines, the polarity of the second seed pixel electrodes is the same as that of the corresponding target data lines, the TFTs corresponding to the second seed pixel electrodes are positioned on one sides, close to the target data lines, of the second seed pixel electrodes, and the second seed pixel electrodes are electrically connected to the target data lines through wiring;
wherein the first pixel structure comprises a first TFT, a second TFT, a first sub-pixel electrode and a second sub-pixel electrode which are arranged in parallel, the polarity of the first data line and the polarity of the first sub-pixel electrode are both first polarities, the polarity of the second data line and the polarity of the second sub-pixel electrode are both second polarities, the first TFT is positioned on one side of the first sub-pixel electrode close to the first data line, and connects the first sub-pixel electrode to the first data line, the second TFT is positioned on one side of the second sub-pixel electrode close to the second data line and connects the second sub-pixel electrode to the second data line, the grid electrode of the first TFT is connected with a second grid line, the grid electrode of the second TFT is connected with a first grid line, and the first grid line and the second grid line are two rows of grid lines in the first row;
the second pixel structure comprises a third TFT, a fourth TFT, a third sub-pixel electrode and a fourth sub-pixel electrode which are arranged in parallel, the polarity of the fourth sub-pixel electrode is a second polarity, the polarity of the third data line and the polarity of the third sub-pixel electrode are both first polarities, the third TFT is positioned on one side of the third sub-pixel electrode close to the third data line, the third sub-pixel electrode is connected to the third data line through a first routing wire, the fourth TFT is positioned on one side of the fourth sub-pixel electrode close to the second data line, the fourth sub-pixel electrode is connected to the second data line through a second routing wire, the third TFT is connected with the first gate line, and the fourth TFT is connected with the second gate line;
two top corners of one side of the third sub-pixel electrode close to the third data line are provided with openings, and two top corners of one side of the fourth sub-pixel electrode close to the second data line are provided with openings; two groups of openings adjacent to the third sub-pixel electrode and the fourth sub-pixel electrode form two opening spaces; the third TFT is disposed in one of the open spaces, and the fourth TFT is disposed in the other open space.
2. The array substrate of claim 1, wherein an opening is formed at a top corner of the first sub-pixel electrode close to the first data line, and the first TFT is located at the opening.
3. The array substrate of claim 1, wherein an opening is formed at a top corner of the second sub-pixel electrode close to the second data line, and the second TFT is located at the opening.
4. The array substrate of claim 1,
a third pixel structure between the first data line and the second data line in a second row of the array substrate is the same as the second pixel structure, and comprises a fifth TFT and a sixth TFT, and a fifth sub-pixel electrode and a sixth sub-pixel electrode are arranged in parallel; the polarity of the fifth sub-pixel electrode is the same as that of the second data line, the polarity of the sixth sub-pixel electrode is the same as that of the first data line, and the second row is a next row adjacent to the first row;
the fifth TFT is positioned on one side of the fifth sub-pixel electrode close to the second data line, and the fifth sub-pixel electrode is connected to the second data line through a third routing line; the sixth TFT is located on one side, close to the first data line, of the sixth sub-pixel electrode, and the sixth sub-pixel electrode is connected to the first data line through a fourth routing line.
5. The array substrate of claim 4,
an opening is formed in the top corner of one side, close to the fifth sub-pixel electrode, of the first sub-pixel electrode, and the first TFT is located at the opening; or, an opening is arranged at the top corner of one side of the first sub-pixel electrode, which is far away from the fifth sub-pixel electrode, and the first TFT is located at the opening.
6. The array substrate of claim 1, wherein a fourth pixel structure located between the second data line and the third data line in a second row of the array substrate is the same as the first pixel structure, the second row being a next row adjacent to the first row;
the fourth pixel structure comprises a seventh TFT, an eighth TFT, and a seventh sub-pixel electrode and an eighth sub-pixel electrode which are arranged in parallel; the polarity of the seventh sub-pixel electrode is the same as that of the second data line, and the polarity of the eighth sub-pixel electrode is the same as that of the third data line;
the seventh TFT is positioned on one side of the seventh sub-pixel electrode close to the second data line and connects the seventh sub-pixel electrode to the second data line; the eighth TFT is positioned on one side of the eighth sub-pixel electrode close to the third data line and connects the eighth sub-pixel electrode to the third data line.
7. The array substrate of claim 6, wherein an opening is formed at a top corner of the seventh sub-pixel electrode close to the second data line, and the seventh TFT is located at the opening.
8. The array substrate of claim 6, wherein an opening is formed at a top corner of the eighth sub-pixel electrode close to the third data line, and the eighth TFT is located at the opening.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
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| CN101216650A (en) * | 2008-01-14 | 2008-07-09 | 京东方科技集团股份有限公司 | Liquid crystal display device array substrate and driving method thereof |
| CN101819366A (en) * | 2010-04-19 | 2010-09-01 | 友达光电股份有限公司 | Display panel |
| CN102879965A (en) * | 2012-10-12 | 2013-01-16 | 京东方科技集团股份有限公司 | Liquid crystal display panel and liquid crystal display device |
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| KR101359923B1 (en) * | 2007-02-28 | 2014-02-11 | 삼성디스플레이 주식회사 | Display device and method of drive for the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101216650A (en) * | 2008-01-14 | 2008-07-09 | 京东方科技集团股份有限公司 | Liquid crystal display device array substrate and driving method thereof |
| CN101819366A (en) * | 2010-04-19 | 2010-09-01 | 友达光电股份有限公司 | Display panel |
| CN102879965A (en) * | 2012-10-12 | 2013-01-16 | 京东方科技集团股份有限公司 | Liquid crystal display panel and liquid crystal display device |
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