CN106024805A - Array substrate, display panel and display equipment - Google Patents
Array substrate, display panel and display equipment Download PDFInfo
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- CN106024805A CN106024805A CN201610384273.XA CN201610384273A CN106024805A CN 106024805 A CN106024805 A CN 106024805A CN 201610384273 A CN201610384273 A CN 201610384273A CN 106024805 A CN106024805 A CN 106024805A
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- 239000000758 substrate Substances 0.000 title abstract 4
- 230000005611 electricity Effects 0.000 claims description 9
- 208000034699 Vitreous floaters Diseases 0.000 claims 2
- 239000010409 thin film Substances 0.000 abstract description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses an array substrate, a display panel and display equipment, and belongs to the display field. The first row of the array substrate comprises a first pixel structure and a second pixel structure which are arranged alternately; the first pixel structure comprises two first seed pixel electrodes which are arranged side by side; the first seed pixel electrodes are close the corresponding target data line; the TFT (thin film transistor) corresponding to the first seed pixel electrodes is positioned on one side, close to the target data line, of the first seed pixel electrodes; the first seed pixel electrodes are electrically connected to the target data line; the second pixel structure comprises two second seed pixel electrodes which are arranged side by side; the second seed pixel electrodes are far from the corresponding target data line; the TFT corresponding to the second seed pixel electrodes is positioned on one side, close to the target data line, of the second seed pixel electrodes; and the second seed pixel electrodes are electrically connected to the target data line through routing, so that the power consumption of the array substrate is lowered.
Description
Technical field
The present invention relates to display field, particularly to a kind of array base palte, display floater and display device.
Background technology
Array base palte is the important component part of liquid crystal display, and it is positioned at the backlight of liquid crystal display
And between liquid crystal layer.Array base palte turns to for the liquid crystal molecule controlled in liquid crystal layer, makes liquid crystal layer pass through the back of the body
The some light that light source sends, this light passed through can form picture on the screen of liquid crystal display.
Every a line of current array base palte includes the multiple dot structures being set up in parallel, and adjacent two pixels
The polarity of structure is different, is provided with the first data wire in the left side of this dot structure, and right side is provided with the second data wire,
The polarity of the first data wire and the second data wire is different, and wherein there is polarity and this pixel of a data lines
The polarity of structure is identical, it is assumed that be the first data wire.This dot structure includes a TFT (Thin Film
Transistor, thin film transistor (TFT)), the 2nd TFT, the first pixel electrode being set up in parallel and the second sub-pixel
Electrode；Oneth TFT is positioned at first pixel electrode side away from the first data wire, by cabling by first
Pixel electrode is connected to the first data wire, and the 2nd TFT is positioned at the second pixel electrode near the first data wire
Side, by cabling, the second pixel electrode is connected to the first data wire.
During realizing the present invention, inventor finds that prior art at least there is problems in that
It is connected on data wire owing to each pixel electrode in array base palte will rely on cabling, and each
Cabling forms electric capacity with the liquid crystal layer of liquid crystal display, can improve array base palte display power consumption.
Summary of the invention
In order to solve problem of the prior art, embodiments provide a kind of array base palte, display floater
And display device.Described technical scheme is as follows:
First aspect, it is provided that a kind of array base palte, the first row of described array base palte includes being arranged alternately
First dot structure and the second dot structure, described first dot structure is positioned at the first data wire and the second data
Between line, described second dot structure is between the second data wire and the 3rd data wire, and described the first row is
Any row of described array base palte；
Described first dot structure includes two the first pixel electrodes being set up in parallel, described first seed
Pixel electrode is near the target data line of its correspondence, the number of targets that the first pixel electrode described is corresponding
Polarity according to line is identical, and the TFT thin film transistor (TFT) that the first pixel electrode described is corresponding is positioned at described first
The first pixel electrode described, near the side of described target data line, is electrically connected to by sub pixel electrode
Described target data line；
Described second dot structure includes two the second seed pixel electrodes being set up in parallel, described second seed
Pixel electrode is away from the target data line of its correspondence, the number of targets that described second seed pixel electrode is corresponding
Polarity according to line is identical, and the TFT that described second seed pixel electrode is corresponding is positioned at described second seed pixel electricity
Extremely near the side of described target data line, by cabling, described second seed pixel electrode is electrically connected to institute
State target data line.
Optionally, described first dot structure include a TFT, the 2nd TFT, be set up in parallel first son
Pixel electrode and the second pixel electrode, the polarity of described first data wire and described first pixel electrode
Polarity is the first polarity, and the polarity of described second data wire is with the polarity of described second pixel electrode
Second polarity, a described TFT is positioned at described first pixel electrode side near described first data wire,
Being connected on described first data wire by described first pixel electrode, described 2nd TFT is positioned at described second
Described second pixel electrode, near the side of described second data wire, is connected to described by pixel electrode
Two data wires.
Optionally, described first pixel electrode is provided with opening at the side drift angle of described first data wire,
A described TFT is positioned at described opening part.
Optionally, described second pixel electrode is provided with opening at the side drift angle of described second data wire,
Described 2nd TFT is positioned at described opening part.
Optionally, described second dot structure include the 3rd TFT, the 4th TFT, be set up in parallel the 3rd son
Pixel electrode and the 4th pixel electrode, the polarity of described 4th pixel electrode is the second polarity, described
The polarity of three data wires is the first polarity, described 3rd TFT position with the polarity of described 3rd pixel electrode
In described 3rd pixel electrode near the side of described 3rd data wire, by the first cabling by the described 3rd
Pixel electrode is connected on described 3rd data wire, and described 4th TFT is positioned at described 4th pixel electrode
Near the side of described second data wire, described 4th pixel electrode is connected to described by the second cabling
Second data wire.
Optionally, in the second row of described array base palte, it is positioned at described first data wire and described second data
The 3rd dot structure between line is identical with described second dot structure, including the 5th TFT, the 6th TFT,
It is set up in parallel the 5th pixel electrode and the 6th pixel electrode；The polarity of described 5th pixel electrode and institute
The polarity stating the second data wire is identical, the polarity of described 6th sub-pixel and the polarity phase of described first data wire
With, the next line that described second behavior is adjacent with described the first row；
Described five TFT are positioned at described 5th pixel electrode near the side of described second data wire, by
Described 5th pixel electrode is connected on described second data wire by three cablings；Described six TFT are positioned at described
6th pixel electrode is near the side of described first data wire, by the 4th cabling by described 6th sub-pixel
Electrode is connected on described first data wire.
Optionally, described first pixel electrode is provided with at the side drift angle of described 5th pixel electrode
Opening, a described TFT is positioned at described opening part；Or, described first pixel electrode is away from described
Being provided with opening at the side drift angle of five pixel electrodes, a described TFT is positioned at described opening part.
Optionally, in the second row of described array base palte, it is positioned at described second data wire and described 3rd data
The 4th dot structure between line is identical with described first dot structure, described second behavior and described the first row
Adjacent next line；
Described 4th dot structure include the 7th TFT, the 8th TFT, be set up in parallel the 7th pixel electrode and
8th pixel electrode；The polarity of described 7th pixel electrode is identical with the polarity of described second data wire,
The polarity of described 8th sub-pixel is identical with the polarity of described 3rd data wire；
Described 7th TFT is positioned at described 7th pixel electrode near the side of described second data wire, by institute
State the 7th pixel electrode to be connected on described second data wire；Described eight TFT are positioned at described 8th sub-pixel
Described 8th pixel electrode, near the side of described 3rd data wire, is connected to described 3rd data by electrode
On line.
Optionally, described 7th pixel electrode is provided with opening at the side drift angle of described second data wire,
Described 7th TFT is positioned at described opening part.
Optionally, described 8th pixel electrode is provided with opening at the side drift angle of described 3rd data wire,
Described 8th TFT is positioned at described opening part.
Second aspect, it is provided that a kind of display floater, including described array base palte.
The third aspect, it is provided that a kind of display device, including display floater as mentioned.
The technical scheme that the embodiment of the present invention provides has the benefit that
Owing to every a line can exist the dot structure of half, two sub-pixel electricity that this dot structure includes
Pole, respectively close to the data wire identical with respective polarity, and TFT corresponding to this pixel electrode is also provided with
At this pixel electrode near the side of the polarity data wire identical with this pixel electrode, directly by this sub-picture
Element electrode is electrically connected to this data wire, so can save, by cabling, this pixel electrode is electrically connected to this
Data wire, thus reduce the power consumption of array base palte.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to be briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of array base-plate structure schematic diagram that the embodiment of the present invention one provides；
Fig. 2 is the another kind of array base-plate structure schematic diagram that the embodiment of the present invention one provides；
Fig. 3 is the another kind of array base-plate structure schematic diagram that the embodiment of the present invention one provides；
Fig. 4 is the another kind of array base-plate structure schematic diagram that the embodiment of the present invention one provides.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to the present invention
Embodiment is described in further detail.
Embodiment one
Seeing Fig. 1, embodiments provide a kind of array base palte, the first row of this array base palte includes handing over
For the first dot structure 1 and the second dot structure 2 arranged, the first dot structure 1 is positioned at the first data wire 3
With second between data wire 4, the second dot structure 2 between the second data wire 4 and the 3rd data wire 5,
Wherein, any row during the first row is array base palte.
First dot structure 1 includes two the first pixel electrodes being set up in parallel, the first sub-pixel electricity
Extremely near the target data line of its correspondence, the polarity of the target data line that the first pixel electrode is corresponding
Identical, the TFT that the first pixel electrode is corresponding is positioned at the first pixel electrode near this target data line
Side, the first pixel electrode is electrically connected to this target data line；
Second dot structure 2 includes two the second seed pixel electrodes being set up in parallel, second seed pixel electricity
Pole away from the target data line of its correspondence, the polarity of the target data line that second seed pixel electrode is corresponding
Identical, the TFT that second seed pixel electrode is corresponding is positioned at second seed pixel electrode near this target data line
Side, by cabling, second seed pixel electrode is electrically connected to this target data line.
Optionally, the first dot structure 1 include a TFT11, the 2nd TFT12, be set up in parallel first
Pixel electrode 13 and the second pixel electrode 14, the i.e. first pixel electrode 13 and the second pixel electrode
14 is all the first pixel electrode；The polarity of the first pixel electrode 13 and the second pixel electrode 14
Polarity is different, and the polarity of the first data wire 3 is the first polarity with the polarity of the first pixel electrode 13, the
The polarity of two data wires 4 is the second polarity with the polarity of the second pixel electrode 14.
Wherein, the first polarity can be positive pole, and the second polarity can be negative pole.Such as, as shown in Figure 1
Example, the polarity of the first data wire 3 is the most identical with the polarity of the first pixel electrode 13, is all positive pole；The
Two data wires 4 are identical with the polarity of the second pixel electrode 14, are all negative pole.
Wherein, a TFT11 is positioned at first pixel electrode 13 side near the first data wire 3, by
One pixel electrode 13 is connected on the first data wire 3, and the 2nd TFT12 is positioned at the second pixel electrode 14
Near the side of the second data wire 4, the second pixel electrode 14 is connected to the second data wire 4.
Further, this first row also includes two row grid lines, the respectively first grid line a and the second grid line b, the
One grid line a and the second grid line b is positioned at the first dot structure 1 that the first row includes and the second dot structure 2
Both sides.
Wherein, the first pixel electrode 13 is provided with opening at the side drift angle of the first data wire 3, and first
TFT11 is arranged on this opening part；The grid of the oneth TFT11 electrically connects with a line grid line in this two row grid line；
First end and first data wire 3 of the oneth TFT11 electrically connect, and the second end and the first pixel electrode 13 are electrically connected
Connect.
Optionally, seeing Fig. 1, the first pixel electrode 13 is near the first data wire 3 and the second grid line b
Being provided with opening at the drift angle of side, a TFT11 can be arranged on this opening part, the grid of a TFT11 with
Second grid line b electrical connection；Or, seeing Fig. 2, the first pixel electrode 13 is near the first data wire 3 He
Being provided with opening at the side drift angle of the first grid line a, a TFT11 can be arranged on this opening part, and first
The grid of TFT11 and the first grid line a electrical connection.
Second pixel electrode 14 is provided with opening at the side drift angle of the second data wire 4, the 2nd TFT12
It is arranged on this opening part；The grid of the 2nd TFT12 electrically connects with another row grid line in this two row grid line, the
First end and second data wire 4 of two TFT12 electrically connect, and the second end and the second pixel electrode 14 electrically connect.
Optionally, seeing Fig. 1, the second pixel electrode 14 is near the second data wire 4 and the first grid line a
Be provided with opening at the drift angle of side, the 2nd TFT12 can be arranged on the grid of this opening part and the 2nd TFT12 with
First grid line a electrical connection；Or, seeing Fig. 2, the second pixel electrode 14 is near the second data wire 4 He
Being provided with opening at the side drift angle of the second grid line b, the 2nd TFT12 can be arranged on this opening part and second
The grid of TFT12 and the second grid line b electrical connection.
Optionally, the second dot structure 2 include the 3rd TFT21, the 4th TFT22, be set up in parallel the 3rd
Pixel electrode 23 and the 4th pixel electrode 24, the i.e. the 3rd pixel electrode 23 and the 4th pixel electrode
24 is second seed pixel electrode, the polarity of the 3rd pixel electrode 23 and the pole of the 4th pixel electrode 24
Property different, the polarity of the second data wire 4 is identical with the polarity of the 4th pixel electrode 24, is the second polarity,
The polarity of the 3rd data wire 5 is identical with the polarity of the 3rd pixel electrode 23, is the first polarity；Such as,
Example as shown in Figure 1, the polarity of the second data wire 4 and the polarity of the 4th pixel electrode 24 are negative pole,
The polarity of the 3rd data wire 5 and the polarity of the 3rd pixel electrode 23 are positive pole.
Wherein, seeing Fig. 1 and 2, the 3rd TFT21 is positioned at the 3rd pixel electrode 23 near the 3rd data wire
The side of 5, is connected to the 3rd pixel electrode 23 on the 3rd data wire 5 by the first cabling 25, the 4th
TFT22 is positioned at the 4th pixel electrode 24 side near the second data wire 4, will by the second cabling 26
4th pixel electrode 24 is connected to the second data wire 4.
Wherein, the 3rd pixel electrode 23 is equipped with opening at two drift angles of the 3rd data wire 5 side,
4th pixel electrode 24 is also equipped with opening at two drift angles of the second data wire 4 side；3rd son
Pixel electrode 23 and adjacent two groups of openings, two open spaces of composition of the 4th pixel electrode 24；3rd
TFT21 is disposed therein in an open space, and in its grid and the first grid line a and the second grid line b
One grid line electrical connection, first end of the 3rd TFT21 is electrically connected with the 3rd data wire 5 by the first cabling 25,
Second end and the 3rd pixel electrode 23 electrically connect.4th TFT22 is arranged in another open space, and
Another grid line electrical connection in its grid and the first grid line a and the second grid line b, first end of the 4th TFT22
Being electrically connected with the second data wire 4 by the second cabling 26, the second end and the 4th pixel electrode 24 electrically connect.
Such as, example as shown in Figure 1, the 3rd TFT21 is positioned close to the open space of the first grid line a
In, the grid of the 3rd TFT21 can electrically connect with the first grid line a, and the 4th TFT22 can be positioned close to
In another open space of second grid line b, the grid of the 4th TFT22 and the second grid line b electrical connection；Or,
Example as shown in Figure 2, the 3rd TFT21 is positioned close in the side open space of the second grid line b, the
The grid of three TFT21 and the second grid line b electrical connection, the 4th TFT22 is positioned close to the another of the first grid line a
In one open space, the grid of the 4th TFT22 and the first grid line a electrical connection.
Optionally, in the present embodiment, the polarity of the polarity Statistical with the 3rd 5 of the first data wire 3 is identical,
Being all the first polarity, the polarity of the first data wire 3 is different from the polarity of the second data wire 4, the second data wire 4
Polarity be the second polarity.Wherein, the polarity of the first data wire 3 and the polarity of the 3rd data wire 5 can be
Positive pole, the polarity of the second data wire 4 can be negative pole；Or, the polarity of the first data wire 3 and the 3rd number
Can be negative pole according to the polarity of line 5, the polarity of the second data wire 4 can be positive pole.Such as, such as Fig. 1 institute
The example shown, the polarity of the first data wire 4 and the 3rd data wire 5 is positive pole, the polarity of the second data wire
For negative pole.
Wherein, see Fig. 3 or 4, it should be understood that the first row can include multiple first dot structure
1 and multiple second dot structure 2, the plurality of first dot structure 1 and the second dot structure 2 are arranged alternately.
Due to the TFT11 in each first dot structure 1 and the 2nd TFT12 all with the most adjacent data wire
It is joined directly together, so saves cabling at two, eliminate the power consumption of cabling at two, thus reduce array base palte
Power consumption.
Wherein, the adjacent rows at array base palte includes the first dot structure and the second dot structure alternately
The order arranged is different.For next line adjacent with the first row in array base palte, for convenience of description, will
This next line is referred to as the second row.
Optionally, referring also to Fig. 1, the second row of array base palte is positioned at the first data wire 3 and the second data
Dot structure between line 4 is the 3rd dot structure 6.
3rd dot structure 6 includes the 5th TFT61, the 6th TFT62, is set up in parallel the 5th pixel electrode
63 and the 6th pixel electrode 64；The polarity phase of the polarity of the 5th pixel electrode 63 and the second data wire 4
With, it being the second polarity, the polarity of the 6th pixel electrode 64 is identical with the polarity of the first data wire 3, all
It is the first polarity；Such as, in the example depicted in figure 1, the polarity of the 5th pixel electrode 63 and the second number
Being all negative pole according to the polarity of line 4, the polarity of the 6th pixel electrode 64 with the polarity of the first data wire 3 is all
Positive pole.
5th TFT61 is positioned at the 5th pixel electrode 63 side near the second data wire 4, walks by the 3rd
5th pixel electrode 63 is connected on the second data wire 4 by line 65；6th TFT62 is positioned at the 6th sub-picture
Element electrode 64 is near the side of the first data wire 3, by the 4th cabling 66 by the 6th pixel electrode 64 even
It is connected on the first data wire 3.
Further, this second row also includes two row grid lines, the respectively the 3rd grid line c and the 4th grid line d,
Three grid line c and the 4th grid line d are positioned at the both sides of the 3rd dot structure 6 that the second row includes.
Wherein, in the 3rd sub-pixel structure 6, the 5th pixel electrode 63 is near the second data wire 4 side
Two drift angles at be equipped with opening, the 6th pixel electrode 64 is near two tops of the first data wire 3 side
Also opening it is equipped with at angle；5th pixel electrode 63 and the adjacent two groups of openings of the 6th pixel electrode 64
Form two open spaces；5th TFT61 is disposed therein in an open space, and its grid and the 3rd
A grid line electrical connection in grid line c and the 4th grid line d, such as, example as shown in the figures 1 and 2, the 5th
The grid of TFT61 and the 3rd grid line c electrical connection；First end of the 5th TFT61 is by the 3rd cabling 65 and the
Two data wires 4 electrically connect, and the second end and the 5th pixel electrode 63 electrically connect.6th TFT62 is arranged on separately
In one open space, and another grid line electrical connection in its grid and the 3rd grid line c and the 4th grid line d,
Such as, example as shown in the figures 1 and 2, the grid of the 6th TFT64 and the 4th grid line d electrical connection；6th
First end of TFT64 is electrically connected with the first data wire 3 by the 4th cabling 66, the second end and the 6th sub-pixel
Electrode 64 electrically connects.
Optionally, in the second row of array base palte between the second data wire 4 and the 3rd data wire 5
Dot structure is referred to as the 4th dot structure 7；
4th dot structure 7 includes the 7th TFT71, the 8th TFT72, is set up in parallel the 7th pixel electrode
73 and the 8th pixel electrode 74；The polarity phase of the polarity of the 7th pixel electrode 71 and the second data wire 2
With, it is all the second polarity, the polarity of the 8th pixel electrode 74 is identical with the polarity of the 3rd data wire 5, all
It is the first polarity；Such as, in example as shown in Figure 1, the polarity and second of the 7th pixel electrode 73
The polarity of data wire 4 is identical, is all negative pole, the polarity of the 8th pixel electrode 74 and the 3rd data wire 5
Polarity is identical, is all positive pole.
Optionally, the 7th TFT71 is positioned at the 7th pixel electrode 73 side near the second data wire 4, will
7th pixel electrode 73 is connected on the second data wire 4；8th TFT72 is positioned at the 8th pixel electrode
8th pixel electrode 74, near the side of the 3rd data wire 5, is connected on the 3rd data wire 5 by 74.
Wherein, the 7th pixel electrode 73 is provided with opening at the side drift angle of the second data wire 4, and the 7th
TFT71 is arranged on this opening part；In the grid of the 7th TFT71 and the 3rd grid line c and the 4th grid line d one
Row grid line electrically connects, and example as shown in Figure 1, the 7th TFT71 is positioned close to the opening of the 4th grid line d
In space, the grid of the 7th TFT71 and the 4th grid line d electrical connection.First end and second of the 7th TFT71
Data wire 4 electrically connects, and the second end and the 7th pixel electrode 73 electrically connect.
8th pixel electrode 74 is provided with opening, the 8th TFT72 at the side drift angle of the 3rd data wire 5
It is arranged on this opening part；Another row grid in the grid of the 8th TFT72 and the 3rd grid line c and the 4th grid line d
Line electrically connects, and example as shown in Figure 1, the 8th TFT72 is positioned close to another opening of the 3rd grid line c
In space, the grid of the 8th TFT72 and the 3rd grid line c electrical connection, first end and the 3rd of the 8th TFT72
Data wire 5 electrically connects, and the second end and the 8th pixel electrode 74 electrically connect.
Wherein it is desired to explanation: see Fig. 1 to 4, in any row the pixel electrode of the first polarity and
The pixel electrode of the second polarity is arranged alternately, such as, in the first row, the first pixel electrode
Polarity is the first polarity, and the polarity of the second pixel electrode is the second polarity, the polarity of the 3rd pixel electrode
First polarity, the polarity of the 4th pixel electrode is the second polarity；Sub-pixel electricity in either rank the first polarity
The pixel electrode of pole and the second polarity is also arranged alternately, such as, at the first data wire 3 and the second number
Being the first polarity according to the polarity of the first pixel electrode between line 4, the polarity of the 5th pixel electrode is
Two polarity；So the sub-picture of the first polarity in the often row of array base palte that provides of the embodiment of the present invention or in each column
The pixel electrode of element electrode and the second polarity is alternately arranged, it is achieved thereby that the structure of some reversion, it is provided that
The effect that image quality shows.
Optionally, such as Fig. 3 and 4, it should be understood that the second row can include multiple 3rd dot structure
6 and multiple 4th dot structure 7, the plurality of 3rd dot structure 6 and the 4th dot structure 7 are arranged alternately.
Due to the 7th TFT71 in each 4th dot structure 7 and the 8th TFT72 all with the most adjacent data wire
It is joined directly together, so saves cabling at two, eliminate the power consumption of cabling at two, thus reduce array base palte
Power consumption.
Wherein, array base palte includes multirow, and at the next line of the second row, for convenience of description, referred to as
Three row, arranging of each dot structure that the third line includes is the most identical with the first row；The next line of the third line,
For convenience of description, referred to as fourth line, arranging sequentially and the second row phase of each dot structure that fourth line includes
With；I.e. in array base palte, the first row and second is the most also arranged alternately.
In embodiments of the present invention, can there is the dot structure of half in every a line, this dot structure includes
Two pixel electrodes, respectively close to the data wire identical with respective polarity, and this pixel electrode pair
The TFT answered is also disposed at the close data identical with this pixel electrode polarity of this pixel electrode, directly will
This pixel electrode is electrically connected to this data wire, so can save and is electrically connected by this pixel electrode by cabling
It is connected to this data wire, thus reduces the power consumption of array base palte.It addition, array base palte often row in or each column
In the pixel electrode of the first polarity and the pixel electrode of the second polarity be alternately arranged, it is achieved thereby that point
The structure of reversion, it is provided that the effect that image quality shows.
Embodiment two
A kind of display floater, any one array base palte provided including embodiment one are be provided.
Embodiment three
A kind of display device, any one display floater provided including embodiment two are be provided.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all the present invention's
Within spirit and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention's
Within protection domain.
Claims (12)
1. an array base palte, it is characterised in that the first row of described array base palte includes be arranged alternately
One dot structure and the second dot structure, described first dot structure is positioned at the first data wire and the second data wire
Between, described second dot structure is between the second data wire and the 3rd data wire, and described the first row is institute
State any row of array base palte；
Described first dot structure includes two the first pixel electrodes being set up in parallel, described first seed
Pixel electrode is near the target data line of its correspondence, the number of targets that the first pixel electrode described is corresponding
Polarity according to line is identical, and the TFT that the first pixel electrode described is corresponding is positioned at the first sub-pixel electricity described
Extremely near the side of described target data line, the first pixel electrode described is electrically connected to described number of targets
According to line；
Described second dot structure includes two the second seed pixel electrodes being set up in parallel, described second seed
Pixel electrode is away from the target data line of its correspondence, the number of targets that described second seed pixel electrode is corresponding
Polarity according to line is identical, and the TFT that described second seed pixel electrode is corresponding is positioned at described second seed pixel electricity
Extremely near the side of described target data line, by cabling, described second seed pixel electrode is electrically connected to institute
State target data line.
2. array base palte as claimed in claim 1, it is characterised in that
Described first dot structure includes a TFT, the 2nd TFT, the first pixel electrode of being set up in parallel
With the second pixel electrode, the polarity of described first data wire is with the polarity of described first pixel electrode
First polarity, the polarity of described second data wire is the second polarity with the polarity of described second pixel electrode,
A described TFT is positioned at described first pixel electrode side near described first data wire, by described
One pixel electrode is connected on described first data wire, and described 2nd TFT is positioned at described second sub-pixel electricity
Extremely near the side of described second data wire, described second pixel electrode is connected to described second data wire.
3. array base palte as claimed in claim 2, it is characterised in that described first pixel electrode is close
Being provided with opening at the side drift angle of described first data wire, a described TFT is positioned at described opening part.
4. array base palte as claimed in claim 2, it is characterised in that described second pixel electrode is close
Being provided with opening at the side drift angle of described second data wire, described 2nd TFT is positioned at described opening part.
5. array base palte as claimed in claim 1, it is characterised in that
Described second dot structure includes the 3rd TFT, the 4th TFT, the 3rd pixel electrode that is set up in parallel
With the 4th pixel electrode, the polarity of described 4th pixel electrode is the second polarity, described 3rd data wire
The polarity of polarity and described 3rd pixel electrode be the first polarity, described 3rd TFT is positioned at described the
Three pixel electrodes are near the side of described 3rd data wire, by the first cabling by described 3rd sub-pixel electricity
Pole is connected on described 3rd data wire, and described 4th TFT is positioned at described 4th pixel electrode near described
The side of the second data wire, is connected to described second data by the second cabling by described 4th pixel electrode
Line.
6. array base palte as claimed in claim 1, it is characterised in that
In the second row of described array base palte between described first data wire and described second data wire
3rd dot structure is identical with described second dot structure, including the 5th TFT, the 6th TFT, is set up in parallel
5th pixel electrode and the 6th pixel electrode；The polarity of described 5th pixel electrode and described second number
Polarity according to line is identical, and the polarity of described 6th sub-pixel is identical with the polarity of described first data wire, described
The next line that second behavior is adjacent with described the first row；
Described five TFT are positioned at described 5th pixel electrode near the side of described second data wire, by
Described 5th pixel electrode is connected on described second data wire by three cablings；Described six TFT are positioned at described
6th pixel electrode is near the side of described first data wire, by the 4th cabling by described 6th sub-pixel
Electrode is connected on described first data wire.
7. array base palte as claimed in claim 6, it is characterised in that
Described first pixel electrode is provided with opening at the side drift angle of described 5th pixel electrode, institute
State a TFT and be positioned at described opening part；Or, described first pixel electrode is away from described 5th sub-pixel
Being provided with opening at the side drift angle of electrode, a described TFT is positioned at described opening part.
8. array base palte as claimed in claim 1, it is characterised in that at the second row of described array base palte
In the 4th dot structure between described second data wire and described 3rd data wire and described first pixel
Structure is identical, the next line that described second behavior is adjacent with described the first row；
Described 4th dot structure include the 7th TFT, the 8th TFT, be set up in parallel the 7th pixel electrode and
8th pixel electrode；The polarity of described 7th pixel electrode is identical with the polarity of described second data wire,
The polarity of described 8th sub-pixel is identical with the polarity of described 3rd data wire；
Described 7th TFT is positioned at described 7th pixel electrode near the side of described second data wire, by institute
State the 7th pixel electrode to be connected on described second data wire；Described eight TFT are positioned at described 8th sub-pixel
Described 8th pixel electrode, near the side of described 3rd data wire, is connected to described 3rd data by electrode
On line.
9. array base palte as claimed in claim 8, it is characterised in that described 7th pixel electrode is close
Being provided with opening at the side drift angle of described second data wire, described 7th TFT is positioned at described opening part.
10. array base palte as claimed in claim 8, it is characterised in that described 8th pixel electrode leans on
Being provided with opening at the side drift angle of the most described 3rd data wire, described 8th TFT is positioned at described opening part.
11. 1 kinds of display floaters, it is characterised in that include such as claim 1 to 10 any one claim
Described array base palte.
12. 1 kinds of display devices, it is characterised in that include display floater as claimed in claim 11.
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| CN101114096A (en) * | 2006-07-25 | 2008-01-30 | 三星电子株式会社 | Liquid crystal display |
| CN101216650A (en) * | 2008-01-14 | 2008-07-09 | 京东方科技集团股份有限公司 | Liquid crystal display device array substrate and driving method thereof |
| US20080204392A1 (en) * | 2007-02-28 | 2008-08-28 | Han Jong-Heon | Display device and driving method therefor |
| CN101819366A (en) * | 2010-04-19 | 2010-09-01 | 友达光电股份有限公司 | Display panel |
| CN102879965A (en) * | 2012-10-12 | 2013-01-16 | 京东方科技集团股份有限公司 | Liquid crystal display panel and liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101114096A (en) * | 2006-07-25 | 2008-01-30 | 三星电子株式会社 | Liquid crystal display |
| US20080204392A1 (en) * | 2007-02-28 | 2008-08-28 | Han Jong-Heon | Display device and driving method therefor |
| CN101216650A (en) * | 2008-01-14 | 2008-07-09 | 京东方科技集团股份有限公司 | Liquid crystal display device array substrate and driving method thereof |
| CN101819366A (en) * | 2010-04-19 | 2010-09-01 | 友达光电股份有限公司 | Display panel |
| CN102879965A (en) * | 2012-10-12 | 2013-01-16 | 京东方科技集团股份有限公司 | Liquid crystal display panel and liquid crystal display device |
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