CN106024657A - Embedded package structure - Google Patents

Embedded package structure Download PDF

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Publication number
CN106024657A
CN106024657A CN201610465118.0A CN201610465118A CN106024657A CN 106024657 A CN106024657 A CN 106024657A CN 201610465118 A CN201610465118 A CN 201610465118A CN 106024657 A CN106024657 A CN 106024657A
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CN
China
Prior art keywords
described
metal
wafer
metal pad
layer
Prior art date
Application number
CN201610465118.0A
Other languages
Chinese (zh)
Inventor
高国华
Original Assignee
南通富士通微电子股份有限公司
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Priority to CN201610465118.0A priority Critical patent/CN106024657A/en
Publication of CN106024657A publication Critical patent/CN106024657A/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02317Manufacturing methods of the redistribution layers by local deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view

Abstract

The invention discloses an embedded package structure, which comprises a substrate, wherein the substrate is used for packaging a wafer; a cavity for embedding of the wafer is arranged in the substrate; a first metal bonding pad is arranged at the lower part of the cavity; the first metal bonding pad communicates with the wafer through a first metal through hole; a copper foil is arranged at the upper part of the cavity; the copper foil communicates with the first metal bonding pad through a second metal through hole; a second metal bonding pad is arranged at the upper part of the copper foil and communicates with the copper foil through a third metal through hole; and the first metal through hole, the first metal bonding pad, the second metal through hole, the copper foil, the third metal through hole and the second metal bonding pad are fixedly arranged in the substrate through lamination. The embedded package structure disclosed by the invention is lighter, thinner and more compact.

Description

A kind of embedded packaging structure

Technical field

The disclosure relates generally to semiconductor technology, is specifically related to wafer level packaging, particularly relates to the most embedding Enter formula encapsulating structure, and Wiring technique and wire bond structure again.

Background technology

The more product of wafer-level packaging uses the connected mode that metal connects up again, part to use copper Post Wiring technique again, but the cost that connects up again of copper post and auxiliary process difficulty.

In semiconductor industry, routing technology is widely used at chip or substrate equivalent-load part On, its weld pad being generally electrically connected with on this chip by a plurality of bonding wire and the connection pad on this substrate. And along with the demand usefulness of electronic product is the highest, the electrical signals of each bonding wire is each other Noise jamming is the most, and part electrical signals can efficiency decline or distortion in transmission.

Along with the extensive application of portable type electronic product, the increasingly desirable miniaturization of semiconductor device and Large Copacity.In order to realize miniaturization and Large Copacity, substantial amounts of semiconductor chip needs to be arranged on half In conductor packaging part, and semiconductor package part needs light, thin and compact.

Summary of the invention

In view of drawbacks described above of the prior art or deficiency, it is desirable to provide one Wiring technique again, And a kind of wire bond structure and a kind of embedded packaging structure.

First aspect according to the disclosure, it is provided that one Wiring technique again, including

Wafer is formed cushion;

Described cushion is formed titanium inculating crystal layer;

Described titanium inculating crystal layer is formed metallic film;

Described metallic film is paved with photoresist;

The photoresist of inactive area on stripping metal thin film, described inactive area is corresponding to for non- The region being electrically connected with;

Erode metallic film and the titanium inculating crystal layer of inactive area corresponding position;And

Soak and peel off remaining photoresist.

Preferably, before wafer forms cushion, also include:

Chip metal pad and passivation layer it is provided with on described crystal column surface;Described chip metal welds Dish is arranged between described crystal column surface and described passivation layer, and described passivation layer covers described wafer Described chip metal pad is also exposed in surface;

Form described cushion in described passivation layer surface, and described cushion exposes described crystalline substance Circle metal pad.

Preferably, described cushion is polyimides glue-line, and described passivation layer is silicon nitride layer.

Preferably, the described titanium inculating crystal layer that formed on described cushion includes:

At described polyimides film surface sputter titanium inculating crystal layer.

Preferably, the thickness of described titanium inculating crystal layer is 100nm.

Preferably, the described metallic film that formed on described titanium inculating crystal layer includes:

At described titanium seed crystal surface sputter or metal film.

Preferably, the thickness of described metallic film is more than 1 μm.

Preferably, on described stripping metal thin film, the photoresist of inactive area includes:

By exposure or developing process, the photoresist of inactive area on stripping metal thin film.

Preferably, metallic film and the titanium inculating crystal layer of inactive area corresponding position are eroded described in Including:

Use aluminum corrosive liquid first to be corroded by the metallic film of inactive area corresponding position, then will expose Titanium inculating crystal layer corrosion.

Preferably, described metallic film is aluminum metal thin film.

Second aspect according to the disclosure, it is provided that a kind of wire bond structure, described structure includes:

Framework, described framework is provided with at least one solder joint;

Wafer, described wafer is arranged on said frame, and described wafer is provided with metal film layer; And

At least one connecting line, described connecting line is arranged between described framework and described wafer, And constitute the electric connection of described solder joint and described metal film layer.

Preferably, the upper surface upstream sequence of described wafer is provided with titanium inculating crystal layer and described metal foil Film layer.

Preferably, described wafer is provided with chip metal pad, and described chip metal pad sets Having passivation layer, described passivation layer covers the upper surface of described wafer and exposes the weldering of described chip metal Dish, described titanium inculating crystal layer is arranged on described passivation layer.

Preferably, cushion, described buffering it are provided with between described passivation layer and described titanium inculating crystal layer Layer covers the upper surface of described passivation layer and exposes described chip metal pad.

Preferably, described cushion is polyimides glue-line.

Preferably, described passivation layer is silicon nitride layer.

Preferably, described connecting line is bonding line.

Preferably, described metallic film is aluminum metal thin film.

Preferably, the thickness of described aluminum metal thin film is more than 1 μm.

The third aspect according to the disclosure, it is provided that a kind of embedded packaging structure, described structure Including:

Substrate, is configured to encapsulate wafer, is provided with and is available for what described wafer embedded in described substrate Cavity;

The lower section of described cavity is provided with the first metal pad, described first metal pad and described crystalline substance Connected by the first metal throuth hole between circle;Described cavity be arranged over Copper Foil, described Copper Foil Being connected by the second metal throuth hole with between described first metal pad, the top of described Copper Foil sets There is the second metal pad, led to by the 3rd metal between described second metal pad and described Copper Foil Hole connects;Described first metal throuth hole, described first metal pad, described second metal throuth hole, Described Copper Foil, described 3rd metal throuth hole and described second metal pad are fixedly installed by lamination In described substrate.

Preferably, described first metal throuth hole, described first metal pad, described second metal Through hole, described Copper Foil, described 3rd metal throuth hole and described second metal pad are pressed together on respectively In respective resin material, then it is fixed in described substrate by each resin material layer pressing.

Preferably, also including wafer, described wafer upside-down mounting is also embedded in described cavity;And Wire structures again, described wire structures again is electrically connected with described wafer and described substrate.

Preferably, described wire structures again is electrically connected with described wafer and described first metal pad.

Preferably, then wire structures includes titanium inculating crystal layer and metal film layer, described titanium inculating crystal layer Being arranged on described wafer, described metal film layer is electrically connected with described first metal pad.

Preferably, described wafer is provided with chip metal pad, and described chip metal pad sets Having passivation layer, described passivation layer covers the upper surface of described wafer and exposes the weldering of described chip metal Dish, described titanium inculating crystal layer is arranged on described passivation layer.

Preferably, cushion, described buffering it are provided with between described passivation layer and described titanium inculating crystal layer Layer also exposes described chip metal pad.

Preferably, described cushion is polyimides glue-line.

Preferably, described passivation layer is silicon nitride layer.

Preferably, described metallic film is aluminum metal thin film, and the thickness of described aluminum metal thin film is More than 1 μm.

According to the Wiring technique again of the application, owing to using aluminum metal thin film, effect dropped cost and Technology difficulty.

According to the wire bond structure of the application, due to routing between metal film layer and solder joint, real Now electrically connect, therefore enable electrical signals keep high efficiency, and undistorted.

According to the application, owing to devising Embedded version, hence in so that packaging part knot On structure lighter, thin and compact.

Accompanying drawing explanation

By reading retouching in detail with reference to made non-limiting example is made of the following drawings Stating, other features, purpose and advantage will become more apparent upon:

Fig. 1 is according to the flow chart of the Wiring technique again of the embodiment of the present application;

Fig. 2 is according to the structural representation obtained after the S10 of Wiring technique again of the embodiment of the present application;

Fig. 3 is according to the structural representation obtained after the S20 of Wiring technique again of the embodiment of the present application;

Fig. 4 is according to the structural representation obtained after the S30 of Wiring technique again of the embodiment of the present application;

Fig. 5 is according to the structural representation obtained after the S50 of Wiring technique again of the embodiment of the present application;

Fig. 6 is according to the structural representation obtained after the S60 of Wiring technique again of the embodiment of the present application;

Fig. 7 is according to the structural representation obtained after the S70 of Wiring technique again of the embodiment of the present application;

Fig. 8 is according to the structural representation obtained after the S11 of Wiring technique again of the embodiment of the present application;

Fig. 9 is according to the wire bond structure schematic diagram of the embodiment of the present application;And

Figure 10 is according to the schematic diagram of the embedded packaging structure of the embodiment of the present application.

Detailed description of the invention

With embodiment, the application is described in further detail below in conjunction with the accompanying drawings.It is appreciated that , specific embodiment described herein is used only for explaining related invention, rather than to this Bright restriction.It also should be noted that, for the ease of describe, accompanying drawing illustrate only with The part that invention is relevant.

It should be noted that in the case of not conflicting, the embodiment in the application and embodiment In feature can be mutually combined.Describe this below with reference to the accompanying drawings and in conjunction with the embodiments in detail Application.

Refer to Fig. 1, it illustrates the flow chart of the Wiring technique again of the embodiment of the present application.As Shown in figure, then Wiring technique includes:

S10: form cushion 201 on wafer 101, form structure as shown in Figure 2, preferably Ground cushion 201 is polyimides glue-line.

S20: forming titanium inculating crystal layer 301 on the buffer layer 201, titanium inculating crystal layer 301 will be located in delaying The region rushed in layer 201 all covers, and forms structure as shown in Figure 3.

S30: form metallic film 302 on titanium inculating crystal layer 301, form structure as shown in Figure 4. Preferably, metallic film 302 is aluminum metal thin film.

S40: be paved with photoresist 303 on metallic film.

S50: the photoresist 303 of inactive area on stripping metal thin film 302, inactive area is corresponding In the region for non-electric connection, form structure as shown in Figure 5.

S60: erode metallic film 302 and the titanium inculating crystal layer 301 of inactive area corresponding position, Form structure as shown in Figure 6.

S70: soak and peel off remaining photoresist 303, form structure as shown in Figure 7, make metal Thin film without connecting, forms wire structures again for the effective coverage of non-electric connection.

Use the Wiring technique again of present embodiment, form cushion, by the structure of crystal column surface Planarization, effectively discharges stress.And, in the effective coverage for non-electric connection, aluminum is set Metallic film 302, and by aluminum metal thin film 302 and extraneous routing, it is achieved it is electrically connected with. The area of aluminum metal thin film 302 is relatively big, more in order to routing and the position realizing being electrically connected with, Electrical signals can stably be transmitted.Thus so that electrical signals can keep high efficiency And it is undistorted.

Further preferably embodiment, before step S10, crystal column surface is provided with wafer Metal pad and passivation layer, it is preferable that passivation layer is silicon nitride layer.Chip metal pad 102 Being arranged between wafer 101 surface and passivation layer 103, passivation layer 103 covers wafer 101 table Chip metal pad 102 is also exposed in face;Cushion 201 is formed on passivation layer 103 surface, and Cushion 201 exposes chip metal pad 102, as shown in Figure 8 structure.So, in nitridation Form polyimides glue-line on silicon layer, the surface smoothness of nitride structure can be increased, effectively Release stress, it is therefore prevented that because fragile material ruptures, the bottom electrical leakage problems caused.

Further preferably embodiment, step S20, specifically include: at polyimides glue-line 201 surface sputter titanium inculating crystal layers 301, wherein titanium inculating crystal layer 301 cushion to be covered in Chip metal pad 102 also to be covered by the surface of 201, forms structure shown in Fig. 3.Preferably Ground, the thickness of titanium inculating crystal layer 301 is 100nm.

Further preferably embodiment, step S30, specifically include: at titanium inculating crystal layer 301 Surface sputter or metal film 302, form structure as shown in Figure 4.Preferably, metal The thickness of thin film 302 is more than 1 μm.

Further preferably embodiment, step S40, specifically include: by exposure or development work Skill, the photoresist 303 of inactive area on stripping metal thin film 302.

Further preferably embodiment, step S50, specifically include: peeling off dead space After the photoresist 303 in territory, use aluminum corrosive liquid first by the metallic film of inactive area corresponding position 302 corrosion, metallic film 302 exposes titanium inculating crystal layer 301, then will expose titanium seed crystal after being corroded Layer 301 corrosion.

Using the Wiring technique again of the application, relatively low technology difficulty is relatively low, and utilizes aluminium gold Belong to thin film and realize wire structures again, aluminum metal low price, the one-tenth connected up again can be effectively reduced This.

Refer to Fig. 9, it illustrates the technical scheme of the wire bond structure of the embodiment of the present application.As Shown in Fig. 9, wire bond structure includes: framework 401, wafer and connecting line 402, wafer is arranged on On framework 401, wafer is provided with metallic film 302.Its middle frame 401 is provided with at least one Individual solder joint, and connecting line 402 also at least.Further, connecting line 402 is arranged at framework Between 401 and wafer, and constitute the electric connection of solder joint and metallic film 302, i.e. complete Routing between solder joint and metallic film 302.The area of metallic film 302 is relatively big, permissible It is used for more, in such manner, it is possible to make electrically to believe with solder joint routing and the position realizing being electrically connected with Number can stably between wafer and framework 401 transmit.Thus so that electrical signals can Keep high efficiency and undistorted.Preferably, metallic film 302 is aluminum metal thin layer, aluminium Material is cheap, reduces production cost;It is further preferred that the thickness of metallic film 302 is 1 μm Above.Preferably, connecting line 402 is bonding line, has electric, the heat conduction of excellence, machinery Performance and chemical stability.

Further preferably embodiment, the upper surface of wafer 101 is provided with titanium inculating crystal layer 301, Metallic film 302 is on titanium inculating crystal layer 301.Titanium inculating crystal layer can promote that wafer is formed, thus Can provide more can be with the effective coverage of extraneous routing.

Further preferably embodiment, wafer 101 is provided with chip metal pad 102, gold Belonging to pad and be arranged over passivation layer 103, passivation layer 103 covers the upper surface of wafer 101 and reveals Go out chip metal pad 102, it is preferable that passivation layer 103 is silicon nitride layer.Passivation layer 103 Covering the upper surface of wafer 101, titanium inculating crystal layer 301 is arranged on passivation layer 103.Passivation layer Be equivalent to the protective layer of wafer, prevent wafer to be corroded.

Further preferably embodiment, is provided with slow between passivation layer 103 and titanium inculating crystal layer 301 Rushing layer 201, cushion 201 covers the upper surface of passivation layer 103 and exposes chip metal pad 102, chip metal also to be welded by the surface of titanium inculating crystal layer 301 cushion to be covered in 201 Dish 102 covers, it is preferable that cushion 201 is polyimides glue-line.Cushion can be by crystalline substance The structure planarization of circular surfaces, effectively discharges stress.

Refer to Figure 10, it illustrates the skill of the embedded packaging structure according to the embodiment of the present application Art scheme.As shown in Figure 10, a kind of embedded packaging structure, including substrate 501, configuration is used In encapsulation wafer 101, substrate is provided with and is available for the cavity that wafer 101 embeds.The lower section of cavity It is provided with the first metal pad 504, by first between the first metal pad 504 and wafer 404 Metal throuth hole 503 connects.Cavity be arranged over Copper Foil 502, Copper Foil 502 and the first metal Connected by the second metal throuth hole 505 between pad 504.So, being used on wafer 101 The effective coverage being electrically connected with is by first metal throuth hole the 503, first metal pad 504 and the Two metal throuth holes 505 are conducted to Copper Foil 502.Copper Foil be arranged over the second metal pad 507, Connected by the 3rd metal throuth hole 506 between second metal pad 507 and Copper Foil 502.So, Effective coverage on wafer 101 is conducted to the second metal pad by the 3rd metal throuth hole 506 again 507, it is possible to be in the electric connection outside the realization of other elements at the second metal pad 507. Wherein, the first metal throuth hole the 503, second metal throuth hole 505 and the 3rd metal throuth hole 506, no Only can play electric action;Thermolysis is may also operate as with outer member when electrically connecting, Decrease basic internal heat to assemble, improve electrical efficiency.Meanwhile, arrange in a substrate Copper Foil, as shown in Figure 10, Copper Foil horizontally set, so can be by the second metal pad 507 Position extend to the both sides of substrate, thus it is empty to leave bigger cavity in substrate 501 Between.Preferably, cavity can be provided with multiple wafer.Further, the 507 of the second metal pad Position extends to the both sides of substrate 501, so that the wafer being disposed over can be with second Sufficiently long routing distance is there is between metal pad.

Further preferably embodiment, first metal throuth hole the 503, first metal pad 504, Second metal throuth hole 505, Copper Foil the 502, the 3rd metal throuth hole 506 and the second metal pad 507 It is fixedly installed in a substrate by lamination.Preferably, substrate is fixed by resin material layer pressing In.

Further preferably embodiment, embedded packaging structure also includes wafer 101 and cloth again Line structure, wafer upside-down mounting is also embedded in cavity, by wire structures again be electrically connected with wafer with Substrate, further, is electrically connected with wafer and the first metal pad 504 by wire structures again. So, wafer upside-down mounting arranges safer, and Embedded encapsulation, more light in structure, Thin and compact.

Further preferably embodiment, as shown in Figure 10, then wire structures includes titanium inculating crystal layer 301 and metal film layer 302, described titanium inculating crystal layer 301 is arranged on described wafer 102.Titanium Inculating crystal layer can promote that wafer is formed, thus can provide more can be with the having of extraneous routing Effect region.

Further preferably embodiment, wafer 101 is provided with chip metal pad 102, gold Belong to pad and be arranged over passivation layer 103, it is preferable that passivation layer 103 is silicon nitride layer.Passivation Layer 103 covers the upper surface of wafer 101 and exposes chip metal pad 102, titanium inculating crystal layer 301 It is arranged on passivation layer 103.Passivation layer is equivalent to the protective layer of wafer, prevents wafer to be corroded.

Further preferably embodiment, is provided with slow between passivation layer 103 and titanium inculating crystal layer 301 Rushing layer 201, cushion 201 is covered on passivation layer 103 and exposes chip metal pad 102, Wherein, the surface of titanium inculating crystal layer 301 cushion to be covered in 201 also will be by chip metal Pad 102 covers.Preferably, cushion 201 is polyimides glue-line.Cushion can be by The structure planarization of crystal column surface, effectively discharges stress.

In the equipment and method of the application, it is clear that each parts or each step be can decompose, Reconfigure after combination and/or decomposition.These decompose and/or reconfigure and should be regarded as the present invention's Equivalents.It may also be noted that the step performing above-mentioned series of processes can be pressed naturally Order as directed performs in chronological order, but is not required to perform the most sequentially in time. Some step can perform parallel or independently of one another.Meanwhile, in reality concrete to the application above Execute in the description of example, describe for a kind of embodiment and/or the feature that illustrates can with identical or Similar mode uses in one or more other embodiment, and in other embodiment Feature combined, or substitute the feature in other embodiment.

It should be emphasized that term " include/comprise " referring to when using herein feature, key element, step or The existence of assembly, but it is not precluded from one or more further feature, key element, step or assembly Existence or additional.

Although the present invention of being described in detail and advantage thereof it should be appreciated that without departing from by Can carry out various in the case of the spirit and scope that appended claim is limited Change, substitute and convert.And, scope of the present application is not limited only to the mistake described by description Journey, equipment, means, the specific embodiment of method and steps.Ordinary skill people in this area Member will readily appreciate that from present disclosure, can use execution and at this according to the application Function that described corresponding embodiment is essentially identical or obtain the result essentially identical with it, Existing and the most to be developed process, equipment, means, method or step.Therefore, institute Attached claim is directed in the range of them including such process, equipment, means, side Method or step.

Claims (10)

1. an embedded packaging structure, described structure includes:
Substrate, is configured to encapsulate wafer, is provided with and is available for what described wafer embedded in described substrate Cavity;
The lower section of described cavity is provided with the first metal pad, described first metal pad and described crystalline substance Connected by the first metal throuth hole between circle;Described cavity be arranged over Copper Foil, described Copper Foil Being connected by the second metal throuth hole with between described first metal pad, the top of described Copper Foil sets There is the second metal pad, led to by the 3rd metal between described second metal pad and described Copper Foil Hole connects;Described first metal throuth hole, described first metal pad, described second metal throuth hole, Described Copper Foil, described 3rd metal throuth hole and described second metal pad are fixedly installed by lamination In described substrate.
Embedded packaging structure the most according to claim 1, it is characterised in that described One metal throuth hole, described first metal pad, described second metal throuth hole, described Copper Foil, institute State the 3rd metal throuth hole and described second metal pad be pressed together in respective resin material respectively, It is fixed in described substrate by each resin material layer pressing again.
Embedded packaging structure the most according to claim 1 and 2, it is characterised in that also Including wafer, described wafer upside-down mounting is also embedded in described cavity;And wire structures, institute again State again wire structures and be electrically connected with described wafer and described substrate.
Embedded packaging structure the most according to claim 3, it is characterised in that described again Wire structures is electrically connected with described wafer and described first metal pad.
Embedded packaging structure the most according to claim 3, it is characterised in that connect up again Structure includes that titanium inculating crystal layer and metal film layer, described titanium inculating crystal layer are arranged on described wafer, Described metal film layer is electrically connected with described first metal pad.
Embedded packaging structure the most according to claim 5, it is characterised in that described crystalline substance Circle is provided with chip metal pad, and described chip metal pad is provided with passivation layer, described passivation Layer covers the upper surface of described wafer and exposes described chip metal pad, and described titanium inculating crystal layer sets Put on described passivation layer.
Embedded packaging structure the most according to claim 6, it is characterised in that described blunt Changing and be provided with cushion between layer and described titanium inculating crystal layer, described cushion also exposes described wafer gold Belong to pad.
Embedded packaging structure the most according to claim 7, it is characterised in that described slow Rushing layer is polyimides glue-line.
Embedded packaging structure the most according to claim 5, it is characterised in that described blunt Change layer is silicon nitride layer.
Embedded packaging structure the most according to claim 1 and 2, it is characterised in that Described metallic film is aluminum metal thin film, and the thickness of described aluminum metal thin film is more than 1 μm.
CN201610465118.0A 2016-06-24 2016-06-24 Embedded package structure CN106024657A (en)

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CN103779333A (en) * 2012-10-17 2014-05-07 钰桥半导体股份有限公司 Circuit board with embedded component and electromagnetic shielding
CN104600039A (en) * 2014-12-26 2015-05-06 南通富士通微电子股份有限公司 Double-side interconnecting fan-out process
CN105428265A (en) * 2014-09-11 2016-03-23 株式会社吉帝伟士 Manufacturing method for semiconductor device
CN105470144A (en) * 2014-09-09 2016-04-06 欣兴电子股份有限公司 Coreless layer packaging substrate and manufacturing method thereof
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101288351A (en) * 2005-10-14 2008-10-15 株式会社藤仓 Printed wiring board and method for manufacturing printed wiring board
US20090042336A1 (en) * 2007-08-06 2009-02-12 Kyung-Wook Paik Fabrication method of an organic substrate having embedded active-chips
CN101689539A (en) * 2007-08-08 2010-03-31 卡西欧计算机株式会社 Semiconductor device and method for manufacturing the same
CN101364581A (en) * 2007-08-10 2009-02-11 全懋精密科技股份有限公司 Loading board construction embedded with chip and preparation thereof
CN101944519A (en) * 2009-07-02 2011-01-12 卡西欧计算机株式会社 Semiconductor device including sealing film and manufacturing method of semiconductor device
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CN105428265A (en) * 2014-09-11 2016-03-23 株式会社吉帝伟士 Manufacturing method for semiconductor device
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CN104600039A (en) * 2014-12-26 2015-05-06 南通富士通微电子股份有限公司 Double-side interconnecting fan-out process

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