CN106023921A - GOA circuit - Google Patents
GOA circuit Download PDFInfo
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- CN106023921A CN106023921A CN201610536534.5A CN201610536534A CN106023921A CN 106023921 A CN106023921 A CN 106023921A CN 201610536534 A CN201610536534 A CN 201610536534A CN 106023921 A CN106023921 A CN 106023921A
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- film transistor
- thin film
- tft
- electrically connected
- level
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The present invention provides a GOA circuit comprising cascaded n-level GOA units; each level GOA unit comprises an up-pull control module, an up-pull module, a down-pull module, a bootstrap capacitor and a square wave signal generation module. The up-pull control module is connected respectively with the up-pull module, the down-pull module and the square wave signal generation module. The GOA circuit of the invention, with a square wave signal generation module to generate a square wave signal whose frequency is between the low frequency and the high frequency, can effectively prevent the gate of a thin film transistor from being affected by too high frequency or too low frequency, thus causing no work abnormality to the circuit.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of GOA circuit.
Background technology
Gate Driver On Array, is called for short GOA, i.e. at existing thin film transistor (TFT) liquid
Scan drive circuit is made, it is achieved to scan line line by line on the array base palte of LCD panel
The type of drive of scanning.The structural representation of existing GOA circuit as it is shown in figure 1,
This GOA circuit includes pulling up control module 101, pull-up module 104, drop-down module
105, bootstrap capacitor 103 and drop-down maintenance module 102.
Defeated for the pull-up control module in GOA circuit of drop-down maintenance module 102
The outfan going out to hold Q (n) and scanning signal G (n) carries out assisting drop-down.And it is drop-down
Maintain module switching frequency typically use the frequency identical with clock signal frequency or
Switch once every some frames, so easily cause the grid of thin film transistor (TFT) by high frequency
Or the impact of low frequency signal, causes circuit operation irregularity.
Therefore, it is necessary to provide a kind of GOA circuit, to solve asking of prior art existence
Topic.
Summary of the invention
It is an object of the invention to provide a kind of GOA circuit, it is provided that a kind of square wave letter
Number maintain the low level of the scanning signal of the scanning level signal of this grade and this grade, and just
The frequency of ripple signal, between low frequency and high frequency, is cut solving existing GOA circuit because
Change the technical problem of the highest or the lowest circuit operation irregularity caused of frequency.
For solving the problems referred to above, the technical scheme that the present invention provides is as follows:
The embodiment of the present invention provides a kind of GOA circuit, and it includes n level GOA of cascade
Unit, every one-level GOA unit all includes:
Pull-up control module, the control for the scanning signal according to upper level generates this level
Scanning level signal；
Pull-up module, for the clock letter of the scanning level signal according to this grade and this grade
Number draw high the scanning signal of this grade；
Drop-down module, for the scanning signal according to next stage, drags down the scanning electricity of this grade
Ordinary mail number；
Bootstrap capacitor, for generating the high level of the scanning signal of this grade；And,
Square-wave signal generation module, maintains the scanning level of this grade for generating square-wave signal
The low level of the scanning signal of signal and this grade；Wherein,
Pull-up control module generates with pull-up module, drop-down module and square-wave signal respectively
Module connects.
GOA circuit in the present invention also includes 2m second clock signal source, and it is electrical
It is connected to described square-wave signal generation module, for providing the second clock signal of this grade extremely
Described square-wave signal generation module generates the square-wave signal of this grade, and wherein, m is positive integer.
In the GOA circuit of the present invention, the described square wave of 2mk+a level GOA unit
Signal generation module is electrically connected at a described second clock signal source, and wherein, a is
Less than or equal to the integer of 2m, k is the positive integer more than or equal to 0.
In the GOA circuit of the present invention, the second of 2m second clock signal source offer
The pulsion phase of clock signal with and adjacent second clock signal source provide second clock
The time difference of signal is identical.
In the GOA circuit of the present invention, the second of 2m second clock signal source offer
The frequency of clock signal is 2～50 times of the frequency of the clock signal of this grade.
In the GOA circuit of the present invention, square-wave signal generation module includes the first film
Transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT),
5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT) and the 8th thin film
Transistor；
The grid of the first film transistor is electrically connected at the n-th-m level GOA unit circuit
The outfan of square-wave signal generation module；The source electrode of the first film transistor is electrically connected with
In constant voltage high level source；It is brilliant that the drain electrode of the first film transistor is electrically connected at the 3rd thin film
The grid of body pipe, the grid of the 5th thin film transistor (TFT) and the drain electrode of the second thin film transistor (TFT)；
The grid of the second thin film transistor (TFT) is electrically connected at the n-th+m level GOA unit circuit
The outfan of square-wave signal generation module, the source electrode of the second thin film transistor (TFT) is electrically connected with
In constant voltage low level source；
The source electrode of the 3rd thin film transistor (TFT) is electrically connected at the second clock signal source of this grade；
The drain electrode of the 3rd thin film transistor (TFT) is electrically connected at the outfan of square-wave signal generation module；
The grid of the 4th thin film transistor (TFT) is electrically connected at the n-th+m level GOA unit circuit
The outfan of square-wave signal generation module；The source electrode of the 4th thin film transistor (TFT) is electrically connected with
In constant voltage low level source；It is brilliant that the drain electrode of the 4th thin film transistor (TFT) is electrically connected at the 5th thin film
The drain electrode of body pipe, the drain electrode of the 6th thin film transistor (TFT), the grid of the 7th thin film transistor (TFT) and
The grid of the 8th thin film transistor (TFT)；
5th thin film transistor (TFT) source electrode be electrically connected at the second clock signal of this grade
Source；
The grid of the 6th thin film transistor (TFT) is electrically connected at the output of the scanning-line signal of this grade
End；The source electrode of the 6th thin film transistor (TFT) is electrically connected at constant voltage low level source；
The source electrode of the 7th thin film transistor (TFT) is electrically connected at constant voltage low level source；7th thin film
The drain electrode of transistor is electrically connected at the outfan of pull-up control module；
The source electrode of the 8th thin film transistor (TFT) is electrically connected at constant voltage low level source；8th thin film
The drain electrode of transistor is electrically connected at the outfan of the scanning signal of this grade.
In the GOA circuit of the present invention, pull-up control module includes the 9th film crystal
Pipe, the grid of the 9th thin film transistor (TFT) is electrically connected at the output of the scanning signal of upper level
End；The source electrode of the 9th thin film transistor (TFT) is electrically connected at constant voltage height power supply；9th thin film is brilliant
The drain electrode of body pipe is electrically connected at the outfan of pull-up control module.
In the GOA circuit of the present invention, pull-up module includes the tenth thin film transistor (TFT),
The grid of the tenth thin film transistor (TFT) is electrically connected at the outfan of pull-up control module；Tenth
The source electrode of thin film transistor (TFT) accesses the clock signal of this grade；The drain electrode of the tenth thin film transistor (TFT)
It is electrically connected at the outfan of the scanning signal of this grade.
In the GOA circuit of the present invention, drop-down module includes the 11st thin film transistor (TFT)
With the 12nd thin film transistor (TFT)；
The grid of the 11st thin film transistor (TFT) is electrically connected at the defeated of the scanning signal of next stage
Go out end；The source electrode of the 11st thin film transistor (TFT) is electrically connected at the low power supply of constant voltage；11st
The drain electrode of thin film transistor (TFT) is electrically connected with and the outfan of pull-up control module；
The grid of the 12nd thin film transistor (TFT) is electrically connected at the defeated of the scanning signal of next stage
Go out end；The source electrode of the 12nd thin film transistor (TFT) is electrically connected at the low power supply of constant voltage；12nd
The drain electrode of thin film transistor (TFT) is electrically connected at the outfan of the scanning signal of this grade.
In the GOA circuit of the present invention, one end of bootstrap capacitor is electrically connected at pull-up
The outfan of control module；The other end of bootstrap capacitor is electrically connected at the scanning letter of this grade
Number outfan.
Compared to existing GOA circuit, the GOA circuit of the present invention is by arranging square wave
Signal generation module, its frequency of square-wave signal generated between low frequency and high frequency,
Can effectively prevent the grid of thin film transistor (TFT) too high by frequency or underfrequency signal
Impact, and then do not result in circuit operation irregularity.
For the foregoing of the present invention can be become apparent, preferred embodiment cited below particularly,
And coordinate institute's accompanying drawings, it is described in detail below:
Accompanying drawing explanation
Below in conjunction with the accompanying drawings, by the detailed description of the invention of the present invention is described in detail, will
Make technical scheme and other beneficial effect apparent.
Fig. 1 is the structural representation of a kind of existing GOA circuit；
Fig. 2 is the structural representation of the first preferred embodiment of the GOA circuit of the present invention；
Fig. 3 is that the square-wave signal of the first preferred embodiment of the GOA circuit of the present invention is raw
Become oscillogram；
Fig. 4 is the signal waveforms of the first preferred embodiment of the GOA circuit of the present invention；
Fig. 5 is the structural representation of the second preferred embodiment of the GOA circuit of the present invention；
The square-wave signal of the second preferred embodiment of the GOA circuit that Fig. 6 is the present invention
Generate oscillogram；
The signal waveform of the second preferred embodiment of the GOA circuit that Fig. 7 is the present invention
Figure.
Detailed description of the invention
By further illustrating the technological means and effect thereof that the present invention taked, below tie
Close the preferred embodiments of the present invention and accompanying drawing is described in detail.
Seeing Fig. 2, the structure for the first preferred embodiment of the GOA circuit of the present invention is shown
It is intended to；
The GOA circuit of this preferred embodiment includes pulling up control module 201, pull-up module
202, drop-down module 203, bootstrap capacitor Cbt and square-wave signal generation module 204.
Pull-up control module 201, for the control of scanning signal G (n-1) according to upper level
Generate the scanning level signal of this grade；Pull-up module 202, for the scanning according to this grade
Clock signal CK (n) of level signal and this grade draws high scanning signal G (n) of this grade；
Drop-down module 203, for scanning signal G (n+1) according to next stage, drags down this level
Scanning level signal；Square-wave signal generation module 204, is used for generating square-wave signal P
N () maintains the scanning level signal of this grade and the low level of the scanning signal of this grade；Bootstrapping
Electric capacity Cbt is arranged on outfan and the scanning signal of this grade of pull-up control module 201
Between the outfan of G (n), for generating the high electricity of scanning signal G (n) of this grade
Flat；
Wherein, pull-up control module 201 respectively with pull-up module 202, drop-down module 203
And square-wave signal generation module 204 connects.
The GOA circuit of the embodiment of the present invention also includes 4 second clock signal sources, when second
Clock signal source is electrically connected at square-wave signal generation module 204, for providing the second of this grade
Clock signal generates square-wave signal P (n) of this grade to square-wave signal generation module.
It should be noted that the square-wave signal of the 4k+1 level GOA unit of GOA circuit
Generation module 204 is electrically connected at first second clock signal source, the of GOA circuit
The square-wave signal generation module 204 of 4k+2 level GOA unit is electrically connected at second
Two signal source of clock, the square-wave signal of the 4k+3 level GOA unit of GOA circuit generates
Module 204 is electrically connected at the 3rd second clock signal source, the 4k+4 of GOA circuit
The square-wave signal generation module 204 of level GOA unit is electrically connected at the 4th second clock
Signal source, wherein, k is the integer not less than 0.
The pulsion phase of the second clock signal of 4 second clock signal source offers is same and adjacent
Second clock signal source provide the time difference of second clock signal identical.
The frequency of the second clock signal that 4 second clock signal sources provide be this grade time
2～50 times of the frequency of clock signal CK (n).This preferred embodiment can be by adjusting second
What signal source of clock provided the frequency of second clock signal so that the embodiment of the present invention
GOA circuit is more stable.Preferably, 4 of the GOA circuit of the embodiment of the present invention
The frequency of the second clock signal that second clock signal source provides is this grade of clock signal
4 times of the frequency of CK (n).
Square-wave signal generation module 204 includes that the first film transistor T1, the second thin film are brilliant
Body pipe T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th thin film are brilliant
Body pipe T6, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7 and the 8th thin film are brilliant
Body pipe T8；
The grid of the first film transistor T7 is electrically connected at the n-th-2 grades GOA unit
The outfan of square-wave signal P (n-2) generation module；The source electrode of the first film transistor T1
It is electrically connected at constant voltage high level source VDD；The drain electrode of the first film transistor T1 is electrical
Be connected to the grid of the 3rd thin film transistor (TFT) T3, the grid of the 5th thin film transistor (TFT) T5 and
The drain electrode of the second thin film transistor (TFT) T2；
The grid of the second thin film transistor (TFT) T2 is electrically connected at the n-th+2 grades GOA unit
The outfan of square-wave signal P (n+2) generation module, the source of the second thin film transistor (TFT) T2
Pole is electrically connected at constant voltage low level source Vss；
The source electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at the second clock signal of this grade
Source CKH；The drain electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at square-wave signal and generates mould
The outfan of block P (n)；
The grid of the 4th thin film transistor (TFT) T4 is electrically connected at the n-th+2 grades GOA unit
The outfan of square-wave signal P (n+2) generation module；The source of the 4th thin film transistor (TFT) T4
Pole is electrically connected at constant voltage low level source Vss；The drain electrode of the 4th thin film transistor (TFT) T4 is electrical
Be connected to the drain electrode of the 5th thin film transistor (TFT) T5, the drain electrode of the 6th thin film transistor (TFT) T6,
The grid of the 7th thin film transistor (TFT) T7 and the grid of the 8th thin film transistor (TFT) T8；
5th thin film transistor (TFT) T5 source electrode be electrically connected at this grade second clock letter
Number source CKH；
The grid of the 6th thin film transistor (TFT) T6 is electrically connected at scanning signal G (n) of this grade
Outfan；The source electrode of the 6th thin film transistor (TFT) T6 is electrically connected at constant voltage low level source
Vss；
The source electrode of the 7th thin film transistor (TFT) T7 is electrically connected at constant voltage low level source Vss；The
The drain electrode of seven thin film transistor (TFT) T7 is electrically connected at the outfan of pull-up control module 201；
The source electrode of the 8th thin film transistor (TFT) T8 is electrically connected at constant voltage low level source Vss；The
The drain electrode of eight thin film transistor (TFT) T8 is electrically connected at the defeated of scanning signal G (n) of this grade
Go out end.
Pull-up control module 201 includes the 9th thin film transistor (TFT) T9, the 9th thin film transistor (TFT)
The grid of T9 is electrically connected at the outfan of scanning signal G (n-1) of upper level；9th
The source electrode of thin film transistor (TFT) T9 is electrically connected at constant voltage height power vd D；9th thin film is brilliant
The drain electrode of body pipe T9 is electrically connected at the outfan of pull-up control module 201.
Pull-up module 202 includes the tenth thin film transistor (TFT) T10, the tenth thin film transistor (TFT) T10
Grid be electrically connected at pull-up control module 201 outfan；Tenth thin film transistor (TFT)
The source electrode of T10 accesses clock signal CK (n) of this grade；Tenth thin film transistor (TFT) T10's
Drain electrode is electrically connected at the outfan of scanning signal G (n) of this grade.
Drop-down module 203 includes the 11st thin film transistor (TFT) T11 and the 12nd film crystal
Pipe T12；
The grid of the 11st thin film transistor (TFT) T11 is electrically connected at the scanning signal of next stage
The outfan of G (n+1)；The source electrode of the 11st thin film transistor (TFT) T11 is electrically connected at constant voltage
Low power supply Vss；The drain electrode of the 11st thin film transistor (TFT) T11 is electrically connected with and controls mould with pull-up
The outfan of block 201；
The grid of the 12nd thin film transistor (TFT) T12 is electrically connected at the scanning signal of next stage
The outfan of G (n+1)；The source electrode of the 12nd thin film transistor (TFT) T12 is electrically connected at constant voltage
Low power supply Vss；The drain electrode of the 12nd thin film transistor (TFT) T12 is electrically connected at the scanning of this grade
The outfan of signal G (n).
One end of bootstrap capacitor Cbt is electrically connected at the outfan of pull-up control module 201；
The other end of bootstrap capacitor Cbt is electrically connected at the output of scanning signal G (n) of this grade
End.
Seeing Fig. 2, Fig. 3, Fig. 3 is that the first of the GOA circuit of the present invention is preferable to carry out
The square-wave signal of example generates oscillogram；
Within t1～the t2 time period, when the square-wave signal of the n-th-2 grades GOA unit generates mould
When the square-wave signal P (n-2) of block output is high level, the first film transistor T1 beats
Opening, the constant voltage high level that constant voltage high level source VDD provides is through the first film transistor T1
Reaching the 3rd thin film transistor (TFT) T3 and the grid of the 5th thin film transistor (TFT) T5, the 3rd is thin
Film transistor T3 and the 5th thin film transistor (TFT) T5 opens, now the second clock of this grade
Signal CKH output low level, through the 3rd thin film transistor (TFT) T3 and the 5th thin film transistor (TFT)
T5 reaches outfan and first reference of square-wave signal P (n) of this grade of GOA unit
Point K (n) so that square-wave signal P (n) and first of this grade of GOA unit output
Reference point K (n) is low level.
Within t2～the t3 time period, the square-wave signal generation module of the n-th-2 grades GOA unit
The square-wave signal P (n-2) of output transfers low level to, but now brilliant due to the 3rd thin film
Body pipe T3 and the Capacitance Coupled effect of the 5th thin film transistor (TFT) T5 grid so that now
The grid of the 3rd thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5 still maintains high electricity
Position, now the 3rd thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5 is still within leading
Logical state, the second clock signal CKH of this grade transfers high level to, through the 3rd accordingly
Thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5 reaches the square wave of this grade of GOA unit
The outfan of signal P (n) and the first reference point K (n) so that this grade of GOA is mono-
Square-wave signal P (n) and first reference point K (n) of unit's output transfer high level to.
Within t3～the t4 time period, when the square-wave signal of the n-th+2 grades GOA unit generates mould
The square-wave signal P (n+2) of block output is when being high level, the second thin film transistor (TFT) T2 and
4th thin film transistor (TFT) T4 opens, the constant voltage low level that constant voltage low level source Vss provides
The 3rd film crystal is reached through the second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4
The grid of pipe T3, the grid of the 5th thin film transistor (TFT) T5 and the first reference point K (n),
Square-wave signal P (n) and the first reference point K so that this grade of GOA unit output
N () transfers low level to.
Within t4～the t5 time period, the square-wave signal generation module of the n-th-2 grades GOA unit
The square-wave signal P (n-2) of output and the square-wave signal of the n-th+2 grades GOA unit generate
The square-wave signal P (n+2) of module output is low level, this grade of GOA unit output
Square-wave signal P (n) and the first reference point K (n) are low level.
Seeing Fig. 2, Fig. 4, Fig. 4 is that the first of the GOA circuit of the present invention is preferable to carry out
The signal waveforms of example；
When the GOA circuit of this preferred embodiment uses, when the scanning signal of upper level
G (n-1) is high level, and the 9th thin film transistor (TFT) T9 conducting, constant voltage high level source provides
Constant voltage high level, through the 9th thin film transistor (TFT) T9 to bootstrap capacitor Cbt charge, make
Obtain the second reference point Q (n) and rise to a higher level.
Scanning signal G (n-1) of upper level subsequently transfers low level to, the 9th thin film transistor (TFT)
T9 closes, and the second reference point Q (n) maintains a higher level by bootstrap capacitor Cbt.
Meanwhile, clock signal CK (n) of this grade transfers high level to, and clock signal CK (N) is passed through
Tenth thin film transistor (TFT) T10 continues to charge to bootstrap capacitor Cbt so that the second reference point
Q (n) reaches a higher level, and scanning signal G (n) of this grade transfers high level to.
When scanning signal G (n+1) of next stage transfers high level to, the 11st film crystal
Pipe T11 and the 12nd thin film transistor (TFT) T12 opens, and constant voltage low level source Vss produces
Constant voltage low level reaches the second reference point Q (n), the constant voltage that constant voltage low level source Vss produces
Low level reaches the outfan of scanning signal G (n) of this grade, the second reference point Q (n) place
Voltage and scanning signal G (n) of this grade be pulled low.
The square-wave signal that this preferred embodiment is generated by square-wave signal generation module, to
The outfan of the scanning signal of two reference points Q (n) and this grade carry out 4 times drop-down, dimension
Hold the low electricity of the outfan of scanning signal G (n) of the second reference point Q (n) and this grade
Position.Specifically, when the first reference point K (n) is high level, the 7th film crystal
Pipe T7 and the 8th thin film transistor (TFT) T8 opens, the perseverance that constant voltage low level source Vss provides
Force down level and reach second through the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8
The outfan of scanning signal G (n) of reference point Q (n) and this grade, maintains the second ginseng
The electronegative potential of the outfan of scanning signal G (n) of examination point Q (n) and this grade.
It is specifically intended that when scanning signal G (n) outfan of this grade is high level,
6th thin film transistor (TFT) T6 opens, the constant voltage low level that constant voltage low level source Vss provides
The first reference point K (n) is reached so that the first reference point through the 6th thin film transistor (TFT) T6
K (n) is now low level, the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8
Now close.
The GOA circuit of this preferred embodiment is by arranging square-wave signal generation module, and it is raw
The square-wave signal frequency become, between low frequency and high frequency, can effectively prevent film crystal
The grid of pipe is too high by frequency or underfrequency signal is affected, and then does not results in
Circuit operation irregularity.
Seeing Fig. 5, the structure for the second preferred embodiment of the GOA circuit of the present invention is shown
It is intended to；
The GOA circuit of this preferred embodiment and the GOA circuit of the first preferred embodiment
Difference is, the quantity of the second clock signal accessing GOA circuit is 8, permissible
Reduce power consumption further, and do not result in circuit operation irregularity.
The GOA circuit of this preferred embodiment includes pulling up control module 301, pull-up module
302, drop-down module 303, bootstrap capacitor Cbt and square-wave signal generation module 304.
Pull-up control module 301, for the control of scanning signal G (n-1) according to upper level
Generate the scanning level signal of this grade；Pull-up module 302, for the scanning according to this grade
Clock signal CK (n) of level signal and this grade draws high scanning signal G (n) of this grade；
Drop-down module 303, for scanning signal G (n+1) according to next stage, drags down this level
Scanning level signal；Square-wave signal generation module 304, is used for generating square-wave signal P
N () maintains the scanning level signal of this grade and the low level of the scanning signal of this grade；Bootstrapping
Electric capacity Cbt is arranged on outfan and the scanning signal of this grade of pull-up control module 301
Between the outfan of G (n), for generating the high electricity of scanning signal G (n) of this grade
Flat；
Wherein, pull-up control module 301 respectively with pull-up module 302, drop-down module 303
And square-wave signal generation module 304 connects.
The GOA circuit of the embodiment of the present invention accesses 8 second clock signal sources CKH, the
Two signal source of clock are electrically connected at square-wave signal generation module 304, for providing this grade
Second clock signal generates square-wave signal P (n) of this grade to square-wave signal generation module.
It should be noted that the square-wave signal of the 8k+1 level GOA unit of GOA circuit
Generation module 304 is electrically connected at first second clock signal source CKH, GOA circuit
The square-wave signal generation module 304 of 8k+2 level GOA unit be electrically connected at second
Individual second clock signal source, the square-wave signal of the 8k+3 level GOA unit of GOA circuit
Generation module 304 is electrically connected at the 3rd second clock signal source, the of GOA circuit
The square-wave signal generation module 304 of 8k+4 level GOA unit is electrically connected at the 4th
Two signal source of clock, the square-wave signal of the 8k+5 level GOA unit of GOA circuit generates
Module 304 is electrically connected at the 5th second clock signal source CKH, the of GOA circuit
The square-wave signal generation module 304 of 8k+6 level GOA unit is electrically connected at the 6th
Two signal source of clock CKH, the square-wave signal of the 8k+7 level GOA unit of GOA circuit
Generation module 304 is electrically connected at the 7th second clock signal source CKH, GOA circuit
The square-wave signal generation module 304 of 8k+8 level GOA unit be electrically connected at the 8th
Wherein, k is the integer not less than 0 to individual second clock signal source CKH.
The pulsion phase of the second clock signal of 8 second clock signal source offers is same and adjacent
Second clock signal source provide the time difference of second clock signal identical..
The frequency of the second clock signal that 8 second clock signal sources provide be this grade time
2～50 times of the frequency of clock signal CK (n).This preferred embodiment can be by adjusting second
What signal source of clock provided the frequency of second clock signal so that the embodiment of the present invention
GOA circuit is more stable.Preferably, 8 of the GOA circuit of the embodiment of the present invention
The frequency of the second clock signal that second clock signal source provides is this grade of clock signal
2 times of the frequency of CK (n).
Square-wave signal generation module 304 includes that the first film transistor T1, the second thin film are brilliant
Body pipe T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4, the 5th thin film are brilliant
Body pipe T6, the 6th thin film transistor (TFT) T6, the 7th thin film transistor (TFT) T7 and the 8th thin film are brilliant
Body pipe T8；
The grid of the first film transistor T7 is electrically connected at the n-th-4 grades GOA unit
The outfan of square-wave signal P (n-4) generation module；The source electrode of the first film transistor T1
It is electrically connected at constant voltage high level source VDD；The drain electrode of the first film transistor T1 is electrical
Be connected to the grid of the 3rd thin film transistor (TFT) T3, the grid of the 5th thin film transistor (TFT) T5 and
The drain electrode of the second thin film transistor (TFT) T2；
The grid of the second thin film transistor (TFT) T2 is electrically connected at the n-th+4 grades GOA unit
The outfan of square-wave signal P (n+4) generation module, the source of the second thin film transistor (TFT) T2
Pole is electrically connected at constant voltage low level source Vss；
The source electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at the second clock signal of this grade
Source CKH；The drain electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at square-wave signal and generates mould
The outfan of block P (n)；
The grid of the 4th thin film transistor (TFT) T4 is electrically connected at the n-th+4 grades GOA unit
The outfan of square-wave signal P (n+4) generation module；The source of the 4th thin film transistor (TFT) T4
Pole is electrically connected at constant voltage low level source Vss；The drain electrode of the 4th thin film transistor (TFT) T4 is electrical
Be connected to the drain electrode of the 5th thin film transistor (TFT) T5, the drain electrode of the 6th thin film transistor (TFT) T6,
The grid of the 7th thin film transistor (TFT) T7 and the grid of the 8th thin film transistor (TFT) T8；
5th thin film transistor (TFT) T5 source electrode be electrically connected at this grade second clock letter
Number source CKH；
The grid of the 6th thin film transistor (TFT) T6 is electrically connected at scanning signal G (n) of this grade
Outfan；The source electrode of the 6th thin film transistor (TFT) T6 is electrically connected at constant voltage low level source
Vss；
The source electrode of the 7th thin film transistor (TFT) T7 is electrically connected at constant voltage low level source Vss；The
The drain electrode of seven thin film transistor (TFT) T7 is electrically connected at the outfan of pull-up control module 301；
The source electrode of the 8th thin film transistor (TFT) T8 is electrically connected at constant voltage low level source Vss；The
The drain electrode of eight thin film transistor (TFT) T8 is electrically connected at the defeated of scanning signal G (n) of this grade
Go out end.
Pull-up control module 301 includes the 9th thin film transistor (TFT) T9, the 9th thin film transistor (TFT)
The grid of T9 is electrically connected at the outfan of scanning signal G (n-1) of upper level；9th
The source electrode of thin film transistor (TFT) T9 is electrically connected at constant voltage height power vd D；9th thin film is brilliant
The drain electrode of body pipe T9 is electrically connected at the outfan of pull-up control module 301.
Pull-up module 302 includes the tenth thin film transistor (TFT) T10, the tenth thin film transistor (TFT) T10
Grid be electrically connected at pull-up control module 301 outfan；Tenth thin film transistor (TFT)
The source electrode of T10 accesses clock signal CK (n) of this grade；Tenth thin film transistor (TFT) T10's
Drain electrode is electrically connected at the outfan of scanning signal G (n) of this grade.
Drop-down module 303 includes the 11st thin film transistor (TFT) T11 and the 12nd film crystal
Pipe T12；
The grid of the 11st thin film transistor (TFT) T11 is electrically connected at the scanning signal of next stage
The outfan of G (n+1)；The source electrode of the 11st thin film transistor (TFT) T11 is electrically connected at constant voltage
Low power supply Vss；The drain electrode of the 11st thin film transistor (TFT) T11 is electrically connected with and controls mould with pull-up
The outfan of block 301；
The grid of the 12nd thin film transistor (TFT) T12 is electrically connected at the scanning signal of next stage
The outfan of G (n+1)；The source electrode of the 12nd thin film transistor (TFT) T12 is electrically connected at constant voltage
Low power supply Vss；The drain electrode of the 12nd thin film transistor (TFT) T12 is electrically connected at the scanning of this grade
The outfan of signal G (n).
One end of bootstrap capacitor Cbt is electrically connected at the outfan of pull-up control module 301；
The other end of bootstrap capacitor Cbt is electrically connected at the output of scanning signal G (n) of this grade
End.
Seeing Fig. 5, Fig. 6, Fig. 6 is that the second of the GOA circuit of the present invention is preferable to carry out
The square-wave signal of example generates oscillogram；
Within t1～the t2 time period, when the square-wave signal of the n-th-4 grades GOA unit generates mould
When the square-wave signal P (n-4) of block output is high level, the first film transistor T1 beats
Opening, the constant voltage high level that constant voltage high level source VDD provides is through the first film transistor T1
Reaching the 3rd thin film transistor (TFT) T3 and the grid of the 5th thin film transistor (TFT) T5, the 3rd is thin
Film transistor T3 and the 5th thin film transistor (TFT) T5 opens, now second clock signal CKH
Output low level, reaches through the 3rd thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5
The outfan of square-wave signal P (n) of the GOA unit of this grade and the first reference point K (n),
Make square-wave signal P (n) and first reference point K (n) of this grade of GOA unit output
For low level.
Within t2～the t3 time period, the square-wave signal generation module of the n-th-4 grades GOA unit
The square-wave signal P (n-4) of output transfers low level to, but now brilliant due to the 3rd thin film
Body pipe T3 and the Capacitance Coupled effect of the 5th thin film transistor (TFT) T5 grid so that now
The grid of the 3rd thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5 still maintains high electricity
Position, now the 3rd thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5 is still within leading
Logical state, the second clock signal CKH of this grade transfers high level to, through the 3rd accordingly
Thin film transistor (TFT) T3 and the 5th thin film transistor (TFT) T5 reaches the square wave of this grade of GOA unit
The outfan of signal P (n) and the first reference point K (n) so that this GOA unit
Square-wave signal P (n) and first reference point K (n) of output transfer high level to.
Within t3～the t4 time period, when the square-wave signal of the n-th+4 grades GOA unit generates mould
The square-wave signal P (n+4) of block output is when being high level, the second thin film transistor (TFT) T2 and
4th thin film transistor (TFT) T4 opens, the constant voltage low level that constant voltage low level source Vss provides
The 3rd film crystal is reached through the second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4
The grid of pipe T3, the grid of the 5th thin film transistor (TFT) T5 and the first reference point K (n),
Make square-wave signal P (n) and first reference point K (n) of this grade of GOA unit output
Transfer low level to.
Within t4～the t5 time period, the square-wave signal generation module of the n-th-4 grades GOA unit
The square-wave signal P (n-4) of output and the square-wave signal of the n-th+4 grades GOA unit generate
The square-wave signal P (n+4) of module output is low level, this grade of GOA unit output
Square-wave signal P (n) and the first reference point K (n) are low level.
Seeing Fig. 5, Fig. 7, Fig. 7 is that the second of the GOA circuit of the present invention is preferable to carry out
The signal waveforms of example；
When the GOA circuit of this preferred embodiment uses, when the scanning signal of upper level
G (n-1) is high level, and the 9th thin film transistor (TFT) T9 conducting, constant voltage high level source provides
Constant voltage high level, through the 9th thin film transistor (TFT) T9 to bootstrap capacitor Cbt charge, make
Obtain the second reference point Q (n) and rise to a higher level.
Scanning signal G (n-1) of upper level subsequently transfers low level to, the 9th thin film transistor (TFT)
T9 closes, and the second reference point Q (n) maintains a higher level by bootstrap capacitor Cbt.
Meanwhile, clock signal CK (n) of this grade transfers high level to, and clock signal CK (N) is passed through
Tenth thin film transistor (TFT) T10 continues to charge to bootstrap capacitor Cbt so that the second reference point
Q (n) reaches a higher level, and scanning signal G (n) of this grade transfers high level to.
When scanning signal G (n+1) of next stage transfers high level to, the 11st film crystal
Pipe T11 and the 12nd thin film transistor (TFT) T12 opens, and constant voltage low level source Vss produces
Constant voltage low level reaches the second reference point Q (n), the constant voltage that constant voltage low level source Vss produces
Low level reaches the outfan of scanning signal G (n) of this grade, the second reference point Q (n) place
Voltage and scanning signal G (n) of this grade be pulled low.
The square-wave signal that this preferred embodiment is generated by square-wave signal generation module, to
The outfan of the scanning signal of two reference points Q (n) and this grade carry out 2 times drop-down, dimension
Hold the low electricity of the outfan of scanning signal G (n) of the second reference point Q (n) and this grade
Position.Specifically, when the first reference point K (n) is high level, the 7th film crystal
Pipe T7 and the 8th thin film transistor (TFT) T8 opens, the perseverance that constant voltage low level source Vss provides
Force down level and reach second through the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8
The outfan of scanning signal G (n) of reference point Q (n) and this grade, maintains the second ginseng
The electronegative potential of the outfan of scanning signal G (n) of examination point Q (n) and this grade.
It is specifically intended that when scanning signal G (n) outfan of this grade is high level,
6th thin film transistor (TFT) T6 opens, the constant voltage low level that constant voltage low level source Vss provides
The first reference point K (n) is reached so that the first reference point through the 6th thin film transistor (TFT) T6
K (n) is now low level, the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8
Now close.
The GOA circuit of this preferred embodiment is by arranging square-wave signal generation module, and it is raw
The square-wave signal frequency become, between low frequency and high frequency, can effectively prevent film crystal
The grid of pipe is too high by frequency or underfrequency signal is affected, and then does not results in
Circuit operation irregularity.
To sum up, although the present invention is disclosed above with preferred embodiment, but above-mentioned preferred reality
Executing example and be not used to limit the present invention, those of ordinary skill in the art, without departing from this
In the spirit and scope of invention, all can make various change and retouching, the therefore guarantor of the present invention
Scope of protecting defines in the range of standard with claim.
Claims (10)
1. a GOA circuit, it is characterised in that include that n level GOA of cascade is mono-
Unit, every one-level GOA unit all includes:
Pull-up control module, the control for the scanning signal according to described upper level generates
The scanning level signal of this grade；
Pull-up module, for according to the scanning level signal of described level and this grade time
Clock signal draws high the scanning signal of this grade；
Drop-down module, for the scanning signal according to next stage, drags down sweeping of described level
Retouch level signal；
Bootstrap capacitor, for generating the high level of the scanning signal of described level；And,
Square-wave signal generation module, maintains the scanning of described level for generating square-wave signal
The low level of the scanning signal of level signal and described level；Wherein,
Described pull-up control module respectively with described pull-up module, described drop-down module and
Described square-wave signal generation module connects.
GOA circuit the most according to claim 1, it is characterised in that described GOA
Circuit also includes 2m second clock signal source, and it is raw that it is electrically connected at described square-wave signal
Become module, for providing the second clock signal of this grade to described square-wave signal generation module
Generating the square-wave signal of this grade, wherein, m is positive integer.
GOA circuit the most according to claim 2, it is characterised in that 2mk+a
The described square-wave signal generation module of level GOA unit is electrically connected at a described second
Signal source of clock, wherein, a is the integer less than or equal to 2m, and k is more than or equal to 0
Positive integer.
GOA circuit the most according to claim 2, it is characterised in that described 2m
The pulsion phase of the second clock signal that individual second clock signal source provides with and adjacent second
What signal source of clock provided the time difference of second clock signal is identical.
GOA circuit the most according to claim 2, it is characterised in that described 2m
The frequency of the second clock signal that individual second clock signal source provides is the clock of described level
2～50 times of the frequency of signal.
GOA circuit the most according to claim 2, it is characterised in that described side
Ripple signal generation module includes the first film transistor, the second thin film transistor (TFT), the 3rd thin
Film transistor, the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT),
7th thin film transistor (TFT) and the 8th thin film transistor (TFT)；
The grid of described the first film transistor is electrically connected at the n-th-m level GOA unit
The outfan of square-wave signal generation module；The source electrode of described the first film transistor is electrical
It is connected to constant voltage high level source；The drain electrode of described the first film transistor is electrically connected at institute
State the grid of the 3rd thin film transistor (TFT), the grid of described 5th thin film transistor (TFT) and described
The drain electrode of two thin film transistor (TFT)s；
The grid of described second thin film transistor (TFT) is electrically connected at the n-th+m level GOA unit
The outfan of the square-wave signal generation module of circuit, the source electrode of described second thin film transistor (TFT)
It is electrically connected at constant voltage low level source；
The source electrode of described 3rd thin film transistor (TFT) is electrically connected at the second clock signal of this grade
Source；The drain electrode of described 3rd thin film transistor (TFT) is electrically connected at described square-wave signal and generates mould
The outfan of block；
The grid of described 4th thin film transistor (TFT) is electrically connected at described n-th+m level GOA
The outfan of the square-wave signal generation module of element circuit；Described 4th thin film transistor (TFT)
Source electrode is electrically connected at described constant voltage low level source；The drain electrode of described 4th thin film transistor (TFT)
It is electrically connected at the drain electrode of described 5th thin film transistor (TFT), described 6th thin film transistor (TFT)
Drain electrode, the grid of described 7th thin film transistor (TFT) and the grid of described 8th thin film transistor (TFT)；
Described 5th thin film transistor (TFT) source electrode be electrically connected at described level second time
Clock signal source；
The grid of described 6th thin film transistor (TFT) is electrically connected at the scan line letter of described level
Number outfan；It is low that the source electrode of described 6th thin film transistor (TFT) is electrically connected at described constant voltage
Level source；
The source electrode of described 7th thin film transistor (TFT) is electrically connected at described constant voltage low level source；
The drain electrode of described 7th thin film transistor (TFT) is electrically connected at the output of described pull-up control module
End；
The source electrode of described 8th thin film transistor (TFT) is electrically connected at described constant voltage low level source；
The drain electrode of described 8th thin film transistor (TFT) is electrically connected at the defeated of the scanning signal of described level
Go out end.
GOA circuit the most according to claim 1, described pull-up control module bag
Including the 9th thin film transistor (TFT), the grid of described 9th thin film transistor (TFT) is electrically connected at one
The outfan of the scanning signal of level；The source electrode of described 9th thin film transistor (TFT) is electrically connected at
Constant voltage height power supply；The drain electrode of described 9th thin film transistor (TFT) is electrically connected at described pull-up control
The outfan of molding block.
GOA circuit the most according to claim 1, it is characterised in that on described
Drawing-die block includes that the tenth thin film transistor (TFT), the grid of described tenth thin film transistor (TFT) electrically connect
It is connected to the outfan of described pull-up control module；The source electrode of described tenth thin film transistor (TFT) connects
Enter the clock signal of described level；The drain electrode of described tenth thin film transistor (TFT) is electrically connected at
The outfan of the scanning signal of described level.
GOA circuit the most according to claim 1, it is characterised in that under described
Drawing-die block includes the 11st thin film transistor (TFT) and the 12nd thin film transistor (TFT)；
The grid of described 11st thin film transistor (TFT) is electrically connected at the scanning of described next stage
The outfan of signal；It is low that the source electrode of described 11st thin film transistor (TFT) is electrically connected at constant voltage
Power supply；The drain electrode of described 11st thin film transistor (TFT) is electrically connected with and controls mould with described pull-up
The outfan of block；
The grid of described 12nd thin film transistor (TFT) is electrically connected at the scanning of described next stage
The outfan of signal；It is low that the source electrode of described 12nd thin film transistor (TFT) is electrically connected at constant voltage
Power supply；The drain electrode of described 12nd thin film transistor (TFT) is electrically connected at the scanning of described level
The outfan of signal.
GOA circuit the most according to claim 1, it is characterised in that described
One end of bootstrap capacitor is electrically connected at the outfan of described pull-up control module；Described from
The other end lifting electric capacity is electrically connected at the outfan scanning signal of described level.
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| CN201610536534.5A CN106023921B (en) | 2016-07-08 | 2016-07-08 | A kind of GOA circuits |
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| CN201610536534.5A CN106023921B (en) | 2016-07-08 | 2016-07-08 | A kind of GOA circuits |
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| CN107705761A (en) * | 2017-09-27 | 2018-02-16 | 深圳市华星光电技术有限公司 | A kind of GOA circuits and liquid crystal display |
| CN110164391A (en) * | 2019-04-25 | 2019-08-23 | 昆山龙腾光电有限公司 | Horizontal drive circuit, display device and row driving method |
| WO2020151050A1 (en) * | 2019-01-22 | 2020-07-30 | 深圳市华星光电半导体显示技术有限公司 | Goa circuit and liquid crystal display device |
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| CN106023921B (en) | 2018-07-03 |
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