CN106019351A - Extremely-low-noise particle detection system and read-out chip - Google Patents

Abstract

The invention relates to an extremely-low-noise particle detection system and a read-out chip. The read-out chip applied to an extremely-low-noise particle detector comprises a plurality of channels, wherein each channel comprises an input stage JFET and a front-end CMOS amplification circuit; each input stage JFET is used for receiving an output signal of the extremely-low-noise particle detector; and each front-end CMOS amplification circuit is coupled with the corresponding input stage JFET, and is used for amplifying the output signal. The extremely-low-noise particle detection system and the read-out chip provided by the invention can improve noise performance of the read-out chip.

Description

Extremely low noise particle detection system and reading chip

Technical field

It relates to Particel Detection Methods, in particular to extremely low noise particle detection system and reading chip.

Background technology

In recent years, in the particle detection application in increasing such as astronomical experiment, application-specific integrated circuit ASIC (Application Specific Integrated Circuit) is used for the read-out system of extensive intensive detector. ASIC is in the advantage of the aspect such as volume, power consumption, considerably beyond the read-out system using discrete component composition.Along with extensive detection The development of array, corresponding high density ASIC read-out system becomes the focus instantly studied.

It is said that in general, read-out system can use two schemes.One is pure cmos device scheme, the most before puts reading and all uses CMOS technology makes.Another kind is detector and discrete JFET (Junction Field-Effect Transistor, JFET) The scheme that device is integrated, detector output and JFET input are directly connected to by processing technology standard on detector silicon chip.

But, these schemes are still difficult to meet demand at the aspect such as noiseproof feature or volume.Accordingly, it would be desirable to the particle improved Detection system and reading chip solution, in particular for reading chip and the system of extremely low noise particle detection.

Be only used for strengthening the understanding of background of this disclosure in information above-mentioned disclosed in described background section, therefore it Can include not constituting the information to prior art known to persons of ordinary skill in the art.

Summary of the invention

A kind of extremely low noise particle detection system of disclosure and reading chip, it is possible to improve and read chip noise Energy.

According to an aspect of this disclosure, it is provided that a kind of reading chip for extremely low noise particle detector, described reading Go out chip and include that multiple passage, each passage include:

Input stage JFET, the output signal of receiving pole low noise particle detector；

Front end CMOS amplifying circuit, couples with described input stage JFET, is amplified described output signal.

According to some embodiments, described extremely low noise particle detector is the semiconductor detector without enlarging function.

According to some embodiments, described front end CMOS amplifying circuit includes cmos amplifier and is coupled to described CMOS amplification Feedback arrangement between input and the outfan of device.

According to some embodiments, described feedback arrangement includes:

The feedback resistance being connected in parallel and feedback capacity；Or

The switch element being connected in parallel and feedback capacity.

According to some embodiments, the input pipe of described cmos amplifier meets following condition:

L=L_min

$W=\frac{C_{in}}{\frac{2}{3}{C}_{ox}L}$

${\mathrm{ENC}}^2\≈\frac{8}{3}{C}_{in}{\mathrm{\πK}}_f(1+\frac{3C_{ov}}{C_{ox}L})$

Wherein L is the channel length of described input pipe, and W is the channel width of described input pipe, L_minFor process critical chi Very little；C_inFor reading the input total capacitance of chip, K_f、C_ov、C_oxFor technique relevant parameter, ENC is equivalent noise charge.

According to some embodiments, read chip and also include: filtering wave-shaping circuit, defeated with described front end CMOS amplifying circuit Go out end to couple.

According to some embodiments, described filtering wave-shaping circuit is CR-(RC)ⁿActive filter circuit, described filtering shapes electricity The peak time on road meets following condition:

$\mathrm{\τ}\≤\frac{10}{A_{px}}\left(\mathrm{\μ}s\right)$

Wherein τ is peak time, A_pxFor elemental area.

According to some embodiments, the series connection that the peak time of described filtering wave-shaping circuit is chosen so as to input stage JFET is white Noise and white noise sum in parallel are minimum.

According to some embodiments, described reading chip includes: the first conductive-type semiconductor substrate, described input stage JFET and Described front end CMOS amplifying circuit is formed on the semiconductor substrate.

According to some embodiments, input stage JFET includes:

The the second conductivity type isolation deep trap being formed in described first conductive-type semiconductor substrate；

It is formed at the first conductivity type bottom gate on described second conductivity type isolation deep trap；

It is formed at the second conductive type of channel district on described first conductivity type bottom gate；

It is formed at the first conductivity type top-gated on described second conductive type of channel district and is positioned at described first conductivity type The source/drain electrode of top-gated both sides, carries out electricity by shallow trench isolation region between described first conductivity type top-gated and described source/drain electrode Isolation.

According to a further aspect in the invention, it is provided that a kind of extremely low noise particle detection system, visit including extremely low noise particle Survey device and aforementioned reading chip.

According to some embodiments of the present invention, input stage JFET can be integrated in reading chip by standard CMOS process, And obtain the performance suitable with discrete type JFET.

According to some embodiments of the present invention, read chip input stage and use parasitic JFET, subsequent conditioning circuit in CMOS technology Employing standard CMOS device makes, and solve pure cmos device reads the problem that chip noise performance is the best.Meanwhile, eliminate Reading circuit volume based on the design of discrete type JFET device is bigger, it is difficult to expand to multichannel problem.

Other characteristics of the disclosure and advantage will be apparent from by detailed description below, or partially by the disclosure Practice and acquistion.

Accompanying drawing explanation

Describing its example embodiment in detail by referring to accompanying drawing, above and other feature of the disclosure and advantage will become more Add substantially.

Fig. 1 schematically shows according to an embodiment of the invention for the reading chip of extremely low noise particle detector；

Fig. 2 A and Fig. 2 B schematically shows front end CMOS amplifying circuit according to embodiments of the present invention；

Fig. 3 illustrates filtering wave-shaping circuit according to embodiments of the present invention；

Fig. 4 illustrates JFET equivalent noise analytical structure；

Fig. 5 illustrates the structural representation of CMOS endoparasitism JFET according to embodiments of the present invention；

Fig. 6 schematically shows the most extremely low noise particle detection system.

Specific embodiment

It is described more fully with example embodiment referring now to accompanying drawing.But, example embodiment can be real in a variety of forms Execute, and be not understood as limited to embodiment set forth herein；On the contrary, it is provided that these embodiments make the disclosure by comprehensively with complete Whole, and the design of example embodiment is conveyed to those skilled in the art all sidedly.The most identical reference represents Same or similar part, thus repetition thereof will be omitted.

Additionally, described feature, structure or characteristic can be combined in one or more enforcement in any suitable manner In example.In the following description, it is provided that many details thus provide fully understanding of embodiment of this disclosure.But, It will be appreciated by persons skilled in the art that can put into practice the technical scheme of the disclosure and do not have in specific detail one or more, Or can use other adds speed system, constituent element, material, device, step etc..In other cases, it is not shown in detail or retouches State known features, add speed system, device, realization, material or operation to avoid each side of the fuzzy disclosure.

Fig. 1 schematically shows according to an embodiment of the invention for the reading chip of extremely low noise particle detector.This In alleged extremely low noise particle detector, refer to noise at 10 electronics (10e-) detection below devices, such as without amplification merit The semiconductor detector of energy, such as Si-PIN (silicon positive-intrinsic-negative) detector, SDD (silicon Drift Detector) detector, CZT (cadmium-zinc-teiluride；Cadmium zinc telluride) detector etc., but The invention is not restricted to this.

As it is shown in figure 1, the reading chip 100 for extremely low noise particle detector according to embodiments of the present invention can include Multiple passages (such as, N channel), each passage can include input stage JFET 110 and front end CMOS amplifying circuit 120.According to one A little embodiments, read chip 100 and may also include filtering wave-shaping circuit 130 and current source 140.

As it is shown in figure 1, read the integrated N number of read-out channel of chip 100, there is Simulation scale-up and shape function etc., will detection Device output signal JFET device in sheet receives, then amplifies through front end CMOS amplifying circuit and filter shaping further, Simulation output can be realized.

With reference to Fig. 1, the output signal of input stage JFET 110 receiving pole low noise particle detector.Input stage JFET 110 Source follower mode can be operated in, but the invention is not restricted to this, it is possible to use such as common-source stage to amplify or other forms.Current source 140 can be that JFET 110 provides bias current.Current source 140 can be external current source.

Input stage JFET 110 can be integrated in reading chip 100 by standard CMOS process, and obtains and discrete type The performance that JFET is suitable.Owing to input stage JFET 110 is to be integrated in reading chip 100 by standard CMOS process, therefore also referred to as For parasitic JFET.Front end CMOS amplifying circuit 120 then uses standard CMOS process manufacture.

With reference to Fig. 1, front end CMOS amplifying circuit 120 can couple with described input stage JFET 110, to described output signal It is amplified.The signal of detector output is after input stage JFET 110, and signal parameter does not changes, so needing Connect pre-amplification circuit it to be amplified further.

According to embodiments of the invention, reading chip input stage and use parasitic JFET in CMOS technology, subsequent conditioning circuit uses Standard CMOS device makes, and (noiseproof feature such as 1/f is not to solve the best problem of chip noise performance that reads of pure cmos device Good), eliminate reading circuit volume based on the design of discrete type JFET device bigger, it is difficult to expand to multichannel asking simultaneously Topic.The reading chip of integrated JFET device according to embodiments of the present invention can obtain extremely low noiseproof feature.

Filtering wave-shaping circuit 130 can couple with the outfan of described front end CMOS amplifying circuit 120.Filtering wave-shaping circuit The signals of 130 outputs can be as the criterion gaussian signal, this signal is passed out to chip exterior, can be processed by MCA.

Fig. 2 A and Fig. 2 B schematically shows front end CMOS amplifying circuit according to embodiments of the present invention.

As shown in Figure 2 A and 2B, CMOS amplifying circuit in front end includes cmos amplifier 202 and is coupled to described CMOS amplification Feedback arrangement 204A or 204B between input and the outfan of device.

Front end CMOS amplifying circuit can use Charge sensitive amplifier structure.As shown in Figure 2 A and 2B, feedback arrangement can select Select continuous resetting structure, such as, comprise the feedback resistance R being connected in parallel or the metal-oxide-semiconductor used as resistance and feedback capacity C；Or switching mode resetting structure, such as comprise the switch element K and feedback capacity C being connected in parallel.

According to embodiments of the present invention, the parasitic JFET parameter obtained according to test, the selection of the input pipe of cmos amplifier Can meet following condition:

L=L_min

$W=\frac{C_{in}}{\frac{2}{3}{C}_{ox}L}$

${\mathrm{ENC}}^2\≈\frac{8}{3}{C}_{in}{\mathrm{\πK}}_f(1+\frac{3C_{ov}}{C_{ox}L})$

L is the channel length of described input pipe, and W is the channel width of described input pipe, L_minFor process critical dimension；C_in For the input total capacitance of cmos amplifier, K_fFor 1/f noise coefficient, C_ovFor overlap capacitance density, C_oxFor gate capacitance density, ENC is equivalent noise charge.C_in=C_J+C_p+C_g, be JFET output stage direct-to-ground capacitance, JFET amplifier stage and this grade of wire capacitances, Input metal-oxide-semiconductor grid capacitance sum.Because being low power dissipation design, input pipe bias current can be in hundreds of μ A magnitude, preposition amplification The conversion gain that circuit adds will be at 1 (V/fC).

Fig. 3 illustrates filtering wave-shaping circuit according to embodiments of the present invention.

As it is shown on figure 3, filtering wave-shaping circuit according to embodiments of the present invention can be CR-(RC)ⁿActive filter circuit.Filtering Wave-shaping circuit can form pole-zero cancellation with front end CMOS amplifying circuit.CR-(RC)ⁿThe filter order n of active filter circuit and reaching Peak time can determine according to the combined factors such as noise requirements, power consumption demand.According to some embodiments of the present invention, peak time τ Scope can meet following condition:

$\mathrm{\τ}\≤\frac{10}{A_{px}}\left(\mathrm{\μ}s\right)$

A_pxFor elemental area.

According to an embodiment, as it is shown on figure 3, two stage filter structure can be used: T-shaped filtering+gain is the Sallen-key of 1 Filtering；Curring time scalable.Filter circuit also has certain amplification, about 3m (V/fC).

Obtaining the one of peak time τ by JFET equivalent noise analysis and choose according to embodiments of the present invention is described below Mode so that the series connection white noise of input stage JFET and white noise sum in parallel are minimum.

Fig. 4 illustrates JFET equivalent noise analytical structure.

See Fig. 4,

$\stackrel{\‾}{c_n^2}=\stackrel{\‾}{|c_{n1}+c_{n2}+c_{n3}{|}^2}=\stackrel{\‾}{c_{n1}^2}+\stackrel{\‾}{c_{n2}^2}+\stackrel{\‾}{c_{n3}^2}.$

$\stackrel{\‾}{i_n^2}=\stackrel{\‾}{|i_{n1}+i_{n2}{|}^2}=\stackrel{\‾}{i_{n1}^2}+\stackrel{\‾}{i_{n2}^2}.$

e_n1It is JFET channel noise, e_n2It is the thermal noise caused by transistor biasing resistance Rb and genertor impedance Zs, e_n3It it is the 1/f noise of JFET.

The voltage v of JFET input_n1、v_n2It is represented by:

$\begin{array}{c}\stackrel{\‾}{v_{n1}^2}=\stackrel{\‾}{i_{n1}^2}|Z{|}^2\\ \stackrel{\‾}{v_{n2}^2}=\stackrel{\‾}{i_{n2}^2}|Z{|}^2,\\ Z=\left(R_b\right|\left|Z_s\right|\left|\frac{1}{{\mathrm{j\ωC}}_{in}}\right)=\frac{R_b{Z}_s}{R_b+(1+{\mathrm{jWR}}_b{C}_{in})Z_s}\end{array}$

The noise equivalent voltage u of JFET input stage_inIt is represented by:

$\stackrel{\‾}{u_{in}^2}=\stackrel{\‾}{|e_{n1}+e_{n2}+e_{n3}+u_{n1}+u_{n2}{|}^2}$

Total noise equivalent voltage is represented by:

$\stackrel{\‾}{v_{ins}^2}=\stackrel{\‾}{v_{in}^2}\·|\frac{1}{G_1}{|}^2,G_1=\frac{R_b}{Z_s(1+{\mathrm{j\ωR}}_b{C}_{in})+R_b}$

Equivalent noise charge can be represented simply as:

${\mathrm{ENC}}^2\≈\frac{e_n^2{C}_{in}^2}{\mathrm{\τ}}+{\mathrm{\πC}}_{in}^2{A}_f+\frac{1}{2}{i}_n^2\mathrm{\τ}$

In above formula equivalent noise charge three respectively connect white noise, series connection 1/f noise, white noise in parallel.Wherein It it is noise power spectral density；C_inInput total capacitance, comprise detector electric capacity, input node parasitic capacitance and The gate-source capacitance of input pipe；τ is wave-shaping circuit peak time, and Af is the constant of definition 1/f noise.

By formula it can be seen that series connection white noise reduces with peak time, 1/f noise does not changes with peak time, and White noise in parallel increases along with peak time.In low-frequency range, the noise of JFET mainly comprises series connection white noise and 1/f makes an uproar Sound, at high band, 1/f noise almost can be left in the basket.So noise optimization mainly considers how to select optimum wave-shaping circuit Peak time, so that series connection white noise and white noise sum in parallel are minimum.

The basic parameter side of integrated parasitic JFET in describing acquisition standard CMOS process according to embodiments of the present invention below Method.

Can provide schematic diagram and the domain of normal component in common CMOS technology, its performance parameter is all through authenticator Close process modeling.Parasitic JFET is not belonging to normal component, and the CMOS technology being required for choosing manually is added schematic diagram and sets Meter domain, determines size and the layout of grid in element layout, source class, drain electrode and deep N-well etc. so that it is meet technique mould The properity parameter of type and standard JFET.The parameter of CMOS technology endoparasitism JFET includes: conducting resistance R_on, pinch-off voltage V_off, input capacitance parameter, maximum operating frequency f_max, DC characteristic I-V curve, maximum saturation electric current I_DSS, grid current, hand over Properties of flow mutual conductance G_mAnd RF characteristic, wherein grid current and input capacitance are directly related with low-noise characteristic.Based on standard JFET model, contrasts parasitic JFET device characterisitic parameter, the curve obtained repeatedly, until finding satisfactory JFET device to tie Structure and parameter thereof.Determine and modeling etc. it addition, parameter characteristic under CMOS endoparasitism JFET low temperature also can be carried out.Carry out a series of The simulation comparison of parasitic JFET parameter on standard CMOS process, can obtain parasitic JFET parameter and the model optimized.For selected Technological experiment find suitably parasitic JFET breadth length ratio, and conducting resistance with this understanding, input capacitance, grid current Etc. parameter, use it for reading the design of chip.

Fig. 5 illustrates the structural representation of CMOS endoparasitism JFET according to embodiments of the present invention.

With reference to Fig. 5, input stage JFET is formed in the first conductivity type (p-type or N-type) Semiconductor substrate 502.As it was previously stated, Other cmos circuit structures such as front end CMOS amplifying circuit are also formed in Semiconductor substrate 502.

As it is shown in figure 5, input stage JFET can include that be formed in described first conductive-type semiconductor substrate 502 second leads Electricity type isolation deep trap 504, the second conductivity type and the first conductivity type are contrary, can be N-type or p-type.

First conductivity type bottom gate 506 is formed on described second conductivity type isolation deep trap 504.

Second conductive type of channel district 508 is formed on described first conductivity type bottom gate 506.

First conductivity type top-gated 510 and be positioned at the source/drain electrode 512 of described first conductivity type top-gated 510 both sides and formed On described channel region 508.Between described first conductivity type top-gated 510 and described source/drain electrode 512 by such as shallow slot every Electrically insulate from district (STI) 514.STI compares traditional native oxide isolation, can reduce electrical leak between electrodes stream, make device have There is bigger source-leakage running voltage, keep low conducting resistance Ron simultaneously.

It is formed with the first conduction in the first conductivity type bottom gate 506 both sides on deep trap 504 it addition, isolate at the second conductivity type Type electrical contacts 516, for electrical connection the first conductivity type bottom gate 506, and is electrically coupled to surface bottom gate connection electrode simultaneously 517 to electrically connect with miscellaneous part.Isolate on deep trap 504 in the first conductivity type electrical contacts 516 both sides at the second conductivity type It is formed with the second conductivity type electrical contacts 518, for electrical connection the second conductivity type isolation deep trap 504, and is electrically connected simultaneously To surface extraction electrode 519 to be connected to such as predetermined potential.

With reference to Fig. 5, JFET device noise and input resistance are all low than MOS device, and conducting channel is internal at it, does not exists Cmos device 1/f noise caused by surface or interface.

It addition, raceway groove is enclosed between top-gated and bottom gate, this between top-gated and bottom gate by external connection together Double-grid structure raceway groove can exhaust from top and bottom node simultaneously so that raceway groove pinch-off voltage is lower.Bottom gate/deep trap node energy Enough contribute to obtaining low electric capacity, high-breakdown-voltage parameter.

According to one embodiment of the invention, the anode of detector is connected with the grid of JFET, connects distance the shortest, introducing Stray capacitance is the least, it is to avoid make the noise degradation of whole read-out system.The anode of detector can use with the grid of JFET The connected mode of wire bond (wiring bonding), does not encapsulate reading chip, directly it is connected with detector, pcb board routing, Thus line is apart from short, reduce lead-in wire stray capacitance and encapsulation parasitic capacitance.

According to one embodiment of the invention, input JFET is operated in source class follower pattern, and device is provided biasing by current source Electric current.Under this pattern, JFET device duty can follow the current input signal of change and leakage current adjusts automatically, visits The electric charge that survey device anode is collected is released by grid current, will not cause the stacking of signal.

Fig. 6 schematically shows the most extremely low noise particle detection system, including extremely low noise grain Sub-detector 610 and reading chip 620 described above.Extremely low noise particle detector can include Si-PIN, SDD and CZT Semiconductor detector etc., but the invention is not restricted to this.Reading chip 620 and see description above, here is omitted.

By above detailed description, those skilled in the art it can be readily appreciated that according to the system of disclosure embodiment and Add speed system to have one or more of the following advantages.

According to some embodiments of the present invention, input stage JFET can be integrated in reading chip by standard CMOS process, And obtain the performance suitable with discrete type JFET.

According to some embodiments of the present invention, read chip input stage and use parasitic JFET, subsequent conditioning circuit in CMOS technology Employing standard CMOS device makes, and solve pure cmos device reads the problem that chip noise performance is the best.Meanwhile, eliminate Reading circuit volume based on the design of discrete type JFET device is bigger, it is difficult to expand to multichannel problem.

According to some embodiments of the invention, input JFET is operated in source class follower pattern, and device is provided partially by current source Put electric current.Under this pattern, JFET device duty can follow the current input signal of change and leakage current adjusts automatically, The electric charge that detector anode is collected is released by grid current, will not cause the stacking of signal.

It will be understood by those skilled in the art that accompanying drawing is the schematic diagram of example embodiment, the module in accompanying drawing or process Not necessarily implement necessary to the disclosure, therefore cannot be used for limiting the protection domain of the disclosure.

It will be appreciated by those skilled in the art that above-mentioned each module can be distributed in device according to the description of embodiment, it is possible to It is disposed other than in one or more devices of the present embodiment carrying out respective change.The module of above-described embodiment can be merged into One module, it is also possible to be further split into multiple submodule.

More than it is particularly shown and described the exemplary embodiment of the disclosure.It should be understood that the disclosure is not limited to institute's public affairs The embodiment opened, on the contrary, the disclosure be intended to contain the various amendments comprised in the spirit and scope of the appended claims and etc. Effect is arranged.

Claims (10)

1. the reading chip for extremely low noise particle detector, it is characterised in that described reading chip includes multiple logical Road, each passage includes:

Input stage JFET, the output signal of receiving pole low noise particle detector；

Front end CMOS amplifying circuit, couples with described input stage JFET, is amplified described output signal.

Read chip the most as claimed in claim 1, it is characterised in that described extremely low noise particle detector is without enlarging function Semiconductor detector.

Read chip the most as claimed in claim 1, it is characterised in that described front end CMOS amplifying circuit includes cmos amplifier And it is coupled to the feedback arrangement between input and the outfan of described cmos amplifier.

Read chip the most as claimed in claim 3, it is characterised in that described feedback arrangement includes:

The feedback resistance being connected in parallel and feedback capacity；Or

The switch element being connected in parallel and feedback capacity.

Read chip the most as claimed in claim 3, it is characterised in that the input pipe of described cmos amplifier meets following bar Part:

L=L_min

$W=\frac{C_{in}}{\frac{2}{3}{C}_{ox}L}$

${\mathrm{ENC}}^2\≈\frac{8}{3}{C}_{in}{\mathrm{\πK}}_f(1+\frac{3C_{ov}}{C_{ox}L})$

Wherein L is the channel length of described input pipe, and W is the channel width of described input pipe, L_minFor process critical dimension；C_in For reading the input total capacitance of chip, K_f、C_ov、C_oxFor technique relevant parameter, ENC is equivalent noise charge.

Read chip the most as claimed in claim 1, it is characterised in that also include:

Filtering wave-shaping circuit, couples with the outfan of described front end CMOS amplifying circuit.

Read chip the most as claimed in claim 6, it is characterised in that described filtering wave-shaping circuit is CR-(RC)ⁿActive power filtering Circuit, the peak time of described filtering wave-shaping circuit meets following condition:

$\mathrm{\τ}\≤\frac{10}{A_{px}}\left(\mathrm{\μ}s\right)$

Wherein τ is peak time, A_pxFor elemental area.

Reading chip the most as claimed in claims 6 or 7, it is characterised in that the peak time of described filtering wave-shaping circuit selects Series connection white noise and white noise sum in parallel for making input stage JFET are minimum.

Read chip the most as claimed in claim 1, it is characterised in that described reading chip includes:

First conductive-type semiconductor substrate, described input stage JFET and described front end CMOS amplifying circuit are formed at described quasiconductor On substrate,

Wherein, described input stage JFET includes:

The the second conductivity type isolation deep trap being formed in described first conductive-type semiconductor substrate；

It is formed at the first conductivity type bottom gate on described second conductivity type isolation deep trap；

It is formed at the second conductive type of channel district on described first conductivity type bottom gate；

It is formed at the first conductivity type top-gated on described second conductive type of channel district and is positioned at described first conductivity type top-gated The source/drain electrode of both sides, between described first conductivity type top-gated and described source/drain electrode by shallow trench isolation region carry out electricity every From.

10. an extremely low noise particle detection system, it is characterised in that including:

Extremely low noise particle detector；

Reading chip as described in claim 1-9.