CN106019129B - The test method of DSP embedded inner multiplication device in FPGA - Google Patents
The test method of DSP embedded inner multiplication device in FPGA Download PDFInfo
- Publication number
- CN106019129B CN106019129B CN201610338155.5A CN201610338155A CN106019129B CN 106019129 B CN106019129 B CN 106019129B CN 201610338155 A CN201610338155 A CN 201610338155A CN 106019129 B CN106019129 B CN 106019129B
- Authority
- CN
- China
- Prior art keywords
- test vector
- compressor reducer
- vector collection
- multiplier
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31707—Test strategies
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention belongs to technical field of integrated circuits, the test method of DSP embedded inner multiplication device in specially FPGA.The present invention includes a kind of method that multiplier compressor circuit structure describing mode defined and automatically generated optimal test vector collection, which may be implemented high fault coverage and low testing time.For the multiplier of given coding mode and Partial product compression circuit structure, an optimal test vector collection can be automatically provided.The present invention can be good at completing the test to DSP embedded in FPGA, have the characteristics that test failure coverage rate is high, at low cost, portable good, versatile.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of survey to DSP embedded inner multiplication device in FPGA
Method for testing.
Background technology
With field programmable gate array（Field Programmable Gate Array, FPGA）Application increasingly
Extensively, people are also higher and higher to the performance and capacity requirement of FPGA.By embedded a variety of IP kernels in FPGA, can greatly improve
The performance and application range of FPGA.Therefore, status of the embedded IP kernel in FPGA is more and more important.Wherein DSP is due to its energy
The ability of enough process data at high speeds, is widely embedded in modern FPGA, becomes component part important in FPGA.
DSP embedded is mainly made of adder and multiplier in FPGA.Wherein multiplier is mainly made of two parts,
A part is partial product generation circuit, and another part is Partial product compression circuit.Partial product compression circuit will be after Partial product compression
Finally generate output of two partial products as multiplier.Two partial products that adder exports multiplier, which are added, to be generated finally
Result.The method generated for the high coverage rate test vector of adder has had very much.Proposing one kind in document [1] has
The test vector of effect generates scheme method, and to the carry lookahead adder of N inputs, it only needs 2N+2 test vector real
Existing 100% fault coverage, the test method of this adder can apply the adder portion of the DSP embedded in FPGA
The test [2] divided.However, for the multiplier of DSP embedded in FPGA, due to its it is complicated flexibly and input bit wide compared with
Greatly, difficulty is brought to test.It is for inputThe multiplier of position is then needed according to Black-box Testing methodA survey
Examination vector, testing time are long.Therefore, find a kind of efficient multiplier test method be very it is necessary to.
Common partial product generation circuit mainly has Booth coding circuits in multiplier, is encoded based on Booth and is developed again
The improved various Booth coding modes [3] such as Booth2 and Booth4 are gone out, they can greatly reduce part in coding
Product.In order to improve the performance of Partial product compression circuit, frequently with array structure to Partial product compression.Wherein mainly there is regular pressure
Two class of contracting array and irregular array, wherein irregular array is again most commonly seen [4] with Wallace tree constructions.Wherein it is used for group
At the compressor reducer of array structure other than traditional full adder and half adder, also 4-2 compressor reducers, 7-3 compressor reducers, 11-4 compressions
Device etc..When designing multiplier, according to requirements such as the input bit wide knead dough product of multiplier, speed, different compressions can be selected
Device so that the compressed tree best performance of structure.
Test for array structure circuit, cell fault model（Cell Fault Model）[5] it is a kind of common
Fault model.To reduce the quantity of test vector collection, the common point method of one kind is to use cyclic vector [6].For input data
End, it only need to be to preceding0 to 11 ... 1 traversals that position is carried out from 00 ..., and it is nextBefore position repeatsThe excitation vector of position,
As shown in Figure 1.WhenIt is notMultiple when, it is last remainingBefore position can repeatBefore positionPosition.Its
InReferred to as length of the cycle, the key using the strategy are to find optimal length of the cycle.Document [6] analyzes Booth2 codings
Two input terminals of multiplierWith optimal test vector collection situation when taking 4, mainly by regular array multiplier
Structure is analyzed, and it is highly effective to demonstrate this test vector to apply strategy.Using this method,Booth2 is compiled
The test failure coverage rate of the regular array structure multiplier of code does not account for other Booth up to 99% or more in [6]
The case where coding, and this method is only applicable to the case where Partial product compression circuit is made of full adder and half adder.Based on unit
Model and cyclic policy, propose in document [7] a kind of BIST of the Wallace tree multipliers encoded for Booth2 test to
Quantity set generates scheme.However, document [7] in propose test method remain for only full adder and half adder composition
Wallace tree constructions, for using the Wallace tree constructions of 4-2 compressor reducers, 7-3 compressor reducers, 11-4 compressor reducers [8] [9] etc. to be
It cannot achieve the test of high coverage rate.
For it is different encode, the multiplier of different topological structures, it is excessively complicated by manual analyzing length of the cycle, need
There is a kind of new method to automatically determine suitable length of the cycle.This method not only can provide conjunction to regular array multiplier
Suitable test vector collection, moreover it is possible to be suitable for the structure of various complexity including irregular array structure and various compressor reducers and
Coding circuit.The vector set makes under the premise of there are certain requirements to test coverage so that the testing time is as small as possible, and
Hardware consumption needed for BIST circuit is smaller.
Bibliography：
[1]Nikolos D G, Nikolos D, Vergos H T, et al. An efficient BIST
scheme for high-speed adders[C]//null. IEEE, 2003: 89.
[2]Gizopoulos D, Paschalis A, Zorian Y. An effective built-in self-
test scheme for parallel multipliers[J]. Computers, IEEE Transactions on,
1999, 48(9): 936-950.
[3]Javeed K, Wang X. Radix-4 and radix-8 booth encoded interleaved
modular multipliers over general F p[C]//Field Programmable Logic and
Applications (FPL), 2014 24th International Conference on. IEEE, 2014: 1-6.
[4]Wallace C S. A suggestion for a fast multiplier[J]. Electronic
Computers, IEEE Transactions on, 1964 (1): 14-17.
[5]Elhuni H, Vergis A, Kinney L. C-testability of two-dimensional
iterative arrays[J]. Computer-Aided Design of Integrated Circuits and
Systems, IEEE Transactions on, 1986, 5(4): 573-581.
[6]Gizopoulos D, Paschalis A, Zorian Y. An effective built-in self-
test scheme for parallel multipliers[J]. Computers, IEEE Transactions on,
1999, 48(9): 936-950.
[7]Gizopoulos D, Paschalis A, Zorian Y. Effective built-in self-test
for Booth multipliers[J]. IEEE Design & Test of Computers, 1998 (3): 105-111.
[8]United States Patent, US7467175B2 Programmable logic device with
pipelined DSP slices
[9]Asif S, Kong Y. Analysis of different architectures of counter
based Wallace multipliers[C]//Computer Engineering & Systems (ICCES), 2015
Tenth International Conference on. IEEE, 2015: 139-144。
Invention content
Pair that the purpose of the present invention is to provide a kind of portabilities is good, fault coverage is high, at low cost, versatile
The test method of DSP embedded inner multiplication device in FPGA.This method allows user to retouch tested multiplier architecture with one
State the form input of file.Multiplier architecture is provided according to user, the present invention can automatically provide a high fault coverage and low
The test vector collection of testing time.
In the present invention, it is based on CFM and circulation model, for two input terminals X and Y of multiplier, if its length of the cycle point
It is notWith.To obtain optimal test vector collection, core of the invention is that searching is optimalWithValue.
Due to the flexible structure of Partial product compression circuit, the Partial product compression circuit of DSP multipliers is tested required for user
Configurations, in order to meet the testing requirement of different type compressor circuit, user provides the required multiplier architecture tested,
And it is expressed in the form of one describes file.It can be any netlist that can completely describe compressor circuit structure that this, which describes file,
File, the present invention extract compressor circuit structural information using corresponding netlist parsing module.For the ease of extraction compressor reducer
Essential information, the present invention are illustrated by taking the form of compressed tree structure description file shown in Fig. 2 as an example.According to format shown in table 1
Specification can describe any structure for thinking compressed tree in multiplier to be tested.In table 1, the first row be used for state one newly
Compressor reducer.The essential attribute of 2-8 behavior compressor reducers, including its ID, input bit wide, output bit wide, it is in compressed tree
The type of compressor reducer ID and the compressor reducer that position, output data are transferred to.Wherein each compressor reducer has unique ID.9-
12 rows are to be able to more flexible structure compressed tree and define, it includes allowing a certain position of compressor reducer is constant to connect 1 or permanent
Surely 0 is connect, for the input of sign extended processing, and the temporary position not handled.These, which set, makes application of the invention more
Flexibly, to be suitable for various compression tree constructions.
The present invention is to determine optimal test vector collection, defines a cost function.The function need to consider user couple event
Hinder the requirement of the lower limit of coverage rate.After fault coverage is less than certain value, even if test vector is seldom, user can not be met
Requirement to test.Therefore it is as follows to define cost function：
（1）
Wherein,, reflect the size of test vector collection.It is the minimum failure covering that user requires
Rate,BeFault coverage under test vector collection.ThereforeWithIt is relevant, that is, in each correspondence
Test vector collectionAfter being applied in circuit, all there are one corresponding fault coverages, under normal circumstances,'s
Value withIncrease and increase.After test set is applied to input terminal, if the fault coverage of circuit is less than required
Minimum fault coverage, then be calculatedAs a result it is negative.Result of calculation is the vector set born, because being unsatisfactory for
User demand will be rejected.?Under the premise of just, with test vector collectionIncrease,It will become larger；And with
Test coverageIncrease,It can reduce.Value isWith（-）Ratio, reflect test
The size of vector set increases and increased speed with fault coverage.Therefore,Test is reflected for the minimum value of timing
The growth of vector set size with the growth rate minimum of fault coverage situation.In the case so that test vector collection
Small as far as possible and fault coverage is high as far as possible.
Based on the above analysis, the test method to multiplier in DSP embedded in FPGA proposed in the present invention, algorithm
Flow is as shown in Fig. 2, be as follows：
（1）User provides the required multiplier architecture tested, and is expressed in the form of one describes file.This describes file
Can be any net meter file that can completely describe compressor circuit structure, including multiplier architecture information：Compressed tree knot
Structure description, coding mode, multiplier X and Y input terminals bit wide and compressed tree height and user to fault coverage requirement；
（2）Netlist parses：The compressed tree structure description file provided user parses, by each compressor reducer knot in file
Data transmission relations information extracts between structure information and compressor reducer；
（3）Compressed tree is built：According to the compressor reducer information extracted, corresponding compressor reducer node is built, and according to compression
Data transmission relations between device establish the connection between node, the connection relation one of compressor reducer nodes all in this way and they
It rises and constitutes a compressed tree；
（4）The generation of test vector collection：According to multiplier X and Y the input terminal bit wide that user provides, traversal is all possible
Length of the cycle, and strategy is generated according to loop test vector（I.e. Fig. 1 is provided）, generate test corresponding to each length of the cycle to
Quantity set；
（5）Coding：The coding mode specified according to user, to generating test vector step（4）The test vector of generation into
Row coding, and the partial product generated after coding is sent in compressed tree；
（6）Data update records：First layer compressor reducer, which receives, in compressed tree passes through coding step（5）Data, first layer
Each compressor reducer record the input data that its input terminal receives, then according to the type of itself and input data, calculate defeated
Go out data, and the data of output are sent into next stage compressor reducer.Similarly, the compressor reducer of the second layer receives the defeated of first layer compressor reducer
Go out data and processed data are passed into next layer.In this way, data are transmitted layer by layer, until being transferred to lowermost layer；
（7）Fault coverage calculates：After the completion of institute's directed quantity applies in vector set, according to fault coverage in CFM
Definition, calculates the cell failure coverage rate under the test vector collection；
（8）As a result it verifies：It tests to the output result of multiplier, if output result and the input being directly calculated
Data product is unequal, generation error report；Conversely, if output result is correct, continue to run with；If having traversed all cycles to grow
Degree, then carry out the selection of optimal test vector collection, otherwise, returns and generates test vector collection step（4）；
（9）Optimal test vector collection selection：After all lengths of the cycle are traversed, pass through and count different test vectors
Fault coverage under collection, in conjunction with the requirement for the fault coverage that user provides, according to cost function（1）Formula calculates all follow
Ring length is correspondingValue.MinimumValue corresponding toWithValue, as optimal length of the cycle, this is followed
Test vector collection corresponding to ring length is exactly optimal test vector collection.
Need compression tree construction to be tested for user, by above-mentioned algorithm flow, can provide a high coverage rate and
The test vector collection of low testing time.
Technique effect
To all kinds of multipliers, the present invention can provide a high coverage rate and the small test vector collection of test vector collection.
User only needs according to certain format description compression tree construction, and program can provide an optimal test vector collection.The party
Method has the characteristics that portability is good, at low cost, scalability is strong, unrelated with gate level circuit.
Description of the drawings
Fig. 1 is that test vector generates strategy.
Fig. 2 is test vector collection generating algorithm flow chart.
Fig. 3 is the description example of a 7-3 compressor reducer.
Specific implementation mode
For the multiplier of various structures, the present invention can provide the test vector collection of a high coverage rate.With document [8]
In a kind of FPGA of middle proposition in DSP embeddedFor multiplier architecture.Its multiplier proposed is to use
The multiplier of the Wallace tree constructions of Booth2 codings, and its compressed tree is complicated.The compressor reducer for constituting compressed tree has half to add
Device, 11-4 compressor reducers, 7-3 compressor reducers, 4-2 compressor reducers and 3-2 compressor reducers.For the multiplier, the specific embodiment party of the present invention
Formula is as follows：
Firstly, it is necessary to describe the structure of Wallace trees in multiplier according to format of the presently claimed invention.It is given according to table 1
The compressor reducer descriptor format gone out describes compressor reducer all in compressed tree.It is retouched for example, having given a 7-3 compressor reducer in Fig. 3
The example stated.After the completion of all compressor reducer descriptions, compressor reducer is described into file and is inputted as one.Since the multiplier uses
Be Booth2 coding, therefore coded portion selection Booth2 coding.Bit wide will be inputtedIt is defeated with compressed tree height 4
Enter, and takes minimum fault coverage empirical value 97%.
By parsing the compressed tree description scheme of input, a node is created to each compressor reducer defined in it, and
The information of compressor reducer is stored in node.Each node is connected according to the data transfer relationship between node, constitutes compression
Tree.[6] it proposes, when length of the cycle is more than 3, to realize the fault coverage for Booth2 encoders 100% in.Therefore,
The value of length of the cycle can traverse it is all be more than 3 value.After the application of each vector set, oneself input terminal of each nodes records receives
All inputs various combination.After product test, the fault coverage under each vector set is calculated and by cost equation
Calculate the cost under each test vector collection.Choose a minimum test vector collection of cost and output report.
It can be obtained using this method：When X and Y input terminals length of the cycle is 9 and 6 respectively so that test vector collection is most
Measure it is small in the case of realize high fault coverage.At this point, the size of test vector collection is, the failure under this vector set
Coverage rate is 99.47%.Compared to based on exhaustive Black-box Testing method, the size of test vector collection fromIt is reduced to。
It is especially convenient that the present invention realizes in FPGA, has the characteristics that testing cost is low, portable good, versatile；
It can be used for the test of other embedded multipliers.
Table 1
。
Claims (2)
1. a kind of test method to DSP embedded inner multiplication device in FPGA is based on CFM and circulation model, for multiplier
Two input terminals X and Y, if its length of the cycle is respectivelyWith, to obtain optimal test vector collection, core is that searching is optimal
'sWithValue；For this purpose, defining a cost function：
（1）
Wherein,, the size of test vector collection is reflected,It is the minimum failure covering that user requires
Rate,BeFault coverage under test vector collection, which is characterized in that test method is as follows：
（1）User provides the required multiplier architecture tested, and is expressed in the form of one describes file；It is to appoint that this, which describes file,
What can completely describe the net meter file of compressor circuit structure, including multiplier architecture information：It compresses tree construction description, compile
Code mode, multiplier X and Y input terminals bit wide and compressed tree height and user to fault coverage requirement；
（2）Netlist parses：The compressed tree structure description file provided user parses, and each compressor configuration in file is believed
Data transmission relations information extracts between breath and compressor reducer；
（3）Compressed tree is built：According to the compressor reducer information extracted, build corresponding compressor reducer node, and according to compressor reducer it
Between data transmission relations establish the connection between node, compressor reducer nodes all in this way and their connection relation structure together
At a compressed tree；
（4）The generation of test vector collection：According to multiplier X and Y the input terminal bit wide that user provides, all possible cycle is traversed
Length, and strategy is generated based on loop test vector, generate the test vector collection corresponding to each length of the cycle；
（5）Coding：The coding mode specified according to user, to generating test vector step（4）The test vector of generation is compiled
Code, and the partial product generated after coding is sent in compressed tree；
（6）Data update records：First layer compressor reducer, which receives, in compressed tree passes through coding step（5）Data, first layer it is every
A compressor reducer records the input data that its input terminal receives, and then according to the type of itself and input data, calculates output number
According to, and the data of output are sent into next stage compressor reducer；Similarly, the compressor reducer of the second layer receives the output number of first layer compressor reducer
Next layer is passed to according to and by processed data；In this way, data are transmitted layer by layer, until being transferred to lowermost layer；
（7）Fault coverage calculates：After the completion of institute's directed quantity applies in vector set, according to the definition of fault coverage in CFM,
Calculate the cell failure coverage rate under the test vector collection；
（8）As a result it verifies：It tests to the output result of multiplier, if output result and the input data being directly calculated
Product is unequal, generation error report；Conversely, if output result is correct, continue to run with；If having traversed all lengths of the cycle,
The selection of optimal test vector collection is then carried out, otherwise, returns and generates test vector collection step（4）；
（9）Optimal test vector collection selection：After all lengths of the cycle are traversed, by counting under different test vector collection
Fault coverage, in conjunction with the requirement for the fault coverage that user provides, according to cost function（1）Formula calculates all cycle length
It spends correspondingValue；MinimumValue corresponding toWithValue, as optimal length of the cycle, which grows
Spend the test vector collection that corresponding test vector collection is exactly optimal.
2. test method according to claim 1, which is characterized in that the net meter file format of the compressor circuit structure is advised
Model is as shown in table 1；Wherein, the first row is for stating a new compressor reducer；The essential attribute of 2-8 behavior compressor reducers, including
The compressor reducer ID and the compression that its ID, input bit wide, output bit wide, its position in compressed tree, output data are transferred to
The type of device, wherein each compressor reducer has unique ID；9-12 rows include allowing a certain position of compressor reducer is constant to connect 1 or constant
0 is connect, for the input of sign extended processing, and the temporary position not handled；
Table 1
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610338155.5A CN106019129B (en) | 2016-05-22 | 2016-05-22 | The test method of DSP embedded inner multiplication device in FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610338155.5A CN106019129B (en) | 2016-05-22 | 2016-05-22 | The test method of DSP embedded inner multiplication device in FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106019129A CN106019129A (en) | 2016-10-12 |
| CN106019129B true CN106019129B (en) | 2018-11-13 |
Family
ID=57096155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610338155.5A Active CN106019129B (en) | 2016-05-22 | 2016-05-22 | The test method of DSP embedded inner multiplication device in FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106019129B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771960A (en) * | 2016-11-18 | 2017-05-31 | 天津大学 | The generation of local test vector and optimization method based on ring oscillator network |
| CN110362292B (en) * | 2019-07-22 | 2022-12-20 | 电子科技大学 | Approximate multiplication method and approximate multiplier based on approximate 4-2 compressor |
| CN111025133B (en) * | 2019-10-24 | 2022-02-22 | 北京时代民芯科技有限公司 | Test method of second-order Booth coding Wallace tree multiplier circuit |
| CN111966323B (en) * | 2020-08-18 | 2022-09-13 | 合肥工业大学 | Approximate multiplier based on unbiased compressor and calculation method |
| CN112597009B (en) * | 2020-12-15 | 2024-04-02 | 北京时代民芯科技有限公司 | FPGA embedded PCIExpress IP core mass production test optimization method based on coverage rate sequencing |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1556466A (en) * | 2004-01-09 | 2004-12-22 | 上海交通大学 | Partial integrated compression tree generating method based on mixed compression structure |
| CN101482808A (en) * | 2009-01-23 | 2009-07-15 | 清华大学 | 7:2 compressor used for large number multiplier |
| CN101739231A (en) * | 2010-01-04 | 2010-06-16 | 西安电子科技大学 | Booth-Wallace tree multiplier |
| CN102722352A (en) * | 2012-05-21 | 2012-10-10 | 华南理工大学 | Booth multiplier |
| CN106508019B (en) * | 2010-07-08 | 2014-02-05 | 西北工业大学 | A kind of direct output intent of Eulerian angles based on angular velocity and FPGA |
-
2016
- 2016-05-22 CN CN201610338155.5A patent/CN106019129B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1556466A (en) * | 2004-01-09 | 2004-12-22 | 上海交通大学 | Partial integrated compression tree generating method based on mixed compression structure |
| CN101482808A (en) * | 2009-01-23 | 2009-07-15 | 清华大学 | 7:2 compressor used for large number multiplier |
| CN101739231A (en) * | 2010-01-04 | 2010-06-16 | 西安电子科技大学 | Booth-Wallace tree multiplier |
| CN106508019B (en) * | 2010-07-08 | 2014-02-05 | 西北工业大学 | A kind of direct output intent of Eulerian angles based on angular velocity and FPGA |
| CN102722352A (en) * | 2012-05-21 | 2012-10-10 | 华南理工大学 | Booth multiplier |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106019129A (en) | 2016-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106019129B (en) | The test method of DSP embedded inner multiplication device in FPGA | |
| Lv et al. | Efficient Gröbner basis reductions for formal verification of Galois field arithmetic circuits | |
| Yu et al. | Fast algebraic rewriting based on and-inverter graphs | |
| Cai et al. | A complete dichotomy rises from the capture of vanishing signatures | |
| Pruss et al. | Equivalence verification of large Galois field arithmetic circuits using word-level abstraction via Gröbner bases | |
| Rintanen | Symmetry Reduction for SAT Representations of Transition Systems. | |
| Lin et al. | Counting spanning trees in self-similar networks by evaluating determinants | |
| CN106775577B (en) | A kind of design method of the non-precision redundant manipulators multiplier of high-performance | |
| Davis et al. | A practical reconfigurable hardware accelerator for Boolean satisfiability solvers | |
| Filmus et al. | Towards an understanding of polynomial calculus: New separations and lower bounds | |
| Bläser et al. | Deterministically testing sparse polynomial identities of unbounded degree | |
| Moore | The proper forcing axiom | |
| Mayer | Periodic sequences of p-class tower groups | |
| Xu et al. | Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps | |
| Liew et al. | Verifying properties of bit-vector multiplication using cutting planes reasoning | |
| Mukherjee et al. | Equivalence checking using trace partitioning | |
| CN110458277A (en) | The convolution hardware configuration of configurable precision suitable for deep learning hardware accelerator | |
| Hahanov et al. | Qubit description of the functions and structures for computing | |
| Zhang et al. | An efficient method for testing multipliers of embedded DSPs in FPGA | |
| Netzer et al. | QHDL: A low-level circuit description language for quantum computing | |
| Raghava et al. | Design-Space Exploration of Multiplier Approximation in CNNs | |
| Franz et al. | A constructive enumeration of meanders | |
| Shen et al. | Synthesizing complementary circuits automatically | |
| Burns et al. | Spiraling in on speed-ups of genetic algorithm solvers for coupled non-linear ODE system parameterization and DNA code word library synthesis | |
| Baartse et al. | Topics in real and complex number complexity theory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |