CN105990898A - Parallel UPS (Uninterruptible Power Supply) system and phase lock method and device - Google Patents
Parallel UPS (Uninterruptible Power Supply) system and phase lock method and device Download PDFInfo
- Publication number
- CN105990898A CN105990898A CN201510065250.8A CN201510065250A CN105990898A CN 105990898 A CN105990898 A CN 105990898A CN 201510065250 A CN201510065250 A CN 201510065250A CN 105990898 A CN105990898 A CN 105990898A
- Authority
- CN
- China
- Prior art keywords
- ups
- bypass circuit
- output
- voltage signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a parallel UPS system and a phase lock method and device, and aims at solving the problems that a present phase lock manner causes secondary oscillation of the phase of the parallel UPS system when a phase lock host is changed abruptly. The parallel UPS system comprises multiple UPSs, and the first UPS comprises a secondary bypass circuit and a control processor; when a first bypass circuit is normal, the control processor enables that signals related to voltage signals output by the first bypass circuit are transmitted to a parallel bus via second bypass circuits; when output of the first UPS is output of a rectification and inversion circuit and the first bypass circuit is abnormal, the control processor enables that voltage signals of the parallel bus are transmitted to the first UPS via the second by pass circuits; and the second bypass circuits of the UPSs of the parallel UPS system are connected via the parallel bus.
Description
Technical field
The present invention relates to electric and electronic technical field, particularly relate to a kind of parallel uninterrupted power source system, phase-locked
Method and device.
Background technology
At present, possesses the uninterrupted power source (UPS, Uninterruptible Power Supply) of also function power
Because of all many advantages while fast development, some drawbacks of its own the most gradually come out
, as slack-off in stable state and bad dynamic performance, phase locked track accuracy and speed etc..Due to online parallel connection
UPS needs power at bypass supply and switch between inverter power supply, in order to realize steady, reliable and
Uninterrupted switching, needs to realize the inversion in each UPS in ups system in parallel by genlock
Device output voltage is Tong Bu with bypass voltage therein.
Synchronization phase-locked control completes following functions: bypass supply frequency and amplitude in UPS meet requirement
Time, the frequency of the inverter output voltage in this UPS to be followed the tracks of the frequency of bypass supply in this UPS, is somebody's turn to do
The phase place of the inverter output voltage in UPS to follow the tracks of the phase place of bypass supply in this UPS, and requirement
Phase-locked link can not produce high frequency components to redundancy UPS in parallel UPS system and cause parallel UPS system
Current-sharing effect is deteriorated and even produces machine accident of delaying.When the main frame in the ups system that UPS is in parallel,
And the bypass supply in this UPS is when quickly detecting abnormal or bypass power-off, the inverter in this UPS is wanted solely
On the spot carry out phase angle, amplitude and FREQUENCY CONTROL；The voltage of the inverter output in this UPS is following the tracks of side
Between road power supply and independent control during switching, it is desirable to the frequency change of the inverter output voltage in this UPS
Steadily to occur without and acutely to shake and rapid.
But existing phase-lock mode main frame break down cause slave to change time, can make and machine UPS
System phase occurs secondary to vibrate because of changing phase-locked main frame suddenly, wherein, when main frame breaks down,
There is vibration for the first time in the phase place of system, after determining new main frame, and machine ups system to lock newly
Main frame generate power frequency synchronizing signal, the phase place of system can be vibrated again.Meanwhile, existing phase-locked
Mode will be through the phase-locked link of two-stage: first main frame wants local oscillator to generate system voltage fixed phase, digital processing
Device generates power frequency synchronizing signal, then, main frame and will lock power frequency from machine according to system voltage fixed phase
Synchronizing signal produces the machine Voltage Reference phase place, this can increase phase-locked error, and this is unfavorable for and machine UPS
It is interrupted switching.
In sum, existing phase-lock mode main frame break down cause slave to change time, can make also
Machine ups system phase place occurs secondary to vibrate because of changing phase-locked main frame suddenly.
Summary of the invention
Embodiments provide a kind of parallel uninterrupted power source system, phase-lock technique and device, in order to solve
Certainly use existing phase-lock mode when slave changes, can make and machine ups system phase place is because suddenly
The problem changing phase-locked main frame and occur secondary to vibrate.
Based on the problems referred to above, a kind of parallel UPS system that the embodiment of the present invention provides, including multiple UPS,
Wherein, a UPS includes the first bypass circuit, the first switch, rectification inverter circuit and second switch；
When described first switch Guan Bi, described second switch disconnect, a described UPS is output as described the
The output of one bypass circuit, described first switching off, described second switch Guan Bi time, described first
UPS is output as the output of described rectification inverter circuit；A described UPS is in parallel UPS system
Any one UPS；
A described UPS also includes the second bypass circuit and controls processor；Described control processor,
When described first bypass circuit is normal, control relevant to the voltage signal of described first bypass circuit output
Signal is transferred to by described second bypass circuit and in machine bus；And be output as at a described UPS
When the output of described rectification inverter circuit and described first bypass circuit exception, control in described also machine bus
Voltage signal be transferred to a described UPS by described second bypass circuit；
The second bypass circuit in each UPS in parallel UPS system is connected to by described and machine bus
Together.
The phase-lock technique of a kind of parallel UPS system that the embodiment of the present invention provides, including:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
The first bypass circuit abnormal；
Determine that the second bypass circuit in a described UPS is normal；
Follow the tracks of described second bypass circuit；
Determine frequency and the phase place of the voltage signal that a described UPS obtains from described and machine bus；
Frequency according to the voltage signal obtained and phase place, determine the signal of a described UPS output.
The phase-locking device of a kind of parallel UPS system that the embodiment of the present invention provides, including:
First determines module, is used for when a UPS is output as the output of described rectification inverter circuit,
Determine that the first bypass circuit in a described UPS is abnormal；And determine that second in a described UPS is other
Road circuit is normal；
Tracking module, is used for following the tracks of described second bypass circuit；
Second determines module, for determining the voltage letter that a described UPS obtains from described and machine bus
Number frequency and phase place；And according to the frequency of voltage signal obtained and phase place, determine a described UPS
The signal of output.
The beneficial effect of the embodiment of the present invention includes:
A kind of parallel UPS system, phase-lock technique and the device that the embodiment of the present invention provides, due to parallel UPS
Each UPS in system also includes the second bypass circuit, each UPS the first bypass electricity in self
When road is normal, can be by other by second in self for the voltage signal of the first bypass circuit output in self
Road circuit transmission to and machine bus on, and the commutation inversion that each UPS is in self is output as self
When the output of circuit and the first bypass circuit exception in self, can follow the tracks of and machine bus on voltage letter
Number, so, as long as parallel UPS system having first bypass circuit of a UPS normally, and machine bus
On voltage signal be exactly normal, each UPS in parallel UPS system just can follow the tracks of in self
Second bypass circuit, therefore, main frame in parallel UPS system is abnormal, change main frame time, and machine bus
On voltage signal be unaffected, therefore, in parallel UPS system, each UPS will not be because of replacing
Phase-locked main frame and occur secondary to vibrate.
Accompanying drawing explanation
One of structural representation of parallel UPS system that Fig. 1 provides for the embodiment of the present invention；
The two of the structural representation of the parallel UPS system that Fig. 2 provides for the embodiment of the present invention；
The three of the structural representation of the parallel UPS system that Fig. 3 provides for the embodiment of the present invention；
A UPS in the parallel UPS system that Fig. 4 provides for the embodiment of the present invention determines a UPS
In the flow chart of the second bypass circuit whether normal method；
One of flow chart of phase-lock technique of parallel UPS system that Fig. 5 provides for the embodiment of the present invention；
The two of the flow chart of the phase-lock technique of the parallel UPS system that Fig. 6 provides for the embodiment of the present invention；
The three of the flow chart of the phase-lock technique of the parallel UPS system that Fig. 7 provides for the embodiment of the present invention；
The four of the flow chart of the phase-lock technique of the parallel UPS system that Fig. 8 provides for the embodiment of the present invention；
The structure chart of the phase-locking device of the parallel UPS system that Fig. 9 provides for the embodiment of the present invention.
Detailed description of the invention
A kind of parallel UPS system, phase-lock technique and the device that the embodiment of the present invention provides, if parallel UPS
The first bypass circuit having a UPS in system is normal, and the voltage signal in machine bus is exactly normal,
Each UPS in parallel UPS system just can follow the tracks of the second bypass circuit in self, therefore, in parallel
Main frame in ups system is abnormal, change main frame time, and the voltage signal in machine bus is unaffected,
Therefore, in parallel UPS system, each UPS will occur secondary to vibrate because changing phase-locked main frame.
Below in conjunction with Figure of description, a kind of parallel UPS system that the embodiment of the present invention is provided, phase-locked
The detailed description of the invention of method and apparatus illustrates.
A kind of parallel UPS system that the embodiment of the present invention provides, as it is shown in figure 1, include multiple UPS,
Wherein, a UPS includes first bypass circuit the 11, first switch 12, rectification inverter circuit 13 and second
Switch 14；When the first switch 12 Guan Bi, second switch 14 disconnect, a described UPS is output as
The output of the first bypass circuit 11, when the first switch 12 disconnection, second switch 14 close, described the
One UPS is output as the output of rectification inverter circuit 13；A described UPS is in parallel UPS system
Any one UPS；
A described UPS also includes the second bypass circuit 15 and controls processor 16；Control processor
16, when the first bypass circuit 11 is normal, control relevant to the voltage signal of the first bypass circuit 11 output
Signal by the second bypass circuit 15 be transferred to and machine bus 17 on；And defeated at a described UPS
Go out for the output of described rectification inverter circuit 13 and the first bypass circuit 11 abnormal time, control and machine bus
Voltage signal on 17 is transferred to a described UPS by the second bypass circuit 15；
The second bypass circuit 15 in each UPS in parallel UPS system is connected by also machine bus 17
Together.
So, when the first bypass circuit in the UPS in parallel UPS system is normal, this UPS follows the tracks of
The first bypass circuit in self, and the second bypass circuit in this UPS can be by first in this UPS
The signal of bypass circuit output is transferred to and in machine bus, therefore, if in parallel UPS system
When the first bypass circuit in UPS is normal, the abnormal UPS of the first bypass circuit just can follow the tracks of in self
The second bypass circuit, the signal of the second bypass circuit derives from and machine bus.Therefore, parallel UPS is worked as
Main frame in system is abnormal, when changing phase-locked main frame, the change of main frame does not interferes with and letter in machine bus
Number, therefore, in parallel UPS system, each UPS will occur secondary to vibrate because changing phase-locked main frame.
Further, a kind of parallel UPS system that the embodiment of the present invention provides, as in figure 2 it is shown, second
Bypass circuit includes the first transformator T1, the second transformator T2, the 3rd switch the 151, the 4th switch 152
With wave filter 153；
One end of the primary side winding of the first transformator T1 connects the input of the first bypass circuit 11, and first becomes
The other end of the primary side winding of depressor T1 connects the outfan of the first bypass circuit 11, the first transformator T1
One end of vice-side winding 151 be connected with one end of the primary side winding of the second transformator T2 by the 3rd switch,
The other end of the vice-side winding of the first transformator T1 and the other end phase of the primary side winding of the second transformator T2
Even, one end ground connection of the vice-side winding of the second transformator T2, another of the vice-side winding of the second transformator T2
Hold to be connected by the 4th switch 152 and wave filter 153 and control processor 16；
In one end connection of the primary side winding of the second transformator T2 machine bus 17 one, the second transformator
The other end of the primary side winding of T2 connects and another in machine bus 17；
The signal obtained from also machine bus 17 by the second transformator T2 is filtered by wave filter 153,
Only output frequency is the signal of power frequency；
Controlling processor 16 to be additionally operable to, the signal output power frequency according to receiving from wave filter 153 synchronizes letter
Number.
Due in UPS control processor can the first bypass circuit exception in self time, according to from
The signal output power frequency synchronizing signal that described wave filter receives, therefore, UPS has only to lock control and processes
The power frequency synchronizing signal of device output thus produce voltage and the phase place of this UPS, i.e. have only to carry out the
Secondary latch mutually, generates system without signal or the local oscillator further according to the first bypass circuit output
Send power frequency synchronizing signal at DSP pin after voltage reference signal, i.e. carry out the first order phase-locked, so,
As long as the parallel UPS system that the embodiment of the present invention provides is phase-locked by one-level, this improves the lock of system
Phase precision, thus improve the dynamic of parallel UPS system and steady-state behaviour.
Further, a kind of parallel UPS system that the embodiment of the present invention provides, as it is shown on figure 3, described
Second bypass circuit also includes the first resistance R1；
One end of the vice-side winding of the first transformator T1 is by the 3rd switch 151 and the first resistance R1 and second
One end of the primary side winding of transformator T2 is connected；Or, the other end of the vice-side winding of the first transformator T1
It is connected by the other end of the first resistance R1 and the primary side winding of the second transformator T2.
Owing to the signal of the first bypass circuit output in each UPS in parallel UPS system can be the poorest
Different, therefore, the first resistance R1 in the second bypass circuit in each UPS in parallel UPS system
Resistance also take different values, so so that each UPS is coupled by the second bypass circuit of self
Signal in also machine bus is identical.
Further, at the control in a UPS in the parallel UPS system that the embodiment of the present invention provides
Reason device is determining that a described UPS is output as the output of described rectification inverter circuit and described first side
After the circuit abnormality of road, the voltage signal controlled in described also machine bus is transmitted by described second bypass circuit
Before a described UPS, determine that described second bypass circuit is normal.
Alternatively, as shown in Figure 4, described control processor uses following steps to determine described second bypass electricity
Road is normal；
S401, determine that described second bypass circuit is transferred to the virtual value of the voltage signal of a described UPS；
I.e. determine that wave filter exports to the virtual value of the voltage signal controlling processor；
S402, judge that the virtual value of described voltage signal is whether more than threshold voltage；The most then perform S403；
Otherwise, S407 is performed；
S403, calculate the peak value of described voltage signal according to the virtual value of described voltage signal；
S404, obtain the cosine value of the phase angle of described voltage signal according to described voltage signal, and will obtain
The cosine value of phase angle is multiplied with the peak value of described voltage signal and obtains reference value；
S405, the second bypass circuit calculated in described reference value and a described UPS are transferred to described the
The voltage difference of the voltage signal of one UPS；
S406, judge that described voltage difference is whether more than error threshold；If so, S407 is performed；Otherwise, hold
Row S408；
S407, the count value of anomalous counts device increase N, and wherein, N is natural number；Such as, N can take
1；S409 is performed after S407；
S408, the count value of described anomalous counts device reduce N；The count value of described anomalous counts device is not less than
Zero；S409 is performed after S408；
S409, judge that the count value of described anomalous counts device is whether more than count threshold；If so, S410 is performed；
Otherwise, S411 is performed；
S410, the mark that the second bypass circuit is abnormal is set, and determines that the second bypass circuit is abnormal；
S411, judge that the count value of described anomalous counts device is whether equal to zero；The most then perform S412,
Otherwise, S413 is performed；
S412, remove the mark that the second bypass circuit is abnormal, and determine that the second bypass circuit is normal；
S413, judge whether the abnormal mark of the second bypass circuit exists, the most then perform S414；No
Then, S415 is performed；
S414, determine that described second bypass circuit is abnormal；
S415, determine that described second bypass circuit is abnormal.
Wherein, the mark of the second bypass circuit exception can be a flag bit, and such as, flag bit is 1 table
Showing that the second bypass circuit is abnormal, flag bit is that 0 expression the second bypass circuit is normal, then, arrange second other
The mark of road circuit abnormality, is namely set to 1 by flag bit, removes the mark that the second bypass circuit is abnormal,
Namely flag bit is set to 0.
The phase-lock technique of a kind of parallel UPS system that the embodiment of the present invention provides, as it is shown in figure 5, include:
S501, when a UPS is output as the output of described rectification inverter circuit, determine described first
The first bypass circuit in UPS is abnormal；
S502, the second bypass circuit determined in a described UPS are normal；
S503, follow the tracks of described second bypass circuit；
S504, the frequency determining the voltage signal that a described UPS obtains from described and machine bus and phase
Position；
Wherein, in the voltage signal namely UPS that a UPS obtains from described and machine bus
Second bypass circuit is by the voltage signal device after filtering in also machine bus and controls the electricity after processor processes
Pressure signal, is a power frequency synchronizing signal, and a UPS can lock this power frequency synchronizing signal, thus produce
The output voltage fixed phase of a raw UPS；
S505, according to the frequency of voltage signal obtained and phase place, determine the letter of a described UPS output
Number.
The most in Figure 5, a power frequency synchronizing signal phase-locked for UPS derives from a UPS
The second bypass circuit.
Wherein, according to frequency and the phase place of the voltage signal obtained, the letter of a described UPS output is determined
Number, specifically include following steps:
Calculate the difference of the frequency of frequency and the reference frequency of the voltage signal of described acquisition, and described acquisition
The phase place of voltage signal and the difference of the phase place of fixed phase；
When a described UPS be in parallel UPS system from machine, or a described UPS is in parallel
When main frame in UPS and a described UPS frequency are locked, according to difference and the phase of calculated frequency
The difference of position determines the basic step-length that phase angle regulates, and the basic step-length and described first regulated by the phase angle determined
The current-sharing regulated quantity of UPS is added the step-length obtaining phase angle regulation；
When a described UPS is the main frame in parallel UPS and a described UPS frequency non-locking, will
The basic step-length of phase angle regulation when a described previous secondary frequencies of UPS is locked is with a described UPS's
Current-sharing regulated quantity is added the step-length obtaining phase angle regulation；
The step-length phase that the fixed phase of the initial time of prefixed time interval each time is regulated with described phase angle
Add the fixed phase of the finish time obtaining this prefixed time interval；And at the knot of this prefixed time interval
When the fixed phase in bundle moment is more than 360 degree, by the fixed phase of the finish time of this prefixed time interval
It is set to 0；Wherein, prefixed time interval is the difference in the moment regulating fixed phase adjacent twice；
When the fixed phase of the initial time of a prefixed time interval is less than 360 degree, between this Preset Time
Every the fixed phase of finish time be zero time, use interpolation method, obtain a described UPS mistake accurately
The phase angle in zero point moment；
The sine value of the described UPS phase angle in zero crossing moment accurately and cosine value, determine described
The output signal of one UPS.
The phase-lock technique of a kind of parallel UPS system that the embodiment of the present invention provides, as shown in Figure 6, also wraps
Include:
S601, when a UPS is output as the output of described rectification inverter circuit, determine described first
The first bypass circuit in UPS is normal；
S602, follow the tracks of described first bypass circuit；
S603, the frequency determining the voltage signal of described first bypass circuit and phase place；
S604, according to the frequency of the voltage signal of described first bypass circuit and phase place, determine described first
The signal of UPS output.
Therefore, in figure 6, a power frequency synchronizing signal phase-locked for UPS derives from a UPS
The signal of the first bypass circuit output.
Wherein, according to frequency and the phase place of the voltage signal of described first bypass circuit, described first is determined
The signal of UPS output, specifically includes following steps:
Calculate the frequency of the voltage signal of described first bypass circuit and the difference of the frequency of reference frequency, Yi Jisuo
State the phase place of the voltage signal of the first bypass circuit and the difference of the phase place of fixed phase；
When a described UPS be in parallel UPS system from machine, or a described UPS is in parallel
When main frame in UPS and a described UPS frequency are locked, according to difference and the phase of calculated frequency
The difference of position determines the basic step-length that phase angle regulates, and the basic step-length and described first regulated by the phase angle determined
The current-sharing regulated quantity of UPS is added the step-length obtaining phase angle regulation；
When a described UPS is the main frame in parallel UPS and a described UPS frequency non-locking, will
The basic step-length of phase angle regulation when a described previous secondary frequencies of UPS is locked is with a described UPS's
Current-sharing regulated quantity is added the step-length obtaining phase angle regulation；
The step-length phase that the fixed phase of the initial time of prefixed time interval each time is regulated with described phase angle
Add the fixed phase of the finish time obtaining this prefixed time interval；And at the knot of this prefixed time interval
When the fixed phase in bundle moment is more than 360 degree, by the fixed phase of the finish time of this prefixed time interval
It is set to 0；Wherein, prefixed time interval is the difference in the moment regulating fixed phase adjacent twice；
When the fixed phase of the initial time of a prefixed time interval is less than 360 degree, between this Preset Time
Every the fixed phase of finish time be zero time, use interpolation method, obtain a described UPS mistake accurately
The phase angle in zero point moment；
The sine value of the described UPS phase angle in zero crossing moment accurately and cosine value, determine described
The output signal of one UPS.
The phase-lock technique of a kind of parallel UPS system that the embodiment of the present invention provides, as it is shown in fig. 7, also wrap
Include:
S701, when a UPS is output as the output of described rectification inverter circuit, determine described first
The first bypass circuit in UPS is abnormal；
S702, the second bypass circuit determined in a described UPS are abnormal；
S703, determine that a described UPS is for from machine；
S704, follow the tracks of the output of described system；
S705, the frequency determining the voltage signal that described system exports and phase place；
S706, the frequency of the voltage signal exported according to described system and phase place, determine a described UPS
The signal of output.
In the figure 7, a power frequency synchronizing signal phase-locked for UPS derives from the letter of parallel UPS system output
Number.
Wherein, the frequency of the voltage signal exported according to described system and phase place, determine a described UPS
The signal of output, specifically includes following steps:
Calculate the frequency of the voltage signal of described system output and the difference of the frequency of reference frequency, and described system
The phase place of the voltage signal of system output and the difference of the phase place of fixed phase；
Difference and the difference of phase place according to calculated frequency determine the basic step-length that phase angle regulates, and will determine
Phase angle regulation basic step-length be added with the current-sharing regulated quantity of a described UPS obtain phase angle regulate step
Long；
The step-length phase that the fixed phase of the initial time of prefixed time interval each time is regulated with described phase angle
Add the fixed phase of the finish time obtaining this prefixed time interval；And at the knot of this prefixed time interval
When the fixed phase in bundle moment is more than 360 degree, by the fixed phase of the finish time of this prefixed time interval
It is set to 0；Wherein, prefixed time interval is the difference in the moment regulating fixed phase adjacent twice；
When the fixed phase of the initial time of a prefixed time interval is less than 360 degree, between this Preset Time
Every the fixed phase of finish time be zero time, use interpolation method, obtain a described UPS mistake accurately
The phase angle in zero point moment；
The sine value of the described UPS phase angle in zero crossing moment accurately and cosine value, determine described
The output signal of one UPS.
The phase-lock technique of a kind of parallel UPS system that the embodiment of the present invention provides, as shown in Figure 8, also wraps
Include:
S801, when a UPS is output as the output of described rectification inverter circuit, determine described first
The first bypass circuit in UPS is abnormal；
S802, the second bypass circuit determined in a described UPS are abnormal；
S803, determine that a described UPS is main frame；
S804, determine described oneth UPS output signal.
In fig. 8, a power frequency synchronizing signal phase-locked for UPS derives from the local oscillator of a UPS.
Wherein it is determined that the signal of a described UPS output, specifically include following steps:
The basic step-length and described first that phase angle time locked for a described previous secondary frequencies of UPS is regulated
The current-sharing regulated quantity of UPS is added the step-length obtaining phase angle regulation；
The step-length phase that the fixed phase of the initial time of prefixed time interval each time is regulated with described phase angle
Add the fixed phase of the finish time obtaining this prefixed time interval；And at the knot of this prefixed time interval
When the fixed phase in bundle moment is more than 360 degree, by the fixed phase of the finish time of this prefixed time interval
It is set to 0；Wherein, prefixed time interval is the difference in the moment regulating fixed phase adjacent twice；
When the fixed phase of the initial time of a prefixed time interval is less than 360 degree, between this Preset Time
Every the fixed phase of finish time be zero time, use interpolation method, obtain a described UPS mistake accurately
The phase angle in zero point moment；
The sine value of the described UPS phase angle in zero crossing moment accurately and cosine value, determine described
The output signal of one UPS.
Based on same inventive concept, the embodiment of the present invention additionally provides the phase-locked dress of a kind of parallel UPS system
Put, owing to the principle of the solved problem of this device is similar to the phase-lock technique of aforementioned parallel UPS system, because of
The enforcement of this this device may refer to the enforcement of preceding method, repeats no more in place of repetition.
The phase-locking device of a kind of parallel UPS system that the embodiment of the present invention provides, as it is shown in figure 9, include:
First determines module 91, is used for when a UPS is output as the output of described rectification inverter circuit,
Determine that the first bypass circuit in a described UPS is abnormal；And determine that second in a described UPS is other
Road circuit is normal；
Tracking module 92, is used for following the tracks of described second bypass circuit；
Second determines module 93, for determining the voltage that a described UPS obtains from described and machine bus
The frequency of signal and phase place；And according to the frequency of voltage signal obtained and phase place, determine a described UPS
The signal of output.
Further, first determines that module 91 is additionally operable to: be output as described commutation inversion at a UPS
During the output of circuit, determine that the first bypass circuit in a described UPS is normal；
Tracking module 92, is additionally operable to follow the tracks of described first bypass circuit；
Second determines module 93, is additionally operable to determine frequency and the phase of the voltage signal of described first bypass circuit
Position；And according to the frequency of the voltage signal of described first bypass circuit and phase place, determine a described UPS
The signal of output.
Further, first determines that module 91 is additionally operable to: be output as described commutation inversion at a UPS
During the output of circuit, determine that the first bypass circuit in a described UPS is abnormal；And determine described first
The second bypass circuit in UPS is abnormal；And determine that a described UPS is for from machine；
Tracking module 92, is additionally operable to follow the tracks of the output of described system；
Second determines module 93, is additionally operable to determine frequency and the phase place of the voltage signal that described system exports；And
The frequency of the voltage signal exported according to described system and phase place, determine the signal of a described UPS output.
Further, first determines that module 91 is additionally operable to: be output as described commutation inversion at a UPS
During the output of circuit, determine that the first bypass circuit in a described UPS is abnormal；And determine described first
The second bypass circuit in UPS is abnormal；And determine that a described UPS is main frame；
Second determines module 93, is additionally operable to determine the signal of a described UPS output.
Through the above description of the embodiments, those skilled in the art is it can be understood that arrive the present invention
Embodiment can be realized by hardware, it is also possible to the mode of the general hardware platform adding necessity by software is come real
Existing.Based on such understanding, the technical scheme of the embodiment of the present invention can embody with the form of software product
Come, this software product can be stored in a non-volatile memory medium (can be CD-ROM, USB flash disk,
Portable hard drive etc.) in, including some instructions with so that computer equipment (can be personal computer,
Server, or the network equipment etc.) perform the method described in each embodiment of the present invention.
It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, the mould in accompanying drawing
Block or flow process are not necessarily implemented necessary to the present invention.
It will be appreciated by those skilled in the art that the module in the device in embodiment can describe according to embodiment
Carry out being distributed in the device of embodiment, it is also possible to carry out respective change and be disposed other than one of the present embodiment
Or in multiple device.The module of above-described embodiment can merge into a module, it is also possible to is further split into
Multiple submodules.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. a parallel uninterrupted power supply ups system, it is characterised in that include multiple UPS, wherein,
Oneth UPS includes the first bypass circuit, the first switch, rectification inverter circuit and second switch；Described
When first switch Guan Bi, described second switch disconnect, a described UPS is output as described first bypass
The output of circuit, described first switching off, described second switch Guan Bi time, a described UPS's
It is output as the output of described rectification inverter circuit；A described UPS is any one in parallel UPS system
Individual UPS；
A described UPS also includes the second bypass circuit and controls processor；Described control processor,
When described first bypass circuit is normal, control relevant to the voltage signal of described first bypass circuit output
Signal is transferred to by described second bypass circuit and in machine bus；And be output as at a described UPS
When the output of described rectification inverter circuit and described first bypass circuit exception, control in described also machine bus
Voltage signal be transferred to a described UPS by described second bypass circuit；
The second bypass circuit in each UPS in parallel UPS system is connected to by described and machine bus
Together.
2. the system as claimed in claim 1, it is characterised in that described second bypass circuit includes first
Transformator, the second transformator, the 3rd switch, the 4th switch and wave filter；
One end of the primary side winding of described first transformator connects the input of described first bypass circuit, described
The other end of the primary side winding of the first transformator connects the outfan of described first bypass circuit, and described first becomes
One end of the vice-side winding of depressor is by described 3rd switch and the one of the primary side winding of described second transformator
End is connected, the primary side winding of the other end of the vice-side winding of described first transformator and described second transformator
The other end is connected, one end ground connection of the vice-side winding of described second transformator, the secondary of described second transformator
The other end of winding connects described control processor by described 4th switch and described wave filter；
Described in one end of the primary side winding of described second transformator connects and in machine bus one, described second
The other end of the primary side winding of transformator connects another in described also machine bus；
Described wave filter is used for, and is filtered the signal obtained from also machine bus by the second transformator,
Only output frequency is the signal of power frequency；
Described control processor is additionally operable to, and the signal output power frequency according to receiving from described wave filter synchronizes letter
Number.
3. system as claimed in claim 2, it is characterised in that described second bypass circuit also includes the
One resistance；
One end of the vice-side winding of described first transformator by described 3rd switch and described first resistance with
One end of the primary side winding of described second transformator is connected；Or, the vice-side winding of described first transformator
The other end is connected by the other end of described first resistance with the primary side winding of described second transformator.
4. the system as claimed in claim 1, it is characterised in that described control processor determine described
After oneth UPS is output as output and the described first bypass circuit exception of described rectification inverter circuit,
The voltage signal controlled in described also machine bus is transferred to a described UPS by described second bypass circuit
Before, determine that described second bypass circuit is normal.
5. the system as claimed in claim 1, it is characterised in that described control processor uses following step
Suddenly determine that described second bypass circuit is normal；
Determine that described second bypass circuit is transferred to the virtual value of the voltage signal of a described UPS；
Judge that whether the virtual value of described voltage signal is more than threshold voltage；The most then believe according to described voltage
Number virtual value calculate described voltage signal peak value；Otherwise, the count value of anomalous counts device increases N, its
In, N is natural number；
The cosine value of the phase angle of described voltage signal is obtained according to described voltage signal, and by the phase angle that obtains
Cosine value is multiplied with the peak value of described voltage signal and obtains reference value；
Calculate described reference value and described second bypass circuit and be transferred to the voltage signal of a described UPS
Voltage difference；
Judge that whether described voltage difference is more than error threshold；The count value of the most described anomalous counts device increases
N；Otherwise, the count value of described anomalous counts device reduces N；The count value of described anomalous counts device is not less than
Zero；
When the count value of described anomalous counts device is more than count threshold, it is abnormal that described second bypass circuit is set
Mark, and determine that the second bypass circuit is abnormal；
When the count value of described anomalous counts device is equal to zero, remove the mark that the second bypass circuit is abnormal, and
Determine that the second bypass circuit is normal；
When the count value of described anomalous counts device is less than described count threshold more than zero, it is judged that the second bypass electricity
Whether the mark of road exception exists, if, it is determined that the second bypass circuit is abnormal, otherwise, it determines second is other
Road circuit is normal.
6. a phase-lock technique for the parallel uninterrupted power supply ups system as described in Claims 1 to 5 is arbitrary,
It is characterized in that, including:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
The first bypass circuit abnormal；
Determine that the second bypass circuit in a described UPS is normal；
Follow the tracks of described second bypass circuit；
Determine frequency and the phase place of the voltage signal that a described UPS obtains from described and machine bus；
Frequency according to the voltage signal obtained and phase place, determine the signal of a described UPS output.
7. method as claimed in claim 6, it is characterised in that described method also includes:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
The first bypass circuit normal；
Follow the tracks of described first bypass circuit；
Determine frequency and the phase place of the voltage signal of described first bypass circuit；
The frequency of the voltage signal according to described first bypass circuit and phase place, determine that a described UPS is defeated
The signal gone out.
8. method as claimed in claim 6, it is characterised in that described method also includes:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
The first bypass circuit abnormal；
Determine that the second bypass circuit in a described UPS is abnormal；
Determine that a described UPS is for from machine；
Follow the tracks of the output of described system；
Determine frequency and the phase place of the voltage signal that described system exports；
The frequency of the voltage signal exported according to described system and phase place, determine a described UPS output
Signal.
9. method as claimed in claim 6, it is characterised in that described method also includes:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
The first bypass circuit abnormal；
Determine that the second bypass circuit in a described UPS is abnormal；
Determine that a described UPS is main frame；
Determine the signal of a described UPS output.
10. the phase-locked dress of the parallel uninterrupted power supply ups system as described in Claims 1 to 5 is arbitrary
Put, it is characterised in that including:
First determines module, is used for when a UPS is output as the output of described rectification inverter circuit,
Determine that the first bypass circuit in a described UPS is abnormal；And determine that second in a described UPS is other
Road circuit is normal；
Tracking module, is used for following the tracks of described second bypass circuit；
Second determines module, for determining the voltage letter that a described UPS obtains from described and machine bus
Number frequency and phase place；And according to the frequency of voltage signal obtained and phase place, determine a described UPS
The signal of output.
11. devices as claimed in claim 10, it is characterised in that described first determines that module is additionally operable to:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
One bypass circuit is normal；
Described tracking module, is additionally operable to follow the tracks of described first bypass circuit；
Described second determines module, is additionally operable to determine frequency and the phase of the voltage signal of described first bypass circuit
Position；And according to the frequency of the voltage signal of described first bypass circuit and phase place, determine a described UPS
The signal of output.
12. devices as claimed in claim 10, it is characterised in that described first determines that module is additionally operable to:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
One bypass circuit abnormality；And determine that the second bypass circuit in a described UPS is abnormal；And determine institute
State a UPS for from machine；
Described tracking module, is additionally operable to follow the tracks of the output of described system；
Described second determines module, is additionally operable to determine frequency and the phase place of the voltage signal that described system exports；
And the frequency of the voltage signal exported according to described system and phase place, determine the letter of a described UPS output
Number.
13. devices as claimed in claim 10, it is characterised in that described first determines that module is additionally operable to:
When a UPS is output as the output of described rectification inverter circuit, determine in a described UPS
One bypass circuit abnormality；And determine that the second bypass circuit in a described UPS is abnormal；And determine institute
Stating a UPS is main frame；
Described second determines module, is additionally operable to determine the signal of a described UPS output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510065250.8A CN105990898B (en) | 2015-02-06 | 2015-02-06 | A kind of parallel uninterrupted power source system, phase-lock technique and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510065250.8A CN105990898B (en) | 2015-02-06 | 2015-02-06 | A kind of parallel uninterrupted power source system, phase-lock technique and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990898A true CN105990898A (en) | 2016-10-05 |
| CN105990898B CN105990898B (en) | 2018-12-25 |
Family
ID=57038055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510065250.8A Active CN105990898B (en) | 2015-02-06 | 2015-02-06 | A kind of parallel uninterrupted power source system, phase-lock technique and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990898B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111030285A (en) * | 2019-12-20 | 2020-04-17 | 科华恒盛股份有限公司 | Uninterrupted power supply phase-locking implementation method and terminal equipment |
| CN112039064A (en) * | 2020-08-31 | 2020-12-04 | 科华恒盛股份有限公司 | Control method based on power supply system and related device |
| CN112072706A (en) * | 2020-09-08 | 2020-12-11 | 湖南理工学院 | Inverter parallel operation synchronous phase locking method |
| CN112217277A (en) * | 2020-10-15 | 2021-01-12 | 石家庄通合电子科技股份有限公司 | UPS main bypass switching system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2812380Y (en) * | 2004-12-17 | 2006-08-30 | 左东 | UPS system with cooperative-type redundant parallel function |
| CN201032693Y (en) * | 2007-03-05 | 2008-03-05 | 深圳市新未来电源技术有限公司 | Modularization parallel power dedicated UPS power supply device |
| US20080265680A1 (en) * | 2007-04-27 | 2008-10-30 | Liebert Corporation | Method for pulse width modulation synchronization in a parallel ups system |
| CN201393076Y (en) * | 2009-03-20 | 2010-01-27 | 深圳市捷益达电子有限公司 | Uninterrupted power supply two-machine redundancy parallel connection system |
| CN102480140A (en) * | 2010-11-25 | 2012-05-30 | 中兴通讯股份有限公司 | Method and circuit for synchronizing modularized uninterrupted power supply system |
| CN102780263A (en) * | 2012-08-05 | 2012-11-14 | 武汉中正方圆科技有限公司 | Industrial uninterruptible power supply |
-
2015
- 2015-02-06 CN CN201510065250.8A patent/CN105990898B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2812380Y (en) * | 2004-12-17 | 2006-08-30 | 左东 | UPS system with cooperative-type redundant parallel function |
| CN201032693Y (en) * | 2007-03-05 | 2008-03-05 | 深圳市新未来电源技术有限公司 | Modularization parallel power dedicated UPS power supply device |
| US20080265680A1 (en) * | 2007-04-27 | 2008-10-30 | Liebert Corporation | Method for pulse width modulation synchronization in a parallel ups system |
| CN201393076Y (en) * | 2009-03-20 | 2010-01-27 | 深圳市捷益达电子有限公司 | Uninterrupted power supply two-machine redundancy parallel connection system |
| CN102480140A (en) * | 2010-11-25 | 2012-05-30 | 中兴通讯股份有限公司 | Method and circuit for synchronizing modularized uninterrupted power supply system |
| CN102780263A (en) * | 2012-08-05 | 2012-11-14 | 武汉中正方圆科技有限公司 | Industrial uninterruptible power supply |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111030285A (en) * | 2019-12-20 | 2020-04-17 | 科华恒盛股份有限公司 | Uninterrupted power supply phase-locking implementation method and terminal equipment |
| CN112039064A (en) * | 2020-08-31 | 2020-12-04 | 科华恒盛股份有限公司 | Control method based on power supply system and related device |
| CN112039064B (en) * | 2020-08-31 | 2022-05-10 | 科华恒盛股份有限公司 | Control method based on power supply system and related device |
| CN112072706A (en) * | 2020-09-08 | 2020-12-11 | 湖南理工学院 | Inverter parallel operation synchronous phase locking method |
| CN112217277A (en) * | 2020-10-15 | 2021-01-12 | 石家庄通合电子科技股份有限公司 | UPS main bypass switching system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990898B (en) | 2018-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| AU751441B2 (en) | Slave clock generation system and method for synchronous telecommunications networks | |
| US6239626B1 (en) | Glitch-free clock selector | |
| CN105990898A (en) | Parallel UPS (Uninterruptible Power Supply) system and phase lock method and device | |
| JPH04113718A (en) | Hitless clock switching device | |
| US20090033380A1 (en) | Redundant clock switch circuit | |
| EP0942536A1 (en) | A phase-locked loop circuit with dynamic backup | |
| CN113014350A (en) | PMC interface-based time synchronization method between simulation devices | |
| KR100882391B1 (en) | Seamless clock | |
| CN112072706A (en) | Inverter parallel operation synchronous phase locking method | |
| CN105226811B (en) | System and method are realized in a kind of genlock of uninterruptible power supply | |
| CN115528739A (en) | Single-phase inverter parallel operation synchronization method and system, single-phase inverter and storage medium | |
| CN110119331B (en) | Clock switching method and device, server and clock system | |
| CN110098885B (en) | Clock synchronization circuit, device and method | |
| JP2008176578A (en) | Redundant operation system and operation part | |
| CN101436856A (en) | Frequency synchronization device, frequency synchronization method and frequency generating apparatus using the method | |
| JP2009014363A (en) | Semiconductor testing device | |
| CN107710622B (en) | Clock generation circuit and method for generating clock signal | |
| JP3536780B2 (en) | Sync source signal switching circuit | |
| WO2012127487A1 (en) | An apparatus for glitch-free clock switching and a method thereof | |
| Arbugeri et al. | A digital communication system for a control strategy employed in the parallelism of three-phase voltage source inverter | |
| JP2013115529A (en) | Clock frequency dividing apparatus | |
| JP2011050030A (en) | System employing synchronized crystal oscillator-based clock | |
| JP3894785B2 (en) | Automatic phase controller | |
| CN116207839A (en) | High-frequency synchronization method, device and equipment | |
| JPH11298460A (en) | Clock changeover circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Nanshan District Xueyuan Road in Shenzhen city of Guangdong province 518055 No. 1001 Nanshan Chi Park building B2 Applicant after: Vitamin Technology Co., Ltd. Address before: Nanshan District Xueyuan Road in Shenzhen city of Guangdong province 518055 No. 1001 Nanshan Chi Park building B2 Applicant before: Aimosheng Network Energy Source Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |