CN105990437A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN105990437A
CN105990437A CN201510553386.3A CN201510553386A CN105990437A CN 105990437 A CN105990437 A CN 105990437A CN 201510553386 A CN201510553386 A CN 201510553386A CN 105990437 A CN105990437 A CN 105990437A
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China
Prior art keywords
electrode
semiconductor regions
semiconductor
region
regions
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CN201510553386.3A
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Chinese (zh)
Inventor
泉泽优
石桥弘
大田浩史
佐伯秀
佐伯秀一
奥畠隆嗣
小野升太郎
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Toshiba Corp
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Toshiba Corp
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Publication of CN105990437A publication Critical patent/CN105990437A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

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Abstract

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a first insulating layer, and a second electrode. The first semiconductor region includes a first region and a second region. The second region is provided around the first region. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the first semiconductor region. The first electrode is provided on the third semiconductor region. The first electrode is electrically connected to the third semiconductor region. The first insulating layer is provided on the first electrode. The second electrode is provided on the second semiconductor region. The second electrode is electrically connected to the second semiconductor region. A portion of the second electrode is positioned on the first insulating layer.

Description

Semiconductor device
[related application]
Subject application enjoys Shen based on Japanese patent application 2015-52245 (applying date: on March 16th, 2015) Please the priority of case.The full content that subject application comprises basis application case by referring to this basis application case.
Technical field
Embodiments of the present invention relate to a kind of semiconductor device.
Background technology
Diode used in the purposes such as Electric control or MOSFET (Metal Oxide Semiconductor Field Effect Transistor, mos field effect transistor), IGBT (Insulated Gate Bipolar Transistor, igbt) etc. in semiconductor device, in order to improve withstanding voltage and in week of element area Enclose and terminal area is set.There is following situation: at the cathode side of terminal area, in order to suppress the sky from element area extension Weary layer reaches the outer rim of semiconductor device, and arranges the semiconductor region with the current potential roughly equal with the current potential of anode electrode Territory and the electrode being connected to this semiconductor regions.In the case, owing to being connected to electrode and the negative electrode of semiconductor regions Distance between electrode is shorter, and therefore the electric-field intensity between these electrodes uprises.
On the other hand, when the use of semiconductor device or in reliability testing, because applying the heat to semiconductor device and electricity Pressure, and cause the ion included in the material outside the semiconductor devices such as sealing resin move to be arranged at these electrodes it Between insulation division.Now, if interelectrode electric-field intensity is higher, then the ion moving to insulation division is in insulation division Portion polarizes.Thus there is following situation: because ion causes the electric field in semiconductor regions to divide in the internal polarization of insulation division Cloth is affected, thus the deterioration of the withstanding voltage of semiconductor device.
Therefore, in the semiconductor device of electrode that there is semiconductor regions in terminal area and be connected to this semiconductor regions In, need to suppress the technology of the variation of withstanding voltage.
Content of the invention
Embodiments of the present invention provide the semiconductor device of the variation of a kind of withstanding voltage that can suppress in terminal area.
The semiconductor device of embodiment has the 1st semiconductor regions of the 1st conductivity type, the 2nd half of the 2nd conductivity type the leads Body region, the 3rd semiconductor regions of the 1st conductivity type, the 1st electrode, the 1st insulating barrier and the 2nd electrode.
1st semiconductor regions has the 1st region and the 2nd region.2nd region is arranged at around the 1st region.
2nd semiconductor regions is arranged on the 1st semiconductor regions.
3rd semiconductor regions is arranged on the 1st semiconductor regions.
1st electrode is arranged on the 3rd semiconductor regions.1st electrode and the 3rd semiconductor regions are electrically connected with.
1st insulating barrier is arranged on the 1st electrode.
2nd electrode is arranged on the 2nd semiconductor regions.2nd electrode and the 2nd semiconductor regions are electrically connected with.2nd electricity A part for pole is positioned on the 1st insulating barrier.
Brief description
Fig. 1 is the top view of the semiconductor device representing the 1st embodiment.
Fig. 2 is the A-A' sectional view of Fig. 1.
Fig. 3 is the B-B' sectional view of Fig. 1.
Fig. 4 is the C-C' sectional view of Fig. 1.
Fig. 5 is the D-D' sectional view of Fig. 1.
Fig. 6 is the top view of the semiconductor device representing the 2nd embodiment.
Fig. 7 is the A-A' sectional view of Fig. 6.
Fig. 8 is the top view of the semiconductor device representing the 3rd embodiment.
Fig. 9 is the A-A' sectional view of Fig. 8.
Figure 10 is a part of sectional view of the semiconductor device representing the 4th embodiment.
Figure 11 is the top view of the semiconductor device representing the 5th embodiment.
Figure 12 is the A-A' sectional view of Figure 11.
Detailed description of the invention
Hereinafter, various embodiments of the present invention will be described on one side referring to the drawings.
Accompanying drawing is schematic diagram or concept map, and ratio of size between the thickness of each several part and the relation of width, part etc. is not Must be identical with actual conditions.Even represent the situation of same section, there is also mutual size or ratio with reference to the accompanying drawings and Situation about differently representing.
In specification and each figure of subject application, to it is stated that the identical symbol of the identical key element mark of key element, and Suitably omit detailed description.
In the explanation of each embodiment, use the orthogonal coordinate system of XYZ.Side by the main surface parallel with semiconductor layer S To and 2 mutually orthogonal directions be set to X-direction (the 3rd direction) and Y-direction (the 2nd direction), will be with these X sides To and both orthogonal direction of Y-direction be set to Z-direction (the 1st direction).
In the following description, n+、n、n-And p+、p、p-Record be impurity concentration relative representing each conductivity type The height of property.That is, n+Represent that the impurity concentration of N-shaped is relatively higher than n, n-Represent the impurity concentration of N-shaped relatively lower than n. p+Represent that the impurity concentration of p-type is relatively higher than p, p-Represent the impurity concentration of p-type relatively lower than p.
Also the p-type that for each embodiment described below, can make each semiconductor regions inverts with N-shaped and implements each reality Execute mode.
(the 1st embodiment)
The semiconductor device 100 to the 1st embodiment for Fig. 1～Fig. 5 is used to illustrate.
Fig. 1 is the top view of the semiconductor device 100 representing the 1st embodiment.
Fig. 2 is the A-A' sectional view of Fig. 1.
Fig. 3 is the B-B' sectional view of Fig. 1.
Fig. 4 is the C-C' sectional view of Fig. 1.
Fig. 5 is the D-D' sectional view of Fig. 1.
In FIG, the part of multiple gate electrode 11 is represented by dashed line.
The semiconductor device 100 for example, MOSFET of the 1st embodiment.
The semiconductor device 100 of the 1st embodiment has n+Type drain region the 1st, n-Type semiconductor regions 2 (the 1st conduction 1st semiconductor regions of type), p-type base region 3 (the 2nd semiconductor regions of the 2nd conductivity type), n+Type source region 4 (the 5th semiconductor regions of the 1st conductivity type), n+Type semiconductor regions 5 (the 3rd semiconductor regions of the 1st conductivity type), Gate insulator the 10th, gate electrode the 11st, field plate electrode the 13rd, insulating barrier the 23rd, insulating barrier 25 (the 1st insulating barrier), drain electrode Electrode the 30th, source electrode 31 (the 2nd electrode), electrode 33 (the 1st electrode), electrode 35 and electrode 37.
Semiconductor layer S has front S1 and back side S2.Source electrode 31 is arranged at the front S1 side of semiconductor layer S, Drain electrode 30 is arranged at the back side S2 side of semiconductor layer S.
The region of the inner side of two shown in Fig. 1 chain line comprises p-type base region 3 and n for being formed with+Type source region is the 4th, The element area R1 (the 1st region) of the MOSFET of gate electrode 11 grade.On the other hand, two shown in Fig. 1 chain line The region in outside be not comprise the terminal area R2 (the 2nd region) of MOSFET.As it is shown in figure 1, terminal area R2 It is arranged at around element area R1.
As in figure 2 it is shown, n+Type drain region 1 is arranged at the back side S2 side of semiconductor layer S.n+Type drain region 1 is arranged In both element area R1 and terminal area R2.n+Type drain region 1 is electrically connected with drain electrode 30.
n-Type semiconductor regions 2 is arranged at n at element area R1 and terminal area R2+On type drain region 1.
P-type base region 3 is selectively arranged at n in element area R1-On type semiconductor regions 2.P-type base region Territory 3 is provided with multiple for example in the X direction, and each p-type base region 3 extends along Y-direction.
n+Type source region 4 is partially selectively arranged on p-type base region 3 at the front S1 of semiconductor layer S. n+Type source region 4 is provided with multiple in the X direction, each n+Type source region 4 extends along Y-direction.
In element area R1, front S1 is provided with gate electrode 11.Gate electrode 11 is arranged in the X direction Have multiple.Each gate electrode 11 is across gate insulator 10 and n-A part for type semiconductor regions 2, p-type base Polar region territory 3 and n+A part for type source region 4 to.
Front S1 is provided with source electrode 31.P-type base region 3 and n+Type source region 4 and source electrode 31 It is electrically connected with.It is provided with insulating barrier, gate electrode 11 and source electrode between gate electrode 11 and source electrode 31 31 is electrically isolated.
In the state of drain electrode 30 being applied with relative to source electrode 31 as positive voltage, to gate electrode 11 Applying the voltage of more than threshold value, thus MOSFET becomes conducting state.Now, the grid at p-type base region 3 Region near insulating barrier 10 forms passage (inversion layer).
The front S1 of terminal area R2 is provided with field plate electrode 13.Field plate electrode 13 is surrounded by insulating barrier 23, And it is electrically isolated with gate electrode the 11st, drain electrode 30 and source electrode 31.
Field plate electrode 13 is applied for example relative to n-Type semiconductor regions 2 is negative voltage.By to field plate electrode 13 Apply voltage, and make the n around multiple p-type base region 3-Type semiconductor regions 2 vague and generalization.
In the R2 of terminal area, at n-It is provided with n in the way of the R1 of embracing element region on type semiconductor regions 2+Type Semiconductor regions 5.
Electrode 33 is arranged at n in the way of the R1 of embracing element region+On type semiconductor regions 5, and and n+Type semiconductor Region 5 is electrically connected with.
For example, as in figure 2 it is shown, electrode 33 comprises part 1 33a and part 2 33b.Part 1 33a is arranged On insulating barrier 23, part 2 33b is arranged at n+On type semiconductor regions 5.Therefore, the Z of part 1 33a Length L1 in direction is shorter than length L2 of the Z-direction of part 2 33b.
Electrode 35 is to arrange in the way of the R1 of embracing element region.Specifically, electrode 35 surround gate electrode 11 with A part for source electrode 31, and surrounded by electrode 33.In z-direction, a part for electrode 35 is arranged at n+Type Between semiconductor regions 5 and part 1 33a, another part of electrode 35 is arranged at n-Type semiconductor regions 2 and the 1st Between part 33a.
Herein, the distance in the X-direction between the end of the element area R1 side of electrode 35 and gate electrode 11 is set For D1, by n+The distance in X-direction between type semiconductor regions 5 and gate electrode 11 is set to D2, and by electrode The distance in X-direction between the end of the element area R1 side of 33 and gate electrode 11 is set to D3.
A part for part 1 33a is relative to electrode the 35th, part 2 33b and n+Type semiconductor regions 5 and arrange In element area R1 side.A part for electrode 35 is relative to n+Type semiconductor regions 5 and be arranged at element area R1 side.
Therefore, it as in figure 2 it is shown, distance D1 is longer than distance D3, and is shorter than distance D2.
n+Type semiconductor regions 5 has and n+The roughly the same current potential of the current potential of type drain region 1.Therefore, it is connected to n+ The electrode 33 of type semiconductor regions 5 and electrode 35 also have and n+The roughly the same current potential of the current potential of type drain region 1. Electrode 35 also can be left electrically floating.Even if in the case, due to electrode 35 and n+Type semiconductor regions 5 proximity is arranged, Therefore the current potential of electrode 35 and n+The current potential of type drain region 1 is roughly the same.
Source electrode 31 for example has the 1st source electrode layer the 311st, the 2nd source electrode layer 312 and connecting portion 313. 2nd source electrode layer 312 is electrically connected with the 1st source electrode layer 311 via connecting portion 313.
1st source electrode layer 311 is arranged on the S1 of front.In X-direction and Y-direction, at the 1st source electrode layer It is provided with insulating barrier 23 between the part of 311 and part 2 33b.At the 1st source electrode layer the 311st, insulating barrier the 23rd, And it on electrode 33, is provided with insulating barrier 25, the 2nd source electrode layer 312 is arranged on insulating barrier 25.
Connecting portion 313 can be for being arranged between the 1st source electrode layer the 311 and the 2nd source electrode layer 312 and along X-Y plane The conductive layer of extension.The position arranging connecting portion 313 can be at the 1st source electrode layer the 311 and the 2nd source electrode layer 312 Between suitably change.
2nd source electrode layer 312 has part 1 31a being arranged at terminal area R2.Part 1 31a is positioned at electricity On pole 33.Specifically, a part for part 1 31a is in z-direction across insulating barrier 25 and part 2 33b At least a portion and part 1 33a overlapping.Part 1 31a is set to ring-type along X-Y plane.
It as in figure 2 it is shown, distance D4 the shortest between the 2nd source electrode layer 312 and electrode 33, for example, is shorter than the 1st Distance D5 the shortest between source electrode layer 311 and electrode 33.
As it is shown on figure 3, gate electrode 11 is connected to electrode 37 via connecting portion 12.Electrode 37 for example has the 1st Electrode layer the 371st, the 2nd electrode layer 372 and connecting portion 373.2nd electrode layer 372 via connecting portion 373 with the 1st Electrode layer 371 is electrically connected with.Multiple gate electrodes 11 are supplied common by electrode 37 function as gate pad Grid potential.
Connecting portion 373 can be to be arranged between the 1st electrode layer the 371 and the 2nd electrode layer 372 and leading along X-Y plane extension Electric layer.The position arranging connecting portion 373 suitably can be changed between the 1st electrode layer the 371 and the 2nd electrode layer 372.
Be provided with insulating barrier between electrode 37 and p-type semiconductor region 3, electrode 37 be arranged in semiconductor layer S Each semiconductor regions electrically isolated.
It in X-direction and Y-direction, between the 1st electrode layer the 371 and the 1st source electrode layer 311, is provided with insulating barrier 25.2nd electrode layer 372 is in X-direction and Y-direction, arranged side by side across gap with the 1st source electrode layer 311.Or, Also not shown insulating barrier can be set between the 2nd electrode layer the 372 and the 1st source electrode layer 311.
The principal component of semiconductor layer S for example, silicon.The principal component of semiconductor layer S is alternatively carborundum, gallium nitride or arsenic Change gallium etc..
For gate electrode the 11st, field plate electrode 13 and electrode 35, for example, use polysilicon.
For drain electrode the 30th, source electrode 31 and electrode 33, for example, use the metals such as aluminium, nickel, copper or titanium.
For gate insulator the 10th, insulating barrier 23 and insulating barrier 25, for example, use silica.Also can be for insulating barrier 23 and insulating barrier 25, use the oxide of other semi-conducting materials or the oxide of metal material.
It follows that the functions and effects of present embodiment are illustrated.
In the present embodiment, the electrode 33 be arranged at terminal area R2 is provided with insulating barrier 25, insulate at this It is provided with a part for source electrode 31 on layer 25.By using this composition, and can suppress in terminal area resistance to Changed by voltage.
As comparative example, not there is to source electrode 31 the 2nd source electrode layer 312 and the situation of connecting portion 313 is carried out Explanation.In the case, between source electrode 31 and electrode 33, X-direction and Y-direction produce electric field. And then, owing to a part for electrode 33 is compared with n+Type semiconductor regions 5 and electrode 35 are arranged at and more lean on element area R1 side, Therefore the distance between electrode 33 and source electrode 31 shortens, thus the electric-field strength between electrode 33 and source electrode 31 Degree uprises.
If the electric-field intensity between electrode 33 and source electrode 31 uprises, then move to being configured between these electrodes The ion of insulation division polarizes along direction of an electric field.Now, the direction of ionic polarization for in semiconductor devices from element area R1 produces the identical direction in the direction of gradient of current potential towards terminal area R2.Therefore, this polarization is in semiconductor layer S The distribution (extension of equipotential line) of current potential impact, thus the withstanding voltage of semiconductor device is possible to variation.
According to present embodiment, owing to being provided with a part for source electrode 31 on insulating barrier 25, therefore, it is possible to make Incline towards Z-direction relative to X-direction and Y-direction in the direction of the electric field producing between electrode 33 and source electrode 31 Tiltedly.I.e., it is possible to increase direction of an electric field is relative to the slope of X-direction and Y-direction.Therefore, it is i.e. easy in electrode 33 and source In the case that insulation division between pole electrode 31 produces the polarization of ion, it is possible to reduce the resistance to of because of polarization semiconductor device By voltage influence.
Now, by least a portion of this part Yu electrode 33 of making source electrode 31 in z-direction across insulation Layer 25 and overlapping, and the direction of the electric field of generation can be made between electrode 33 and source electrode 31 more towards Z-direction. That is, the slope relative to X-direction and Y-direction for the direction of an electric field can and then be increased.Its result, can and then reduce at electrode The impact that the withstanding voltage of semiconductor device is caused by the polarization of the ion that the insulation division between 33 and source electrode 31 produces.
It is shorter than the 1st source electrode layer by making distance D7 the shortest between the 2nd source electrode layer 312 and electrode 33 Distance D8 the shortest between 311 and electrode 33, and the electricity producing between electrode 33 and source electrode 31 can be made The direction of field is more suitably towards Z-direction.
(the 2nd embodiment)
The semiconductor device 200 to the 2nd embodiment for Fig. 6 and Fig. 7 is used to illustrate.
Fig. 6 is the top view of the semiconductor device 200 representing the 2nd embodiment.
Fig. 7 is the A-A' sectional view of Fig. 6.
In figure 6, a part and the p-type semiconductor region 6 of gate electrode 11 are represented by dashed line.
Semiconductor device 200 with the comparison of semiconductor device 100, for example, possesses p not possessing field plate electrode 13 The aspect of type semiconductor regions 6 is different.
As shown in Figure 6, p-type semiconductor region 6 is set to ring-type in the R2 of terminal area.P-type semiconductor region 6 case As multiple in being provided with, a p-type semiconductor region 6 is surrounded by another p-type semiconductor region 6.
As shown in FIG. 6 and 7, multiple p-type base regions 3 and multiple n+Type source region 4 is by p-type semiconductor region 6 surround.P-type semiconductor region 6 is by n+Type semiconductor regions 5 surrounds.P-type semiconductor region 6 shown in Fig. 6 Quantity is a case, and the quantity of p-type semiconductor region 6 can be many compared with this quantity, it is possible to few compared with this quantity.
By arranging p-type semiconductor region 6, and make vague and general layer from n-Type semiconductor regions 2 and p-type semiconductor region 6 Knot extension.Therefore, it is possible to suppress multiple p-type base region 3 is positioned in X-direction or Y-direction the p of end Electric field in type base region 3 is concentrated.
On the other hand, it is provided by p-type semiconductor region 6, and in the front S1 side of terminal area R2, partly Manifest the higher part of electric-field intensity.If passed through along the ion that the electric field between electrode 33 and source electrode 31 moves The electric field that p-type semiconductor region 6 produces attracts, then the distribution of the current potential in the R2 of terminal area is unstable, thus partly leads The withstanding voltage of body device easily changes.
According to present embodiment, the direction of the electric field producing between electrode 33 and source electrode 31 can be made relative to X Direction and Y-direction and tilt towards Z-direction.Therefore, present embodiment possesses p-type semiconductor region at semiconductor device It is particularly effective in the case of 6.By present embodiment is applied to the semiconductor device possessing p-type semiconductor region 6, The variation of withstanding voltage while improving withstanding voltage, can be suppressed.
(the 3rd embodiment)
The semiconductor device 300 to the 3rd embodiment for Fig. 8 and Fig. 9 is used to illustrate.
Fig. 8 is the top view of the semiconductor device 300 representing the 3rd embodiment.
Fig. 9 is the A-A' sectional view of Fig. 8.
In fig. 8, it in order to the construction of semiconductor device 200 is described, and is represented by dashed line and is provided with p-Type semiconductor regions A part for the position of 7.
Semiconductor device 300, with the comparison of semiconductor device 100, for example, has not possessing field plate electrode 13 Standby p-The aspect of type semiconductor regions 7 is different.
For example, as shown in Figure 8, p-Type semiconductor regions 7 is provided with multiple in the X direction.Each p-Type semiconductor region Territory 7 for example extends in the Y direction along gate electrode 11.p-A part for type semiconductor regions 7 is arranged at terminal area R2。
p-Type semiconductor regions 7 is not limited to the example shown in Fig. 8, is for example alternatively provided with multiple in the Y direction, Each p-Type semiconductor regions 7 extends in X direction.Or, p-Type semiconductor regions 7 also can be in X-direction and Y-direction It is provided with multiple.Or, p-Type semiconductor regions 7 also can be provided with multiple annularly.
As it is shown in figure 9, p-Type semiconductor regions 7 is provided with multiple in semiconductor layer S.Multiple p-Type semiconductor regions The part of 7 is arranged at element area R1, and another part of multiple p-type semiconductor region is arranged at terminal area R2.
In element area R1, at p-It is provided with p-type base region 3 on type semiconductor regions 7.At terminal area R2 In, insulating barrier 23 and 25 is positioned at p-On type semiconductor regions 7.
p-The impurity concentration of type semiconductor regions 7 is for example with p-The total amount of the n-type impurity included in type semiconductor regions 7 Be positioned at p-N between type semiconductor regions 7-The total amount of the p-type impurity included in type semiconductor regions 2a is equal Mode sets.n-Type semiconductor regions 2a and p-Type semiconductor regions 7 constitutes super junction construction.
It is off-state at MOSFET, and relative to the current potential of source electrode 31, positive electricity is applied to drain electrode 30 During position, vague and general layer is from n-Type semiconductor regions 2a and p-The pn-junction extension of type semiconductor regions 7.Due to n-Type semiconductor Region 2a and p-Type semiconductor regions 7 is relative to n-Type semiconductor regions 2a and p-The knot of type semiconductor regions 7 is vertical Direction on vague and generalization, thus suppression relative to n-Type semiconductor regions 2a and p-Balancing of type semiconductor regions 7 is capable The electric field in direction is concentrated, and therefore obtains higher withstanding voltage.
But, it is being provided with p-In the case of type semiconductor regions 7, the electric-field intensity of the front S1 side of terminal area R2 It is relatively not provided with p-The situation of type semiconductor regions 7 is high.Accordingly, because electric field between electrode 33 and source electrode 31 and The distribution causing current potential in the R2 of terminal area is unstable, and the withstanding voltage of semiconductor device easily changes.
According to present embodiment, the direction of the electric field producing between electrode 33 and source electrode 31 can be made relative to X Direction and Y-direction and tilt to Z-direction.Therefore, present embodiment possesses p at semiconductor device-Type semiconductor regions 7 In the case of be particularly effective.By present embodiment is applied to possess p-The semiconductor device of type semiconductor regions 7, and Withstanding voltage can be improved while suppressing the variation of withstanding voltage.
Above, as a example by the plane MOSFET being formed with gate electrode 11 on semiconductor layer S, to the present invention's 1st embodiment is illustrated to the 3rd embodiment.But, these embodiments are not limited to plane MOSFET, it is possible to be applied to the trench MOSFET that gate electrode 11 is arranged in semiconductor layer S.
(the 4th embodiment)
The semiconductor device 400 to the 4th embodiment for the Figure 10 is used to illustrate.
Figure 10 is a part of sectional view of the semiconductor device 400 representing the 4th embodiment.
The semiconductor device 400 for example, IGBT of the 4th embodiment.
The semiconductor device 400 of the 4th embodiment has p+Type collector region the 8th, n-type semiconductor region 1a, n-Type half Conductive region 2 (the 1st semiconductor regions of the 1st conductivity type), p-type base region 3 (the 2nd semiconductor region of the 2nd conductivity type Territory), n+Type emitting area 4 (the 5th semiconductor regions), n+Type semiconductor regions 5 (the 3rd semiconductor regions), gate insulator Layer the 10th, gate electrode the 11st, insulating barrier the 23rd, insulating barrier 25 (the 1st insulating barrier), collector electrode the 30th, emitter electrode 31 (the 2 electrodes), electrode 33 (the 1st electrode), electrode 35 and electrode 37 (the 3rd electrode).
Semiconductor device 400, with the comparison of semiconductor device 100, is being also equipped with p+Type collector region 8, and conduct The aspect of IGBT function is different.In semiconductor device 400, electrode 31 is emitter electrode, and electrode 30 is Collector electrode.
At p+Type collector region 8 and n-Between type semiconductor regions 2, for example, replace the n in semiconductor device 100+Type half Conductive region 1, and it is provided with n-type semiconductor region 1a.N-type semiconductor region 1a can be as buffer area function.
According to present embodiment, can suppress by generation between electrode 33 and emitter electrode 31 in IGBT The variation of the withstanding voltage caused by electric field.
(the 5th embodiment)
The semiconductor device 500 to the 5th embodiment for Figure 11 and Figure 12 is used to illustrate.
Figure 11 is the top view of the semiconductor device 500 representing the 5th embodiment.
Figure 12 is the A-A' sectional view of Figure 11.
The semiconductor device 500 for example, diode of the 5th embodiment.
The semiconductor device 500 of the 5th embodiment has n+Type semiconductor regions the 1st, n-(the 1st leads type semiconductor regions 2 Electricity type the 1st semiconductor regions), p-type semiconductor region 3 (the 2nd semiconductor regions of the 2nd conductivity type), p+Type is partly led Body region the 9th, n+Type semiconductor regions 5 (the 3rd semiconductor regions), insulating barrier the 23rd, insulating barrier 25 (the 1st insulating barrier), sun Pole electrode the 30th, cathode electrode 31 (the 2nd electrode), electrode 33 (the 1st electrode) and electrode 35.
In semiconductor device 500, electrode 31 is cathode electrode, and electrode 30 is anode electrode.As shown in figure 11, Cathode electrode 31 is arranged at element area R1 and terminal area R2.
As shown in figure 12, in element area R1, at n-It is provided with p-type semiconductor region 3 on type semiconductor regions 2. It in p-type semiconductor region 3, for example, is selectively provided with p+Type semiconductor regions 9.p+Type semiconductor regions 9 is also May be disposed on the whole surface of p-type semiconductor region 3.
p+The through p-type semiconductor region of type semiconductor regions 93, p+A part for type semiconductor regions 9 also can reach n- Type semiconductor regions 2.I.e., it is possible to be p+A part for type semiconductor regions 9 is surrounded by p-type semiconductor region 3, and p+Another part of type semiconductor regions 9 is by n-Type semiconductor regions 2 surrounds.
P-type semiconductor region 3 and p+Type semiconductor regions 9 is electrically connected with cathode electrode 31.With regard to cathode electrode 31 Construction, the identical construction of source electrode 31 with explanation in the 1st embodiment can be used.With regard to other for example Electrode 33 and the construction of electrode 35, it is also possible to use the construction identical with the construction of explanation in the 1st embodiment.n+Type Semiconductor regions the 5th, electrode 33 and electrode 35 have big with the current potential of anode electrode 30 in a same manner as in the first embodiment Cause identical current potential.
Even if in the present embodiment, it is possible to suppress in a same manner as in the first embodiment because of at electrode 33 and cathode electrode 31 Between produce electric field caused by semiconductor device withstanding voltage variation.
Carrier concentration in each semiconductor regions can be regarded as equal with the effective impurity concentration in each semiconductor regions. Height accordingly, with respect to the relativity of the impurity concentration between each semiconductor regions in each embodiment discussed above Low, for instance, it is possible to use SCM (Scanning Capacitance Microscopy, sweep type electrostatic capacitance microscope) to enter Row confirms.
Above, although exemplified with some embodiments of the present invention, but these embodiments propose as example, It is not intended to limit the scope of invention.The embodiment of these novelties can be implemented with other various forms, and can not take off In the range of the purport of invention, carry out various omission, replacement, change etc..These embodiments or its variation comprise It in the scope or purport of invention, and is contained in the scope of invention described in claims and equalization thereof.Additionally, Described each embodiment can be mutually combined and implement.

Claims (15)

1. a semiconductor device, it is characterised in that possess:
1st semiconductor regions of the 1st conductivity type, comprises the 1st region and the 2nd region, and the 2nd region is arranged at Around 1 region；
2nd semiconductor regions of the 2nd conductivity type, is arranged at described 1st semiconductor regions in described 1st region On；
3rd semiconductor regions of the 1st conductivity type, is arranged at described 1st semiconductor regions in described 2nd region On；
1st electrode, is arranged on described 3rd semiconductor regions, described 1st electrode and described 3rd semiconductor region Territory is electrically connected with；
1st insulating barrier, is arranged on described 1st electrode；And
2nd electrode, is arranged on described 2nd semiconductor regions, described 2nd electrode and described 2nd semiconductor region Territory is electrically connected with, and a part for described 2nd electrode is positioned on described 1st insulating barrier.
2. semiconductor device according to claim 1, it is characterised in that: a part for described 1st electrode is relative to institute State the 3rd semiconductor regions and be arranged at described 1st area side.
3. semiconductor device according to claim 2, it is characterised in that: described 2nd electrode comprises part 1, and
Described part 1 on from described 1st semiconductor regions towards the 1st direction of described 2nd semiconductor regions, Overlapping with at least a portion of described 1st electrode across described 1st insulating barrier.
4. semiconductor device according to claim 3, it is characterised in that: described part 1 is set to ring-type.
5. semiconductor device according to claim 1, it is characterised in that be also equipped with being arranged at described 1st semiconductor regions On the 4th semiconductor regions of the 2nd conductivity type, described 4th semiconductor regions is positioned at described 2nd semiconductor regions Around, and described 4th semiconductor regions is surrounded by described 3rd semiconductor regions.
6. semiconductor device according to claim 1, it is characterised in that be also equipped with:
5th semiconductor regions of the 1st conductivity type, is arranged on described 2nd semiconductor regions；
Gate electrode；And
Gate insulator, at least a portion is arranged between described 2nd semiconductor regions and described gate electrode.
7. semiconductor device according to claim 1, it is characterised in that be also equipped with the 6th semiconductor region of the 2nd conductivity type Territory, at least a portion of described 6th semiconductor regions surrounded by described 2nd semiconductor regions, and the described 6th half The carrier concentration of the 2nd conductivity type of conductive region is higher than the current-carrying of the 2nd conductivity type of described 2nd semiconductor regions Sub-concentration.
8. semiconductor device according to claim 6, it is characterised in that be also equipped with being arranged on described gate electrode 3 electrodes, described 3rd electrode is electrically connected with described gate electrode, and a part for described 3rd electrode is arranged at On described 1st insulating barrier.
9. semiconductor device according to claim 6, it is characterised in that be also equipped with the 2nd conductivity type the multiple 7th half is led Body region, each described 7th semiconductor regions is arranged at described 1st semiconductor regions and described 2nd semiconductor region Between territory, and each described 7th semiconductor regions is surrounded by described 1st semiconductor regions.
10. semiconductor device according to claim 9, it is characterised in that: each described 7th semiconductor regions is along relatively Extend in the 2nd vertical direction of the 1st direction from described 1st semiconductor regions towards described 2nd semiconductor regions, And
The plurality of 7th semiconductor regions is 3rd side vertical relative to described 1st direction and described 2nd direction Upwards arranged side by side.
11. semiconductor devices according to claim 10, it is characterised in that: the 2nd of each described 7th semiconductor regions The carrier concentration of conductivity type is less than the carrier concentration of the 2nd conductivity type of described 2nd semiconductor regions.
12. semiconductor devices according to claim 6, it is characterised in that be also equipped with being arranged at described 1st semiconductor regions Under the 8th semiconductor regions of the 2nd conductivity type.
13. semiconductor devices according to claim 12, it is characterised in that: the 2nd of described 8th semiconductor regions is led The carrier concentration of electricity type is higher than the carrier concentration of the 1st conductivity type of described 1st semiconductor regions.
14. semiconductor devices according to claim 1, it is characterised in that: described 1st insulating barrier comprises the oxygen of semiconductor Compound or the oxide of metal.
15. semiconductor devices according to claim 2, it is characterised in that be also equipped with by the 4th of described 1st electrodes surrounding the Electrode, a part for described 4th electrode is arranged at a described part for described 1st electrode and described 1st semiconductor Between region, another part of described 4th electrode is arranged at another part and the described 3rd half of described 1st electrode Between a part for conductive region.
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CN112447833A (en) * 2019-09-05 2021-03-05 株式会社东芝 Semiconductor device with a plurality of semiconductor chips
CN112447833B (en) * 2019-09-05 2024-06-04 株式会社东芝 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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CN112447833A (en) * 2019-09-05 2021-03-05 株式会社东芝 Semiconductor device with a plurality of semiconductor chips
CN112447833B (en) * 2019-09-05 2024-06-04 株式会社东芝 Semiconductor device with a semiconductor device having a plurality of semiconductor chips

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Application publication date: 20161005