CN105990377A - CMOS image sensor and formation method thereof - Google Patents
CMOS image sensor and formation method thereof Download PDFInfo
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- CN105990377A CN105990377A CN201510046868.XA CN201510046868A CN105990377A CN 105990377 A CN105990377 A CN 105990377A CN 201510046868 A CN201510046868 A CN 201510046868A CN 105990377 A CN105990377 A CN 105990377A
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Abstract
The present invention relates to a CMOS image sensor and a formation method thereof, wherein the CMOS image sensor comprises a semiconductor substrate; a photovoltaic conversion element and a CMOS device layer which are located on the semiconductor substrate; an interlayer dielectric layer covering the semiconductor substrate, the photoelectric conversion element and the CMOS device layer; an intermetallic dielectric layer located on the interlayer dielectric layer, wherein a metal interconnection layer is arranged inside the intermetallic dielectric layer, and is characterized by also comprising a through hole located above the photoelectric conversion element, wherein the through hole penetrates the intermetallic dielectric layer and the interlayer dielectric layer of at least partial thickness a transparent substrate sealing a top opening of the through hole; and a color filtering layer located on the transparent substrate. The light response sensitivity of the CMOS image sensor is improved.
Description
Technical field
The present invention relates to field of image sensors, particularly relate to a kind of cmos image sensor and formation thereof
Method.
Background technology
Generally, semiconductor image sensor has charge-coupled image sensor (CCD) and cmos image
Sensor (CIS) two kinds.The electric capacity of many marshallings is had, it is possible to sense on charge-coupled image sensor
Answer light, and video conversion is become digital signal.And cmos image sensor be by photodiode and
Cmos device forms, and turns including as quick cell array, row/column driver, time sequence control logic, AD
Parallel operation, data/address bus delivery outlet and control bus etc., and these ingredients generally may be integrated into
On same chip.Compared to charge coupled sensor part, cmos image sensor has the most anti-
The advantages such as interference performance, therefore cmos image sensor is widely used in the consumption such as mobile phone, PC
In electronic product.
Refer to Fig. 1, existing cmos image sensor generally includes following structure: Semiconductor substrate 100,
Form photo-electric conversion element 110 on a semiconductor substrate 100 and cmos device layer 120, cover light
The interlayer dielectric layer (ILD) 130 of electric transition element 110 and cmos device layer 120, is positioned at interlayer and is situated between
Intermetallic dielectric layer (IMD) 140 on matter layer 130, intermetallic dielectric layer 140 is internal have one layer or
Person's multiple layer metal interconnection layer 150 (showing three layers in Fig. 1), has between metal interconnecting layer 150 in other words
There is intermetallic dielectric layer 140, the colour filter (color filter) 160 being positioned on intermetallic dielectric layer 140,
And the microlens layer (lens) 170 being positioned on colour filter 160.
In existing cmos image sensor as shown in Figure 1, light (as shown in arrow each in Fig. 1,
Do not mark) need through microlens layer 170, colour filter 160, intermetallic dielectric layer 140 and inter-level dielectric
Layer 130 gets to photo-electric conversion element 110 to carry out the conversion (photo-electric conversion element 110 of photosignal
Internal polygon represents the light received), in this communication process, owing to each Rotating fields all has phase
The refraction action answered, each layer is internal and between different layers it also occur that diffusing scattering effect, and some layer knot
Structure (such as metal interconnecting layer) also has reflection to light, so that corresponding light loses in a large number,
The optical signal ultimately resulting in cmos image sensor acquisition is more weak, greatly have impact on cmos image and passes
The light responsing sensitivity of sensor.
Summary of the invention
The problem that the present invention solves is to provide a kind of cmos image sensor and forming method thereof, to reduce
Light loss during traveling to photo-electric conversion element, thus strengthen cmos image sensor and obtain
Optical signal, improve cmos image sensor light responsing sensitivity.
For solving the problems referred to above, the present invention provides a kind of cmos image sensor, including:
Semiconductor substrate；
It is positioned at the photo-electric conversion element in described Semiconductor substrate and cmos device layer；
Cover described Semiconductor substrate, photo-electric conversion element and the interlayer dielectric layer of cmos device layer；
It is positioned at the intermetallic dielectric layer on described interlayer dielectric layer, in described intermetallic dielectric layer, there is metal
Interconnection layer；
Also include:
Be positioned at the through hole above described photo-electric conversion element, described through hole run through described intermetallic dielectric layer and
At least partly described interlayer dielectric layer of thickness；
Seal the transparency carrier of described via top opening；
It is positioned at the colour filter on described transparency carrier.
Optionally, the reflecting layer being positioned at described through-hole side wall is also included.
Optionally, the refractive index in described reflecting layer is more than 2.0.
Optionally, the thickness range in described reflecting layer is
Optionally, the material in described reflecting layer is at least one of silicon nitride or silicon oxynitride.
Optionally, the angular range between described through-hole side wall and via bottoms is 75 °～85 °.
Optionally, described transparency carrier is sealed into vacuum sealing to described through hole.
Optionally, the described inter-level dielectric layer thickness that described via bottoms retains is less than or equal to
For solving the problems referred to above, present invention also offers the forming method of a kind of cmos image sensor,
Including:
Semiconductor substrate is provided；
Form photo-electric conversion element and cmos device layer on the semiconductor substrate；
Form interlayer dielectric layer and cover described Semiconductor substrate, photo-electric conversion element and cmos device layer；
Described interlayer dielectric layer is formed intermetallic dielectric layer and metal interconnecting layer, described metal interconnecting layer
It is positioned at described intermetallic dielectric layer；
Above described photo-electric conversion element formed through hole, described through hole run through described intermetallic dielectric layer and
At least partly described interlayer dielectric layer of thickness；
Transparency carrier is used to seal described via top opening；
Described transparency carrier is formed colour filter.
Optionally, after forming described through hole, and before sealing described via top opening, it is additionally included in
Described through-hole side wall forms the step in reflecting layer.
Optionally, the ranges of indices of refraction in described reflecting layer is more than 2.0.
Optionally, the thickness range in described reflecting layer is
Optionally, the material in described reflecting layer is at least one of silicon nitride or silicon oxynitride.
Optionally, the angular range between described through-hole side wall and via bottoms is 75 °～85 °.
Optionally, vacuum sealing technology is used to seal described via top opening.
Compared with prior art, technical scheme has the advantage that
In technical scheme, run through intermetallic dielectric layer and at least part of thick layer by producing
Between the through hole of dielectric layer so that light can arrive photo-electric conversion element by through hole, decrease light at gold
Loss in dielectric layer and at least part of thickness interlayer dielectric layer between genus, so that photo-electric conversion element obtains
Light signal strength increase, improve cmos image sensor light responsing sensitivity.
Further, by forming reflecting layer at through-hole side wall, the light that arrives photo-electric conversion element is significantly increased
Line, thus the light responsing sensitivity of cmos image sensor is greatly improved.
Further, use vacuum sealing technology to seal through hole, thus improve the reliability of through hole inner structure,
Improve the durability of whole cmos image sensor.
Accompanying drawing explanation
Fig. 1 is existing CMOS image sensor structure schematic diagram；
Fig. 2 to Fig. 6 is that the forming method of the cmos image sensor that the embodiment of the present invention is provided respectively walks
Rapid counter structure schematic diagram.
Detailed description of the invention
As described in background, existing cmos image sensor photoinduction sensitivity is low, this is because
The structure of existing cmos image sensor is limited: light has to pass through corresponding intermetallic dielectric layer and layer
Between dielectric layer can arrive photo-electric conversion element, in this process, light at intermetallic dielectric layer and
Interlayer dielectric layer is internal there is the effects such as diffuse-reflectance, causes light to lose in a large number, so that photoelectric conversion element
The optical signal that part receives significantly weakens.
To this end, the present invention provides a kind of new cmos image sensor and forming method thereof, described CMOS
Imageing sensor has the through hole being positioned at above photo-electric conversion element, and described through hole runs through intermetallic dielectric layer,
And being through to the interlayer dielectric layer of small part thickness, so, substantial amounts of light can be by described simultaneously
Through hole directly arrives photo-electric conversion element, or substantial amounts of light can by described through hole and thickness relatively
Little interlayer dielectric layer arrives photo-electric conversion element, thus light that photo-electric conversion element receive is greatly improved
Signal intensity, improves the light responsing sensitivity of cmos image sensor.
Meanwhile, the sidewall of described through hole has reflecting layer, and reflecting layer can make to avoid being irradiated to described through-hole side
The light of wall is in sidewall generation diffuse-reflectance, and makes to enter into most light of via top opening all
Arrive photo-electric conversion element, further increase the light signal strength that photo-electric conversion element receives, enter one
Step improves the light responsing sensitivity of cmos image sensor.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
The embodiment of the present invention provides the forming method of a kind of cmos image sensor, incorporated by reference to reference to Fig. 2
To Fig. 6.
Incorporated by reference to Fig. 2, it is provided that Semiconductor substrate 200, form photoelectric conversion element on semiconductor substrate 200
Part 210 and cmos device layer 220, then formed interlayer dielectric layer 230 cover Semiconductor substrate 200,
Photo-electric conversion element 210 and cmos device layer 220, and formed between metal on interlayer dielectric layer 230
Dielectric layer 240 and metal interconnecting layer 250.Wherein, metal interconnecting layer 250 is positioned at intermetallic dielectric layer 240
In.
In the present embodiment, Semiconductor substrate 200 can be silicon substrate, and Semiconductor substrate shown in Fig. 2
200 can be a portion of a Silicon Wafer, and described Silicon Wafer is used for making multiple cmos image
Sensor, after completing, then by follow-up packaging technology to each cmos image sensor
Separate.
In other embodiments of the invention, Semiconductor substrate 200 can also be germanium silicon substrate, III-V race
Element compound substrate, silicon carbide substrates or its laminated construction substrate, or silicon-on-insulator substrate, also may be used
Being to well known to a person skilled in the art other suitable semiconductive material substrate.
In the present embodiment, photo-electric conversion element 210 can be photodiode (photodiode), and
Concrete photodiode can have PN junction structure, it is possible to have PIN junction structure.
In the present embodiment, in cmos device layer 220, each photo-electric conversion element 210 can be with 3
The transistor arrangement of transistor arrangement, 4 transistor arrangements or more than 5 forms corresponding circuit structure.
Wherein, described transistor can include that transistor and row choosing are followed in reset transistor, transfering transistor, source
Logical transistor etc..The structure of concrete cmos device layer 220 is referred to existing cmos image sensing
Device internal structure, is not described in detail at this.
In the present embodiment, the material of interlayer dielectric layer 230 can be silicon oxide, can use deposition process
Form interlayer dielectric layer 230.Interlayer dielectric layer 230 can also form contact hole after being formed therein, and
Contact plunger (not shown) is formed in contact hole, so that the CMOS covered by interlayer dielectric layer 230
Device layer 220 can electrically connect with the metal interconnecting layer 250 being subsequently formed.
In the present embodiment, the material of intermetallic dielectric layer 240 can also be silicon oxide, equally uses
Deposition process forms intermetallic dielectric layer 240.
In the present embodiment, the material of metal interconnecting layer 250 can be aluminum, copper or tungsten etc., can pass through
Depositing operation and etching technics form metal interconnecting layer 250.
It should be noted that metal interconnecting layer 250 and intermetallic dielectric layer 240 can replace repeatedly landform
Become.Such as it is initially formed layer of metal interconnection layer 250, then forming intermetallic dielectric layer 240, to cover this metal mutual
Even layer 250, but on this layer of intermetallic dielectric layer 240, form another layer of metal interconnecting layer 250, and again
Secondary intermetallic dielectric layer 240 covers this metal interconnecting layer 250, the most reciprocal.Fig. 2 shows shape
Become metal interconnecting layer 250 structure of three layers, in other embodiments, it is also possible to form two-layer or four
The metal interconnecting layer 250 that layer is above, this is not construed as limiting by the present invention.
Refer to Fig. 3, form through hole 201 above photo-electric conversion element 210, through hole 201 runs through metal
Between dielectric layer 240 and part interlayer dielectric layer 230.
In the present embodiment, the process forming through hole 201 may include that shape on intermetallic dielectric layer 240
Becoming the mask layer 260 of patterning, mask layer 260 can be photoresist layer, it is also possible to be such as silicon nitride material
The hard mask layer of material；Then, with patterning mask layer 260 as mask, be sequentially etched inter-metal medium
Layer 240 and interlayer dielectric layer 230, until the interlayer dielectric layer 230 of remainder thickness, now formed logical
Hole 201.
In above-mentioned forming process, either employing photoresist layer or hard mask layer are as mask, the most all
Need to increase by one light shield technique.Such as when using photoresist layer, can be between the metal of whole wafer
Photoresist is coated on dielectric layer 240, the most exposed and developed, will need to be formed the position of through hole 201
Photoresist layer remove, formed patterning photoresist layer, this patterning photoresist layer as patterning
Mask layer 260.
In the present embodiment, the technique that etching intermetallic dielectric layer 240 and interlayer dielectric layer 230 are used can
Think dry etch process.Owing to the material of intermetallic dielectric layer 240 and interlayer dielectric layer 230 is oxidation
Silicon, thus the main etching gas that described dry etch process uses can be CF4, C4F8 and CHF3
At least one.In other embodiments of the invention, it is also possible to select other suitable gas, this
Bright this is not construed as limiting.
In the present embodiment, bottom through hole 201 retain interlayer dielectric layer 230 thickness (as it is shown on figure 3,
Do not mark) it is less than or equal toThat is remaining interlayer dielectric layer 230 thickness is less than or equal to
Through hole 201 root remaining portion interlayer dielectric layer 230 can protect photo-electric conversion element 210 upper surface to exempt from
By the corrasion of etching technics (described etching technics refers to the etching technics used when through hole 201 is formed),
But also result in subsequent ray to need to be then passed through remaining interlayer dielectric layer 230 and get to opto-electronic conversion simultaneously
Element 210.In order to balance the relation of this conflict so that the performance of cmos image sensor reaches
Ideal level, the residual thickness controlling interlayer dielectric layer 230 existsBelow.
It should be noted that in other embodiments of the invention, through hole 201 can also run through gold simultaneously
Dielectric layer 240 and interlayer dielectric layer 230 between genus, when i.e. forming through hole 201, run through whole gold being etched to
Between genus after dielectric layer 240, continue to be etched to run through whole interlayer dielectric layer 230, the through hole ultimately formed
There is no remaining interlayer dielectric layer 230 bottom 201, but serve as a contrast with photo-electric conversion element 210 place quasiconductor
Surface, the end 200 as through hole 201 bottom.Further, there is not residue interlayer bottom this through hole 201 to be situated between
The scheme of matter layer 230 advantageously arrives photo-electric conversion element 210 in light, therefore, it is possible to carry further
The performance of high cmos image sensor.But need to note controlling corresponding etching process not to photoelectricity simultaneously
Conversion element 210 surface adversely affects.
In the present embodiment, bottom through hole 201 sidewall and through hole 201 between angle α in the range of
75 °～85 °.As it is shown on figure 3, angle α refers to place bottom through hole 201 sidewall place plane and through hole 201
The angle less than or equal to 90 ° that plane is constituted.Owing to the characteristic of dry etching itself determines that through hole 201 can be in
Existing shape wide at the top and narrow at the bottom, so through hole 201 base angle is typically larger than 90 °, therefore angle α would generally be logical
The supplementary angle at base angle, hole 201 rather than through hole 201 base angle itself.The size of angle α needs to consider through hole
Photo-electric conversion element 210 bottom distance between 201 open tops and metal interconnecting wires, and through hole 201
Two factors of area.In order to ensure that through hole 201 open top is relatively big, to collect more light,
Ensure that again through hole 201 bottom area, not less than photo-electric conversion element 210 upper surface area, arranges folder
Angle α is in the range of 75 °～85 °.
In the present embodiment, above photo-electric conversion element 210, form through hole 201, so that photoelectric conversion element
Part 210 is positioned at the bottom part down of through hole 201.Because subsequent ray needs to arrive light through through hole 201
Electric transition element 210.Therefore, the present embodiment can control the shape bottom so that through hole 201 and area with
Shape and the area of photo-electric conversion element 210 upper surface are of substantially equal, or the area bottom through hole 201
Slightly larger than photo-electric conversion element 210 upper surface area.Due to through hole 201 structure the most wide at the top and narrow at the bottom
(corresponding etching technics determines through hole 201 and has structure wide at the top and narrow at the bottom, above-mentioned through hole 201 sidewall
Inclination angle also further demonstrated that this structure wide at the top and narrow at the bottom), therefore, bottom through hole 201, be positioned at light
During electric transition element 210 (just) top, through hole 201 other parts are also all located at photo-electric conversion element 210
(just) top and tiltedly (just) top.
In the present embodiment, the open top diameter (mark) of through hole 201 depend on metal interconnecting wires it
Between distance.In order to enable more collection light, as long as the open top diameter of through hole 201 interconnects than metal
Slightly smaller the getting final product of distance between line (refers between metal interconnecting wires make the gold near through hole 201 position herein
Belong between interconnection line), such as when the distance between metal interconnecting wires is 1 μm, the top of through hole 201 is opened
Mouth diameter substantially can be in 0.5 μm～1 μm.
In the present embodiment, in the position that through hole 201 is formed, intermetallic dielectric layer 240 originally and interlayer
Dielectric layer 230 is internal does not all have conductive structure or device architecture.This is because, these positions originally
Directly over photo-electric conversion element 210 and in certain limit tiltedly directly over intermetallic dielectric layer 240 and layer
Between dielectric layer 230 be also required to by light, therefore, originally would not be at these Position Design conductive structures
Or device architecture.It is to say, these positions are exactly intermetallic dielectric layer 240 and interlayer dielectric layer originally
230, therefore, the formation of through hole 201 does not interferes with cmos image sensor between metal at all
Between any structure between dielectric layer 240 and interlayer dielectric layer 230.
Although it should be noted that display there remains patterning after forming through hole 201 in Fig. 3
Mask layer, but, during actual process, mask layer 260 can be in the process forming through hole 201
Middle etched removal in the lump, or can also individually be used corresponding removal after through hole 201 is formed
Technique removes remaining mask layer 260.
Refer to Fig. 4, form reflecting layer 270 at through hole 201 sidewall.
In the present embodiment, the ranges of indices of refraction in reflecting layer 270 is more than 2.0.Control the folding in reflecting layer 270
Rate of penetrating, more than 2.0, is the reflectance in order to improve reflecting layer 270.Generally reflecting layer 270 is the highest more good,
Reflectance is the highest, and light loss amount during arriving photo-electric conversion element 210 is the fewest, final photoelectricity
The light signal strength that conversion element 210 obtains is the biggest.But, the medium of non-specular surface, such as the present embodiment
The reflecting layer used, all many factors such as the attribute of its reflectance and color, temperature and the light of medium have
Close.And when light is close to normal incidence (i.e. incidence angle θ approximates 0), reflectance computing formula is:
R=(n1-n2)2/(n1+n2)2
Wherein, n1And n2The refractive index being reflecting layer 270 respectively is (the most relative with the true refractive index of air
Refractive index in vacuum).Refractive index refers to the ratio of light speed in a vacuum and light speed within this material
Rate.The refractive index of material is the highest, makes incident illumination occur the ability reflected the strongest, the highest material of usual refractive index
The reflectance of material is the strongest.Therefore in the present embodiment, refractive index n1More than 2.0.I.e. in order to obtain
Ideal light signal strength, the refractive index in control reflecting layer 270 is more than 2.0, thus ensures reflection
The reflection of a large amount of light is arrived photo-electric conversion element 210 by layer 270.
Certainly, in other embodiments of the present invention, if reflecting layer 270 can be fabricated to minute surface medium,
Then its reflectance can reach 100%, and reflecting effect is more preferable.
In the present embodiment, the material in reflecting layer 270 can be silicon nitride or silicon oxynitride at least within
One of.Silicon nitride or silicon oxynitride can be fabricated to the anti-of high reflectance according to the adjustment of processing technology
Penetrate layer 270, so that more light can directly arrive photo-electric conversion element 210 by through hole 201,
And silicon nitride or silicon oxynitride often use in the semiconductor structure, processing technology is ripe.Need
Bright, in other embodiments of the invention, reflecting layer 270 can also select other suitable material.
In the present embodiment, the thickness range in reflecting layer 270 isReflecting layer 270 needs tool
Standby certain thickness can preferably realize corresponding reflecting effect, therefore, generally controls its thickness and existsAbove.Meanwhile, reflecting layer 270 thickness if greater thanNot only extend the work of processing technology
The skill cycle, and cause the aperture area of through hole 201 to reduce, therefore, control the thickness in reflecting layer 270
?Below.
In the present embodiment, the process forming reflecting layer 270 can be: utilizes chemical gaseous phase to deposit (CVD)
Technique directly deposits formation in the bottom of through hole 201 and sidewall surfacesSilicon oxynitride thin
Film or silicon nitride film are using as layer of reflective material；Then the anisotropic feature of dry etching is utilized to lead to
Layer of reflective material bottom hole 201 etches away, and retains the layer of reflective material on sidewall, this remaining reflection
Material layer is reflecting layer 270.Owing to the layer of reflective material having only to bottom through hole 201 is removed, on sidewall
Layer of reflective material be intended to retain, so being typically only capable to use the anisotropic etching method such as dry etching,
And if with wet-etching technology, then the layer of reflective material on through hole 201 sidewall also can be removed.
It should be noted that the making in reflecting layer 270 can roll up arrival photo-electric conversion element 210
Light, improve cmos image sensor light responsing sensitivity.And without reflecting layer 270,
Light enters after through hole 201, has the dielectric layer that major part injects in through hole 201 sidewall (described
Dielectric layer includes intermetallic dielectric layer 240 and interlayer dielectric layer 230), and absorbed by described dielectric layer or
Sidewall surfaces diffuse-reflectance, causes some light can not effectively arrive photo-electric conversion element 210, thus causes total
When body optical signal strength ratio does not has a reflecting layer 270 weak.But, in other embodiments of the invention,
If do not make reflecting layer 270, remain able to reach corresponding light responsing sensitivity by through hole 201
Demand, then can make reflecting layer 270 at through hole 201 sidewall.
Refer to Fig. 5, use transparency carrier 280 to seal through hole 201 open top.
In the present embodiment, the material of transparency carrier 280 can be quartz glass.In other embodiments, thoroughly
The material of bright substrate 280 can also be the materials such as lucite.
In the present embodiment, vacuum sealing technology is used to seal through hole 201.Concrete, can be in vacuum environment
Under carry out bonding or welding procedure, and use between adhesive 202 bonded metal as shown in Figure 5
Dielectric layer 240 and transparency carrier 280, thus transparency carrier 280 is bonded together with wafer.Gluing glue
To fully seal between transparency carrier 280 and through hole 201, and in described bonding process under vacuum condition
Carry out, so that through hole 201 obtains vacuum and seals.
When use vacuum-packed method time, be vacuum environment in through hole 201, can reduce in a large number air and
The scattering process to light such as moisture, light is lost in communication process can be less, so that CMOS figure
As the light responsing sensitivity of sensor is higher.Meanwhile, vacuum environment is prevented from reflecting layer 270 by air
Or the pollution of moisture, additionally it is possible to improve reliability and the ruggedness of cmos image sensor further.
It should be noted that in other embodiments of the invention, it is also possible to vacuum need not be used to seal,
And use transparency carrier 280 to be sealed in through hole 201 non-real vacant lot.
Please continue to refer to Fig. 5, transparency carrier 280 forms colour filter 290.Colour filter 290 can also
Being referred to as color filtering array layer, it generally includes redness, green and the color-filter unit of blue three kinds of array arrangements,
Its effect and formation process are well known to those skilled in the art, and do not repeat them here.
In the present embodiment, colour filter 290 is directly produced on transparency carrier 280.In other embodiments
In, other Rotating fields can also be comprised between transparency carrier 280 and colour filter 290.
Refer to Fig. 6, colour filter 290 is formed microlens layer 203.The effect of microlens layer 203 and
Formation process is well known to those skilled in the art, and does not repeats them here.
Though not shown in figure, the present embodiment is follow-up can be to each cmos image sensor on wafer
Carry out corresponding packaging technology, then each cmos image sensor is carried out cutting and separates.Cut through
Cheng Zhong, if transparency carrier 280 is en-block construction when being sealed on wafer, needs transparency carrier 280
It is also carried out cutting.When specifically cutting, conventional blades cutting technique can be used to cut transparency carrier 280, also
Laser cutting parameter can be used to cut transparency carrier 280.But, when transparency carrier 280 number with
Cmos image sensor is equal, and is mutually separated from each other between each transparency carrier 280 during correspondence,
The most then need not transparency carrier 280 is cut.
In the forming method of the cmos image sensor that the present embodiment is provided, run through gold by producing
Dielectric layer 240 and the through hole 201 of at least part of thickness interlayer dielectric layer 230 between genus, so that light (as
In Fig. 6 shown in each arrow, do not mark) photo-electric conversion element 210 can be arrived by through hole 201, decrease light
Line loss in intermetallic dielectric layer 240 and at least part of thickness interlayer dielectric layer 230, so that light
The light signal strength that electric transition element 210 obtains increases, and improves the photoresponse spirit of cmos image sensor
Sensitivity.
The present embodiment by forming reflecting layer 270 at through hole 201 sidewall, is significantly increased arrival photoelectricity further
The light of conversion element 210, thus the light responsing sensitivity of cmos image sensor is greatly improved.
The present embodiment uses vacuum sealing technology to seal through hole 201 further, thus ties in improving through hole 201
The reliability of structure, improves the durability of whole cmos image sensor.
Another embodiment of the present invention also provides for a kind of cmos image sensor, and described cmos image senses
The forming method that device can use previous embodiment to be provided is formed, and therefore, described cmos image senses
Device is referred to previous embodiment corresponding contents.
Concrete, incorporated by reference to reference to Fig. 6, the cmos image sensor that the present embodiment is provided includes half
Conductor substrate 200, the photo-electric conversion element 210 being positioned in Semiconductor substrate 200 and cmos device layer
220, the interlayer covering Semiconductor substrate 200, photo-electric conversion element 210 and cmos device layer 220 is situated between
Matter layer 230, the intermetallic dielectric layer 240 being positioned on interlayer dielectric layer 230, in intermetallic dielectric layer 240
There is metal interconnecting layer 250.Further, described cmos image sensor also includes being positioned at photoelectric conversion element
Through hole 201 above part 210, through hole 201 runs through intermetallic dielectric layer 240 and the layer of at least part of thickness
Between dielectric layer 230, be positioned at the reflecting layer 270 of through hole 201 sidewall, seal through hole 201 open-topped
Bright substrate 280, as shown in Figure 6, transparency carrier 280 is bonded in inter-metal medium by adhesive 202
On layer 240.Described cmos image sensor also includes the colour filter 290 being positioned on transparency carrier 280,
And the microlens layer 203 being positioned on colour filter 290.
In the present embodiment, Semiconductor substrate 200 can be silicon substrate.In other embodiments of the invention,
Semiconductor substrate 200 can also be germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or
Its laminated construction substrate, or silicon-on-insulator substrate, it is also possible to be to well known to a person skilled in the art other
Suitably semiconductive material substrate.
In the present embodiment, photo-electric conversion element 210 can be photodiode (photodiode), and
Concrete photodiode can have PN junction structure, it is possible to have PIN junction structure.
In the present embodiment, in cmos device layer 220, each photo-electric conversion element 210 can be with 3
The transistor arrangement of transistor arrangement, 4 transistor arrangements or more than 5 forms corresponding circuit structure.
Wherein, described transistor can include that transistor and row choosing are followed in reset transistor, transfering transistor, source
Logical transistor etc..Concrete cmos device layer 220 structure is referred to existing cmos image sensing
Device internal structure, is not described in detail at this.
In the present embodiment, the material of interlayer dielectric layer 230 can be silicon oxide.In interlayer dielectric layer 230
Portion can have contact plunger (not shown), so that the CMOS covered by interlayer dielectric layer 230
Device layer 220 can electrically connect with the metal interconnecting layer 250 being subsequently formed.
In the present embodiment, the material of intermetallic dielectric layer 240 can also be silicon oxide.
In the present embodiment, the material of metal interconnecting layer 250 can be aluminum, copper or tungsten etc..
It should be noted that metal interconnecting layer 250 and intermetallic dielectric layer 240 can be alternately stacked.Example
As Fig. 6 shows the metal interconnecting layer 250 of three layers alternately stacked with intermetallic dielectric layer 240 together with,
In other embodiments, it is also possible to be to be situated between two-layer or the metal interconnecting layer 250 of more than four layers and metal
Matter layer 240 is alternately stacked, and this is not construed as limiting by the present invention.
In the present embodiment, the ranges of indices of refraction in reflecting layer 270 is more than 2.0.Control the folding in reflecting layer 270
Rate of penetrating, more than 2.0, is the reflectance in order to improve reflecting layer 270.Generally reflecting layer 270 is the highest more good,
Reflectance is the highest, and light loss amount during arriving photo-electric conversion element 210 is the fewest, final photoelectricity
The light signal strength that conversion element 210 obtains is the biggest.But, the medium of non-specular surface, such as the present embodiment
The reflecting layer used, all many factors such as the attribute of its reflectance and color, temperature and the light of medium have
Close.And when light is close to normal incidence (i.e. incidence angle θ approximates 0), reflectance computing formula is:
R=(n1-n2)2/(n1+n2)2
Wherein, n1And n2The refractive index being reflecting layer 270 respectively is (the most relative with the true refractive index of air
Refractive index in vacuum).Refractive index refers to the ratio of light speed in a vacuum and light speed within this material
Rate.The refractive index of material is the highest, makes incident illumination occur the ability reflected the strongest, the highest material of usual refractive index
The reflectance of material is the strongest.Therefore in the present embodiment, refractive index n1More than 2.0.I.e. in order to obtain
Ideal light signal strength, the refractive index in control reflecting layer 270 is more than 2.0, thus ensures reflection
The reflection of a large amount of light is arrived photo-electric conversion element 210 by layer 270.
Certainly, in other embodiments of the present invention, if reflecting layer 270 can be fabricated to minute surface medium,
Then its reflectance can reach 100%, and reflecting effect is more preferable.
In the present embodiment, the thickness range in reflecting layer 270 can beReflecting layer 270 needs
Possess certain thickness and can preferably realize corresponding reflecting effect, therefore, generally control it thick
SpendAbove.Meanwhile, reflecting layer 270 thickness if greater thanNot only extend processing technology
Process cycle, and cause the aperture area of through hole 201 to reduce, therefore, control reflecting layer 270
Thickness existsBelow.
In the present embodiment, the material in reflecting layer 270 can be silicon nitride or silicon oxynitride at least within
One of.Silicon nitride or silicon oxynitride can be fabricated to the reflecting layer 270 of high reflectance according to processing technology,
So that more light can directly arrive photo-electric conversion element 210, and silicon nitride by through hole 201
Or silicon oxynitride often uses in the semiconductor structure, processing technology is ripe.It should be noted that
In other embodiments of the invention, reflecting layer 270 can also select other suitable material.
It should be noted that in other embodiments of the invention, it is also possible to need not be at through hole 201 sidewall
Make reflecting layer 270.In the present embodiment, bottom through hole 201 sidewall and through hole 201 between angle α (as
Shown in Fig. 3) may range from 75 °～85 °.The size of angle α need consider through hole 201 open top with
Bottom distance between metal interconnecting wires, and through hole 201 area of photo-electric conversion element 210 two because of
Element.In order to ensure that through hole 201 open top is relatively big, to collect more light, ensure that again
Through hole 201 bottom area is not less than photo-electric conversion element 210 upper surface area, arranges the scope of angle α
It it is 75 °～85 °.
In the present embodiment, transparency carrier 280 can be that vacuum seals to the sealing of through hole 201.Need
Bright, in other embodiments of the invention, it is also possible to vacuum sealing technology need not be used to seal through hole
201。
In the present embodiment, shape bottom through hole 201 and area and photo-electric conversion element 210 upper surface
Shape and area are of substantially equal, or the area bottom through hole 201 is slightly larger than on photo-electric conversion element 210
Surface area.Due to through hole 201 structure the most wide at the top and narrow at the bottom, (corresponding etching technics determines logical
Hole 201 has structure wide at the top and narrow at the bottom, and the inclination angle of above-mentioned through hole 201 sidewall has also further demonstrated that this
Structure wide at the top and narrow at the bottom), therefore, when being positioned at bottom through hole 201 directly over photo-electric conversion element 210,
Through hole 201 other parts are also all located at directly over photo-electric conversion element 210 and oblique surface.
In the present embodiment, the open top diameter of through hole 201 depends on the distance between metal interconnecting wires.
In order to enable more collection light, if the open top diameter of through hole 201 than between metal interconnecting wires away from
From slightly smaller can (refer between metal interconnecting wires to make herein the metal interconnecting wires near through hole 201 position it
Between), such as when the distance between metal interconnecting wires is 1 μm, the open top diameter of through hole 201 is big
Cause can be in 0.5 μm～1 μm.
In the present embodiment, bottom through hole 201 retain interlayer dielectric layer 230 thickness (as it is shown on figure 3,
Do not mark) it is less than or equal toRetaining interlayer dielectric layer 230 bottom through hole 201 can protect photoelectricity to turn
Change the corrasion from etching technics of element 210 upper surface, but also result in subsequent ray simultaneously and need again
Photo-electric conversion element 210 is got to through remaining interlayer dielectric layer 230.Therefore, in order to balance this
Relation to contradiction so that the performance of cmos image sensor reaches ideal level, key-course
Between the residual thickness of dielectric layer 230 existBelow.
It should be noted that in other embodiments of the invention, through hole 201 can also run through gold simultaneously
Interlayer dielectric layer 230 is not had bottom dielectric layer 240 and interlayer dielectric layer 230, i.e. through hole 201 between genus, and
Be using Semiconductor substrate 200 surface, photo-electric conversion element 210 place as through hole 201 bottom.Further,
The scheme that there is not interlayer dielectric layer 230 bottom this through hole 201 advantageously turns in light arrival photoelectricity
Change element 210, therefore, it is possible to improve the performance of cmos image sensor further.
In the cmos image sensor that the present embodiment is provided, run through intermetallic dielectric layer 240 owing to having
With the through hole 201 of at least part of thickness interlayer dielectric layer 230 so that light is (such as arrow institute each in Fig. 6
Show, do not mark) photo-electric conversion element 210 can be arrived by through hole 201, decrease light at inter-metal medium
Loss in layer 240 and at least part of thickness interlayer dielectric layer 230, so that photo-electric conversion element 210
The light signal strength obtained increases, and improves the light responsing sensitivity of cmos image sensor.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (15)
1. a cmos image sensor, including:
Semiconductor substrate；
It is positioned at the photo-electric conversion element in described Semiconductor substrate and cmos device layer；
Cover described Semiconductor substrate, photo-electric conversion element and the interlayer dielectric layer of cmos device layer；
It is positioned at the intermetallic dielectric layer on described interlayer dielectric layer, in described intermetallic dielectric layer, there is metal
Interconnection layer；
It is characterized in that, also include:
Be positioned at the through hole above described photo-electric conversion element, described through hole run through described intermetallic dielectric layer and
At least partly described interlayer dielectric layer of thickness；
Seal the transparency carrier of described via top opening；
It is positioned at the colour filter on described transparency carrier.
2. cmos image sensor as claimed in claim 1, it is characterised in that also include being positioned at described leading to
The reflecting layer of hole sidewall.
3. cmos image sensor as claimed in claim 2, it is characterised in that the refraction in described reflecting layer
Rate is more than 2.0.
4. cmos image sensor as claimed in claim 2, it is characterised in that the thickness in described reflecting layer
Scope is
5. cmos image sensor as claimed in claim 2, it is characterised in that the material in described reflecting layer
For at least one of silicon nitride or silicon oxynitride.
6. cmos image sensor as claimed in claim 1 or 2, it is characterised in that described through-hole side wall
And the angular range between via bottoms is 75 °～85 °.
7. cmos image sensor as claimed in claim 1 or 2, it is characterised in that described transparency carrier
Described through hole is sealed into vacuum seal.
8. cmos image sensor as claimed in claim 1 or 2, it is characterised in that described via bottoms
The described inter-level dielectric layer thickness retained is less than or equal to
9. the forming method of a cmos image sensor, it is characterised in that including:
Semiconductor substrate is provided；
Form photo-electric conversion element and cmos device layer on the semiconductor substrate；
Form interlayer dielectric layer and cover described Semiconductor substrate, photo-electric conversion element and cmos device layer；
Described interlayer dielectric layer is formed intermetallic dielectric layer and metal interconnecting layer, described metal interconnecting layer
It is positioned at described intermetallic dielectric layer；
Above described photo-electric conversion element formed through hole, described through hole run through described intermetallic dielectric layer and
At least partly described interlayer dielectric layer of thickness；
Transparency carrier is used to seal described via top opening；
Described transparency carrier is formed colour filter.
10. forming method as claimed in claim 9, it is characterised in that after forming described through hole, and close
Before sealing described via top opening, it is additionally included in described through-hole side wall and forms the step in reflecting layer.
11. forming methods as claimed in claim 10, it is characterised in that the ranges of indices of refraction in described reflecting layer is
More than 2.0.
12. forming methods as claimed in claim 10, it is characterised in that the thickness range in described reflecting layer is
13. forming methods as claimed in claim 10, it is characterised in that the material in described reflecting layer is silicon nitride
Or at least one of silicon oxynitride.
14. forming methods as described in claim 9 or 10, it is characterised in that at the bottom of described through-hole side wall and through hole
Angular range between portion is 75 °～85 °.
15. forming methods as described in claim 9 or 10, it is characterised in that use vacuum sealing technology to seal
Described via top opening.
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| WO2018133768A1 (en) * | 2017-01-17 | 2018-07-26 | 苏州晶方半导体科技股份有限公司 | Packaging structure and packaging method for fingerprint recognition chip |
| CN109711229A (en) * | 2017-10-26 | 2019-05-03 | 中芯国际集成电路制造(上海)有限公司 | A kind of fingerprint recognition chip and its manufacturing method and electronic device |
| CN114371521A (en) * | 2022-01-13 | 2022-04-19 | 天津山河光电科技有限公司 | Super-surface optical device covered with reflecting layer, optical equipment and manufacturing method |
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| CN105990377B (en) | 2019-01-29 |
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