CN105990357B - Semiconductor devices and preparation method, the test structure of semiconductor devices and method - Google Patents
Semiconductor devices and preparation method, the test structure of semiconductor devices and method Download PDFInfo
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- 239000000463 material Substances 0.000 claims description 61
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Abstract
The present invention relates to a kind of semiconductor devices and preparation methods, the test structure of semiconductor devices and method.The test structure includes semiconductor substrate；Floating gate is located in the semiconductor substrate；Floating gate oxide, between the semiconductor substrate and the floating gate；Control gate is located on the floating gate；First terminal is connect with the semiconductor substrate；Second terminal is electrically connected with the control gate；Third terminal is electrically connected with the floating gate of exposing.The advantages of test structures and methods of the present invention, is: (1) can be tested by online WAT to monitor the boundary layer between the floating gate of peripheral region device and control gate.(2) when there are boundary layers between the floating gate and control gate of the peripheral region device, detection structure of the present invention still can be with capacitor-current curve of accurate detection to gate oxide, and feeds back and obtain the thickness of accurate gate oxide.
Description
Technical field
The present invention relates to semiconductor storage units, in particular it relates to a kind of semiconductor devices and preparation method, half
The test structure and method of conductor device.
Background technique
With high speed development (such as mobile phone, digital camera, MP3 player and the PDA of portable electronic device
Deng), the requirement for data storage is higher and higher.Nonvolatile flash memory is due to the spy for remaining to save data under power blackout situation
Point becomes most important storage unit in these equipment, wherein since flash memory (flash memory) can achieve very high core
Piece storage density, and without introducing new material, manufacturing process is compatible, therefore, can be easier more reliable being integrated into and gather around
Have in digital and analog circuit.
NOR and NAND is that two kinds of main nonvolatile flash memory technologies, NOR flash memory (Flash) device belong to currently on the market
One kind of nonvolatile flash memory, its main feature is that executing in chip, such application program can directly be run in Flash flash memory, no
Code must be read in system RAM (random access memory) again, to make it have higher efficiency of transmission.
It is continuous with dimensions of semiconductor devices for nonvolatile memory (Nonvolatile memories, NVM)
It reduces, pitch also constantly reduces, and relevant technique cannot reuse self aligned polysilicon process, wherein in the peripheral region of memory
In include floating gate polysilicon and control gate polysilicon stacking.
When having boundary layer between the floating gate polysilicon and control gate polysilicon, the boundary layer will will affect wafer
The accuracy of acceptable test (wafer acceptance test, WAT), especially influences whether the gate dielectric thickness
The measurement of degree still further comprises between floating gate and control gate because including not only gate-oxide capacitances in measurement process
Capacitor, the capacitor between floating gate and control gate will affect the measurement of gate-oxide capacitances-current curve, make to the measurement
At interference.
Therefore it needs to be improved further the detection structure and detection method of the current device, on eliminating
State problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, a kind of test structure of semiconductor devices is provided, comprising:
Semiconductor substrate；
Floating gate is located in the semiconductor substrate；
Floating gate oxide, between the semiconductor substrate and the floating gate；
Control gate is located on the floating gate；
First terminal is connect with the semiconductor substrate；
Second terminal is electrically connected with the control gate；
Third terminal is electrically connected with the floating gate of exposing.
Optionally, the first terminal and there is self-aligned silicide between connecting with the semiconductor substrate；
There is self-aligned silicide between the second terminal and the control gate；
There is self-aligned silicide between the third terminal and the floating gate of exposing.
Optionally, the control gate is located at one end of the floating gate.
Optionally, the side wall of the floating gate and the control gate has been respectively formed on side wall insulating protective layer.
The present invention also provides a kind of test methods based on above-mentioned test structure, comprising:
Step S1: being electrically connected the second terminal and the third terminal, and applies electricity on the third terminal
Pressure, to obtain voltage-current curve and calculate resistance, according to the resistance judge the floating gate and control gate it
Between whether there is boundary layer.
Optionally, in the step S1, if the voltage-current curve calculates the resulting resistance and is presented as
Floating gate material, the normal resistance values for controlling grid material, then be not present boundary layer between the floating gate and the control gate；
If the voltage-current curve calculates the resulting resistance greater than floating gate material, the electricity of control grid material
Standard resistance range, then there are boundary layers between the floating gate and the control gate.
Optionally, in the step S1, if the voltage-current curve calculates resulting resistance and is greater than floating gate material
The resistance value range of material, control grid material,
Then further execute step S2: then scanning-V~+V voltage on the floating gate, voltage is on the control gate
0, to obtain capacitance-voltage curve, further confirm that there are boundary layers between the floating gate and the control gate.
Optionally, the method still further comprises step S3: it is electrically connected the first terminal and third terminal, into
Row scanning is to obtain capacitor-potential curve, to test the thickness of the floating gate oxide.
Optionally, if boundary layer is not present between the floating gate and the control gate, it is electrically connected described second eventually
End and third terminal, are scanned to obtain capacitor-potential curve, to test the thickness of the gate oxide.
The present invention also provides a kind of semiconductor devices, comprising:
Core cell area is formed with core memory area in the core cell area；
Surrounding cells area, including above-mentioned test structure and cmos device.
The present invention also provides a kind of preparation methods of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, the semiconductor substrate includes core cell area and surrounding cells area, described
It is formed with core space floating gate and core space boundary layer in core cell area, is formed with peripheral region floating gate in the surrounding cells area
With peripheral region boundary layer；
Step S2: above the core cell area and the top of surrounding cells area one end forms first and covers
Layer, then removes the part boundary layer on the peripheral region floating gate；
Step S3: depositional control gate material layer and barrier layer in the core cell area and the surrounding cells area；
Step S4: the control gate material layer and core space floating gate in the core cell area are patterned, to form core
Area's gate structure；
Step S5: patterning the control gate material layer in the surrounding cells area, with expose the remaining boundary layer and
Peripheral region control gate is formed on the peripheral region floating gate；
Step S6: through-hole is formed between the core space gate structure, and is formed on the peripheral region floating gate floating gate
First terminal forms second terminal on the peripheral region control gate, is formed in the semiconductor substrate of the peripheral region
Third terminal.
Optionally, in the step S3, SiN layer is further formed in the control gate material layer.
Optionally, the step S4 includes:
Step S41: the first mask layer is formed in the core cell area, using first mask layer as exposure mask, etches institute
Control gate material layer and the core space floating gate are stated, to form core space gate structure；
Step S42: LDD ion implanting is executed in the semiconductor substrate of core space gate structure two sides；
Step S43: forming side wall insulating protective layer on the side wall of the core space gate structure, and executes source and drain note
Enter.
Optionally, the step S4 may further comprise:
Step S44: the first interlayer dielectric layer of deposition, to cover the core cell area and the surrounding cells area；
Step S45: planarization first interlayer dielectric layer to the core space gate structure；
Step S46: protective layer is formed in the core cell area and the surrounding cells area；
Step S47: second is formed in the core cell area and covers floor, removes the guarantor in the surrounding cells area
Sheath, wherein the protective layer in the surrounding cells area is removed using wet etching.
Optionally, the step S5 includes:
Step S51: the second mask layer is formed in the core cell area and the surrounding cells area, and is patterned；
Step S52: using patterned second mask layer as the control grid material in surrounding cells area described in mask etch
Layer, to expose the boundary layer on peripheral region floating gate one end, while forming week in the other end of the peripheral region floating gate
Enclose area's control gate.
Optionally, the step S5 may further comprise:
Step S53: LDD ion implanting is executed in the surrounding cells area；
Step S54: the first dielectric layer of deposition and the second dielectric layer, and dry etching is carried out, in the surrounding cells area
Floating gate and the side wall of control gate be respectively formed on side wall insulating protective layer；
Step S55: N-type ion injection is executed in the one end in the surrounding cells area, the one of the another surrounding cells area
Hold P-type ion injection.
Optionally, the step S5 may further comprise:
Step S56: insulation barrier is formed in the core cell area and the surrounding cells area；
Step S57: third is formed in the core cell area and covers floor, described in removing in the surrounding cells area
Insulation barrier；
Step S58: on the peripheral region floating gate of exposing, on the peripheral region control gate and described in the peripheral region
Self-aligned metal silicate layer is formed in semiconductor substrate.
Optionally, the step S6 includes:
Step S61: the second interlayer dielectric layer and third layer are formed in the core cell area and the surrounding cells area
Between dielectric layer, to cover the core cell area and the surrounding cells area；
Step S62: the 4th is formed in the surrounding cells area and covers floor, described in removing in the core cell area
Third interlayer dielectric layer；
Step S63: planarization second interlayer dielectric layer to the core space gate structure；
Step S64: patterning the first interlayer dielectric layer in the core cell area, in first interlayer dielectric layer
In the core space gate structure between form via openings；
Step S65: patterning second interlayer dielectric layer in the surrounding cells area, to form end openings, point
Do not expose the semiconductor substrate in the peripheral region floating gate, the peripheral region control gate and the surrounding cells area；
Step S66: deposition conductive material forms through-hole, while filling the terminal and opening to fill the via openings
Mouthful, with the semiconductor substrate respectively in the peripheral region floating gate, the peripheral region control gate and the surrounding cells area
It is upper to form the first terminal, the second terminal and the third terminal.
Optionally, the step S6 may further comprise:
Step S67: the 4th interlayer dielectric layer is formed in the core cell area and the surrounding cells area；
Step S68: forming contact hole in the 4th interlayer dielectric layer, to be electrically connected the through-hole, described
One terminal, the second terminal and the third terminal.
In order to solve the problems in the existing technology the present invention provides a kind of test structure of semiconductor devices, described
Test structure can not only be detected with the presence or absence of boundary layer between the floating gate and control gate of peripheral region device, if while the interface
The thickness of floating gate oxide can also be further detected in the presence of layer.
The advantages of test structures and methods of the present invention, is:
(1) it can be tested by online WAT to monitor the boundary layer between the floating gate of peripheral region device and control gate.
(2) when there are boundary layer, conventional detection structure meetings between the floating gate and control gate of the peripheral region device
By the interference of interlayer dielectric layer, but detection structure of the present invention can be with accurate detection to the electricity of floating gate oxide
Appearance-current curve, and feed back and obtain the thickness of accurate gate oxide.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, device used to explain the present invention and principle.In the accompanying drawings,
Fig. 1-30 is the preparation process schematic diagram of semiconductor devices described in an embodiment of the present invention；
Figure 31 is the schematic diagram of the detection structure of semiconductor devices described in the prior art；
Figure 32 is the preparation technology flow chart of semiconductor devices described in an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
The WAT test structure of peripheral region gate oxide is as shown in figure 31 in the prior art, and the test structure includes half
Conductor substrate 10, floating gate 11, control gate 12, first terminal 13 and second terminal 14, wherein the floating gate 11 is located at described half
On conductor substrate, it is also formed with gate oxide level between the semiconductor substrate and the floating gate 11, wherein the control gate
Positioned at the top of the floating gate, the first terminal is connected with the control gate, and the second terminal and the semiconductor serve as a contrast
Bottom is connected.
In measurement, apply voltage on the first terminal 13 and the second terminal, if the floating gate 11 and institute
Stating does not have boundary layer between control gate, then structure as shown in figure 31 can be accurately obtained grid by capacitor-current curve
The thickness of oxide, but once there is between the floating gate and the control gate boundary layer, the capacitor measured includes grid
Pole capacitive oxide and interface layer capacitance, the interface layer capacitance will result directly in the inaccuracy of the gate oxide thicknesses,
Therefore it needs to be improved further the current measurement structure and measurement method, to eliminate the above problem.
Embodiment 1
In order to solve the problems in the existing technology, a kind of detection structure of semiconductor devices, the detection are provided
Structure is as shown in figure 30, the test structure of the semiconductor devices, comprising:
Semiconductor substrate 101；
Floating gate 102 is located in the semiconductor substrate；
Floating gate oxide, between the semiconductor substrate and the floating gate；
Control gate 104 is located on the floating gate, and floating gate described in exposed portion；
First terminal 1121 is connect with the semiconductor substrate；
Second terminal 1122 is electrically connected with the control gate；
Third terminal 1123 is electrically connected with the floating gate of exposing；
Wherein, the semiconductor substrate 101 can be following at least one of the material being previously mentioned: on silicon, insulator
Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..
In addition, active area, shallow channel isolation area and peripheral region can be defined in semiconductor substrate 101.For convenience,
There is no indicate in shown figure.
The floating gate 102 can select semiconductor material commonly used in the art, such as can select polysilicon, but not
It is confined to the material.
Further, the control gate 103 can select identical material with the floating gate, such as can select polysilicon.
Optionally, also there is self-aligned silicide, such as metal silicide between the third terminal and the floating gate；
Also there is self-aligned silicide between the second terminal and the control gate；
Also there is self-aligned silicide between the first terminal and the semiconductor substrate.
Wherein, the control gate is located at one end of the floating gate, but is not limited to the position, can according to need progress
Setting.
Optionally, the side wall of the floating gate and the control gate has been respectively formed on clearance wall.
Detection structure of the present invention is additionally provided on the floating gate compared with detection structure in the prior art
With third terminal, the test structure can be realized simultaneously following two functions when being tested:
First is able to detect between floating gate and control gate with the presence or absence of boundary layer, step S1: is electrically connected described second
Terminal and the third terminal, and apply voltage on the third terminal, to obtain voltage-current curve and calculate resistance
Resistance value judges whether there may be boundary layers between the floating gate and control gate according to resistance value.
In the step S1, it is analyzed according to the voltage-current curve, if the voltage-current curve embodies
For the normal resistance values of floating gate material, control grid material, then boundary layer is not present between the floating gate and the control gate.
It is described if the resistance value that the resistance value that the voltage-current curve embodies is greater than floating gate material, controls grid material
There are boundary layers between floating gate and the control gate.
Further, in the step S1, if institute's voltage-current curve calculates resulting resistance and is greater than floating gate material
The normal range (NR) of the resistance value of material, control grid material, in order to further prove that there are boundaries between the floating gate and the control gate
Surface layer, then scanning-V~+V voltage on the floating gate, voltage is 0 on the control gate, to obtain capacitor-current curve,
Further confirm that there are boundary layers between the floating gate and the control gate.
Optionally, if there are boundary layers between floating gate and the control gate, the first terminal and are electrically connected
Three terminals are scanned to obtain capacitor-potential curve, to test the thickness of the floating gate oxide, due to the third
There is no boundary layer above the floating gate of terminal connection, therefore, interface layer capacitance is not present in measurement process, it will not be to described
The measurement of gate-oxide capacitances interferes, and can be accurately obtained the thickness of gate oxide.
In addition, described the can also be electrically connected when boundary layer is not present between the floating gate and the control gate
Two terminals and third terminal are scanned to obtain capacitor-potential curve, to test the thickness of the gate oxide, at this time
There will not be interface layer capacitance, measurement result will not be impacted.
The advantages of test structures and methods of the present invention, is:
(1) it can be tested by online WAT to monitor the boundary layer between the floating gate of peripheral region device and control gate.
(2) when there are boundary layer, conventional detection structure meetings between the floating gate and control gate of the peripheral region device
By the interference of interlayer dielectric layer, but detection structure of the present invention can be with the capacitor-of accurate detection to gate oxide
Current curve, and feed back and obtain the thickness of accurate gate oxide.
Embodiment 2
1-30 is illustrated a kind of specific embodiment of the invention with reference to the accompanying drawing.
Firstly, executing step 201, semiconductor substrate 101 is provided, is formed with core list in the semiconductor substrate 101
First area's (left side figure in Fig. 1), surrounding cells area (Periphery) (right figure in Fig. 1), wherein in the surrounding cells area
It is also formed with shallow trench isolation.
Specifically, firstly, referring to Fig.1, wherein the semiconductor substrate 101 can be in the following material being previously mentioned extremely
Few one kind: silicon, silicon-on-insulator (SOI), be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI),
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Step 202 is executed, forms 102 ˊ of core space floating gate and 103 ˊ of core space boundary layer in the core cell area,
Peripheral region floating gate 102 and peripheral region boundary layer 103 are formed in the surrounding cells area.
Specifically, as shown in Figure 1, forming gate dielectric in the semiconductor substrate 101, wherein the grid is situated between
Electric layer can select dielectric material commonly used in the art, such as can select oxide.
Schematically illustrate the forming method below: when selecting oxide as the gate dielectric, the grid
The forming method of dielectric layer can be high-temperature oxydation or deposition method, it is not limited to which a certain method can according to need
It is selected.
Floating gate material layer, boundary layer (spacer material layer) are sequentially formed on the gate dielectric, and described in patterning
Floating gate material layer, the spacer material layer, to form floating gate.
In this embodiment, the floating gate material layer of polysilicon is formed, the polysilicon selects epitaxy method to be formed.
Further, spacer material layer is formed on the floating gate material layer, the spacer material layer can select this field
Common insulating materials, such as ONO (the structural insulation separation layer of oxidenitride oxide), but be not limited to that institute
State material.
The floating gate material layer, spacer material layer are patterned, to form core space floating gate 102 in the core cell area
103 ˊ of ˊ and core space boundary layer forms peripheral region floating gate 102 and peripheral region boundary layer 103 in the surrounding cells area.
Step 203 is executed, above the core cell area and the top of surrounding cells area one end forms first
Layer is covered, to remove the part boundary layer on the peripheral region floating gate.
Specifically, as shown in Fig. 2, in this step in the core cell area, surrounding cells area one end it is upper
Institute that is rectangular to cover layer, such as patterned photoresist layer at first, then being exposed using the first cover layer as mask etch
Boundary layer is stated, to remove the part boundary layer on the peripheral region floating gate, peripheral region floating gate described in exposed portion.
Execute step 204,104 He of depositional control gate material layer in the core cell area and the surrounding cells area
SiN layer.
Specifically, as shown in figure 3, depositional control gate material layer 104 and SiN layer in this step, described to be covered each by
Core cell area and the surrounding cells area.
Wherein, the control gate material layer 104 selects polysilicon, but be not limited to that the material, can also select this
The common other materials in field.
Step 205 is executed, the control gate material layer in the core cell area is patterned, to form core space grid knot
Structure.
Specifically, as shown in figure 4, forming the first mask layer in the core cell area in the step, while in the week
It encloses to be formed on cellular zone and covers floor to protect the surrounding cells area, then using first mask layer as exposure mask, described in etching
Gate material layer and the core space floating gate are controlled, to form core space gate structure, wherein the core space gate structure is mutual
Interval, as shown in Figure 4.
Step 206 is executed, LDD ion note is executed in the semiconductor substrate of core space gate structure two sides
Enter.
Specifically, it as shown in figure 5, removing the first mask layer above the core cell area in this step, then holds
Row LDD ion implanting, the type and dosage injected in the ion implanting step can be configured according to specific needs.
Step 207 is executed, forms side wall insulating protective layer on the side wall of the core space gate structure, and execute source and drain
Injection.
Specifically, as shown in fig. 6, in this step, depositing the first dielectric layer and the second dielectric layer, and carry out dry method erosion
It carves, the side wall of floating gate and control gate in the surrounding cells area is respectively formed on side wall insulating protective layer.
Then source and drain injection is executed, to form source electrode and drain electrode in the LDD doped region, as shown in fig. 7, wherein source and drain
Injection can select method commonly used in the art, and details are not described herein.
The method further comprises the step of forming clearance wall on the side wall insulating protective layer, as shown in Figure 8.
Step 208 is executed, the first interlayer dielectric layer 106 is deposited, to cover the core cell area and the surrounding cells
Area.
Specifically, as shown in figure 9, removing the cover floor in the surrounding cells area, the first interlayer Jie is then deposited
Electric layer 106, to cover the core cell area and the surrounding cells area.
Wherein, first interlayer dielectric layer 106 can select dielectric material commonly used in the art, such as can select oxygen
Compound or HARP etc..
The deposition method of first interlayer dielectric layer 106 can be FCVD or HARP.
Step 209 is executed, planarizes first interlayer dielectric layer 106 to the core space gate structure.
Specifically, as shown in Figure 10, flattening method commonly used in the art, such as chemical machine can be selected in this step
Tool planarization etc. planarizes first interlayer dielectric layer to the top of the core space gate structure.
Step 210 is executed, forms protective layer 107 in the core cell area and the surrounding cells area.
Specifically, as shown in figure 11, protective layer 107 is deposited, in this step to cover the core cell area and described
Surrounding cells area.
Wherein, the protective layer 107 can select plasma enhanced oxidation object (PEOX), and thickness is not limited to certain
One numberical range.
Step 211 is executed, second is formed in the core cell area and covers floor, remove the institute in the surrounding cells area
State protective layer 107.
Specifically, as shown in figure 12, second is formed in the core cell area in this step and cover floor, such as in institute
It states and forms photoresist layer in core cell area and the surrounding cells area, then expose, develop, to open the surrounding cells
The protective layer 107 in the surrounding cells area is exposed in area, removed in the surrounding cells area using wet etching described in
Protective layer 107, since the protective layer 107 in core cell area and 105 material of the protective layer in surrounding cells area are entirely different,
The acid used in etching can only get rid of protective layer 105, and the protective layer 107 in core cell area still retains.
Then dry etching is selected to remove the protective layer 107, to expose the SiN layer in the surrounding cells area.
Then the SiN layer is removed, to expose the control gate material layer in the surrounding cells area, such as Figure 13 institute
Show.
Step 212 is executed, forms the second mask layer, and pattern in the core cell area and the surrounding cells area
Change, then using patterned second mask layer as the control gate material layer in surrounding cells area described in mask etch, with
Expose the boundary layer on peripheral region floating gate one end, while being formed around described in the other end of the peripheral region floating gate
Area's control gate, as shown in figure 14.
Step 213 is executed, executes LDD ion implanting in the surrounding cells area.
Specifically, as shown in figure 15, it is initially formed LDD ion implanting light shield, then executes ion implanting, it is no longer superfluous herein
It states.
Step 214 is executed, side wall insulation is formed on the side wall of the peripheral region floating gate and the peripheral region control gate and protects
Sheath simultaneously removes the remaining boundary layer, to expose the peripheral region floating gate.
Specifically, as shown in figure 16, it is formed on the side wall of the peripheral region floating gate and the peripheral region control gate first
Side wall insulating protective layer, the forming method can be selected method commonly used in the art, repeat no more.
Then the remaining boundary layer in peripheral region floating gate one end is removed, it is optional to expose the peripheral region floating gate
Ground, is selected and there is the peripheral region floating gate 102 method of larger etching selectivity to remove the boundary layer.
Step 215 is executed, N-type ion injection is executed in the one end in the surrounding cells area, in the another surrounding cells area
One end P-type ion injection, as shown in FIG. 17 and 18, specific method for implanting repeats no more.
Step 216 is executed, forms insulation barrier 108 in the core cell area and the surrounding cells area.
Specifically, as shown in figure 19, the deposition method can select method commonly used in the art, it is not limited to a certain
Kind.
Step 217 is executed, third is formed in the core cell area and covers floor, to remove in the surrounding cells area
The insulation barrier 108.
Specifically, as shown in figure 20, in this step, select described in the removal of the method for dry etching and/or wet etching
The insulation barrier in surrounding cells area.
Step 218 is executed, on the peripheral region floating gate of exposing, on the peripheral region control gate and peripheral region
Self-aligned metal silicate layer 109 is formed in the semiconductor substrate.
Specifically, as shown in figure 21, deposited metal Ni first, then executes rapid thermal annealing, makes metallic nickel and the week
It encloses area's source and drain, peripheral region floating gate, peripheral region control gate to react, then removes the peripheral region source and drain, peripheral region floating gate, week
The metallic nickel gone on region other than area's control gate is enclosed, executes rapid thermal annealing again.
Step 219 is executed, forms 110 He of the second interlayer dielectric layer in the core cell area and the surrounding cells area
Third interlayer dielectric layer 111, to cover the core cell area and the surrounding cells area.
Specifically, as shown in figure 22, second interlayer dielectric layer 110 and third interlayer dielectric layer 111 can be selected often
Dielectric material, such as HSRP, TEPS etc..
Step 220 is executed, the 4th is formed in the surrounding cells area and covers floor, to remove in the core cell area
The third interlayer dielectric layer.
Specifically, as shown in figure 23, dry etching is selected to remove described the in the core cell area in this step
Three interlayer dielectric layers.
Step 221 is executed, planarizes the third interlayer dielectric layer to the core space gate structure
Specifically, as shown in figure 24, the flattening method of the routine such as chemical-mechanical planarization can be selected.
Step 222 is executed, the first interlayer dielectric layer in the core cell area is patterned, to be situated between in first interlayer
Via openings are formed between core space gate structure described in electric layer.
Specifically, as shown in figure 25, in this step, it is initially formed mask layer, such as photoresist layer, then patterns institute
Photoresist layer is stated, to expose the region between the core space gate structure, then etching removes the core space gate structure
Between the first dielectric layer, to form via openings.
Optionally, in this step, BOE wet etching can be selected to form the via openings, repeated no more.
Step 223 is executed, second interlayer dielectric layer in the surrounding cells area is patterned, is opened with forming terminal
Mouthful, expose the semiconductor substrate in the peripheral region floating gate, the peripheral region control gate and the surrounding cells area respectively.
Specifically, as shown in figure 26, in this step, it is initially formed mask layer, such as photoresist layer, then patterns institute
Photoresist layer is stated, opening is formed, to expose the peripheral region floating gate, peripheral region control gate and peripheral region source and drain, then with described
Photoresist layer is that mask etch removes the second interlayer dielectric layer, to form end openings.
Optionally, in this step, dry etching can be selected to form the end openings, repeated no more.
Step 224 is executed, conductive material is deposited, to fill the via openings respectively, forms through-hole, while described in filling
End openings are partly led with described in the peripheral region floating gate, the peripheral region control gate and the surrounding cells area respectively
The third terminal 1123, the second terminal 1122 and the first terminal 1121 are formed in body substrate, as shown in figure 27.
Step 225 is executed, the 4th interlayer dielectric layer is formed in the core cell area and the surrounding cells area, such as schemes
Shown in 28.
Step 225 is executed, patterns and forms contact hole opening in the 4th interlayer dielectric layer, it is described logical to expose respectively
Hole, the first terminal, the second terminal and the third terminal, as shown in figure 29.
Step 226 is executed, conductive material is deposited, to fill contact hole opening, is electrically connected the through-hole, described
First terminal, the second terminal and the third terminal, as shown in figure 30.
So far, the introduction of the preparation process of the semiconductor storage unit of the embodiment of the present invention is completed.Above-mentioned steps it
It afterwards, can also include other correlation steps, details are not described herein again.Also, in addition to the foregoing steps, the preparation side of the present embodiment
Method can also include other steps among above-mentioned each step or between different steps, these steps can be by existing
Various techniques in technology realize that details are not described herein again.
In order to solve the problems in the existing technology the present invention provides a kind of test structure of semiconductor devices, described
Test structure can not only be detected with the presence or absence of boundary layer between the floating gate and control gate of peripheral region device, if while the interface
The thickness of floating gate oxide can also be further detected in the presence of layer.
The advantages of test structures and methods of the present invention, is:
(1) it can be tested by online WAT to monitor the boundary layer between the floating gate of peripheral region device and control gate.
(2) when there are boundary layer, conventional detection structure meetings between the floating gate and control gate of the peripheral region device
By the interference of interlayer dielectric layer, but detection structure of the present invention can be with accurate detection to the electricity of floating gate oxide
Appearance-current curve, and feed back and obtain the thickness of accurate gate oxide.
Wherein, Figure 32 be the embodiment of the invention in semiconductor devices process flow chart, specifically include with
Lower step:
Step S1: semiconductor substrate is provided, the semiconductor substrate includes core cell area and surrounding cells area, described
It is formed with core space floating gate and core space boundary layer in core cell area, is formed with peripheral region floating gate in the surrounding cells area
With peripheral region boundary layer；
Step S2: above the core cell area and the top of surrounding cells area one end forms first and covers
Layer, then removes the part boundary layer on the peripheral region floating gate；
Step S3: the depositional control gate material layer in the core cell area and the surrounding cells area；
Step S4: the control gate material layer and core space floating gate in the core cell area are patterned, to form core
Area's gate structure；
Step S5: patterning the control gate material layer in the surrounding cells area, with expose the remaining boundary layer and
Peripheral region control gate is formed on the peripheral region floating gate；
Step S6: through-hole is formed between the core space gate structure, and is formed on the peripheral region floating gate floating gate
First terminal forms second terminal on the peripheral region control gate, is formed in the semiconductor substrate of the peripheral region
Third terminal.
Embodiment 3
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes the semiconductor detection in embodiment 1
Mechanism, or prepared by method as described in example 2.Semiconductor devices of the present invention can by online WAT test come
Monitor the boundary layer between the floating gate and control gate of peripheral region device.
Embodiment 4
The present invention also provides a kind of electronic devices, including semiconductor devices described in embodiment 3.Wherein, semiconductor device
Part is semiconductor devices described in embodiment 3, or the semiconductor devices obtained according to preparation method as described in example 2.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.The electronic device of the embodiment of the present invention above-mentioned is partly led due to having used
Body device, thus there is better performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (19)
1. a kind of test structure of semiconductor devices is located at surrounding cells area characterized by comprising
Semiconductor substrate；
Floating gate is located in the semiconductor substrate；
Floating gate oxide, between the semiconductor substrate and the floating gate；
Control gate directly connects on the floating gate and with the floating gate, and floating gate described in exposed portion；
First terminal is electrically connected with the semiconductor substrate；
Second terminal is electrically connected with the control gate；
Third terminal is electrically connected with the floating gate of exposing.
2. test structure according to claim 1, which is characterized in that between the first terminal and the semiconductor substrate
With self-aligned silicide；
There is self-aligned silicide between the second terminal and the control gate；
There is self-aligned silicide between the third terminal and the floating gate of exposing.
3. test structure according to claim 1, which is characterized in that the control gate is located at one end of the floating gate.
4. test structure according to claim 1, which is characterized in that equal shape on the side wall of the floating gate and the control gate
At there is side wall insulating protective layer.
5. a kind of test method based on test structure described in one of Claims 1-4, comprising:
Step S1: being electrically connected the second terminal and the third terminal, and apply voltage on the third terminal, with
Obtain voltage-current curve and calculate resistance, judged according to the resistance be between the floating gate and control gate
It is no that there are boundary layers.
6. according to the method described in claim 5, it is characterized in that, in the step S1, if the voltage-current curve meter
Calculate the normal resistance values that the resulting resistance is presented as floating gate material, controls grid material, the then floating gate and the control
Boundary layer is not present between grid processed；
If the voltage-current curve calculates resistance value of the resulting resistance greater than floating gate material, control grid material
Range, then there are boundary layers between the floating gate and the control gate.
7. according to the method described in claim 6, it is characterized in that, in the step S1, if the voltage-current curve meter
Resistance value range of the resulting resistance greater than floating gate material, control grid material is calculated,
Then further execute step S2: then scanning-V~+V voltage on the floating gate, voltage is 0 on the control gate, with
Capacitor-potential curve is obtained, further confirms that there are boundary layers between the floating gate and the control gate.
8. the method according to one of claim 5 to 7, which is characterized in that the method still further comprises step S3: point
It is not electrically connected the first terminal and third terminal, is scanned to obtain capacitor-potential curve, to test the floating gate oxygen
The thickness of compound.
9. according to the method described in claim 5, it is characterized in that, if interface is not present between the floating gate and the control gate
Layer, then be electrically connected the second terminal and first terminal, is scanned to obtain capacitor-potential curve, described to test
The thickness of floating gate oxide.
10. a kind of semiconductor devices, comprising:
Core cell area is formed with core memory area in the core cell area；
Surrounding cells area, including test structure and cmos device described in one of Claims 1-4.
11. a kind of preparation method of semiconductor devices, comprising:
Step S1: semiconductor substrate is provided, the semiconductor substrate includes core cell area and surrounding cells area, in the core
It is formed with core space floating gate and core space boundary layer on cellular zone, is formed with peripheral region floating gate and week in the surrounding cells area
Enclose regional boundary surface layer；
Step S2: above the core cell area and the top of surrounding cells area one end forms first and covers floor, so
The part boundary layer on the peripheral region floating gate is removed afterwards；
Step S3: depositional control gate material layer and barrier layer in the core cell area and the surrounding cells area；
Step S4: the control gate material layer and core space floating gate in the core cell area are patterned, to form core space grid
Pole structure；
Step S5: patterning the control gate material layer in the surrounding cells area, to expose the remaining boundary layer and described
Peripheral region control gate is formed on peripheral region floating gate；
Step S6: forming through-hole between the core space gate structure, and form first terminal on the peripheral region floating gate,
Second terminal is formed on the peripheral region control gate, forms third terminal in the semiconductor substrate of the peripheral region.
12. according to the method for claim 11, which is characterized in that in the step S3, SiN is selected on the barrier layer.
13. according to the method for claim 11, which is characterized in that the step S4 includes:
Step S41: the first mask layer is formed in the core cell area and etches the control using first mask layer as exposure mask
Gate material layer processed and the core space floating gate, to form core space gate structure；
Step S42: LDD ion implanting is executed in the semiconductor substrate of core space gate structure two sides；
Step S43: forming side wall insulating protective layer on the side wall of the core space gate structure, and executes source and drain injection.
14. according to the method for claim 13, which is characterized in that the step S4 may further comprise:
Step S44: the first interlayer dielectric layer of deposition, to cover the core cell area and the surrounding cells area；
Step S45: planarization first interlayer dielectric layer to the core space gate structure；
Step S46: protective layer is formed in the core cell area and the surrounding cells area；
Step S47: second is formed in the core cell area and covers floor, removes the protection in the surrounding cells area
Layer, wherein the protective layer in the surrounding cells area is removed using wet etching.
15. according to the method for claim 11, which is characterized in that the step S5 includes:
Step S51: the second mask layer is formed in the core cell area and the surrounding cells area, and is patterned；
Step S52: using patterned second mask layer as the control gate material layer in surrounding cells area described in mask etch, with
Expose the boundary layer on peripheral region floating gate one end, while forming peripheral region control in the other end of the peripheral region floating gate
Grid processed.
16. according to the method for claim 15, which is characterized in that the step S5 may further comprise:
Step S53: LDD ion implanting is executed in the surrounding cells area；
Step S54: the first dielectric layer of deposition and the second dielectric layer, and dry etching is carried out, it is floating in the surrounding cells area
The side wall of grid and control gate is respectively formed on side wall insulating protective layer；
Step S55: N-type ion injection is executed in the one end in the surrounding cells area, the other end in the surrounding cells area is held
The injection of row P-type ion.
17. according to the method for claim 16, which is characterized in that the step S5 may further comprise:
Step S56: insulation barrier is formed in the core cell area and the surrounding cells area；
Step S57: third is formed in the core cell area and covers floor, to remove the insulation in the surrounding cells area
Barrier layer；
Step S58: it is partly led on the peripheral region floating gate of exposing, on the peripheral region control gate with the described of the peripheral region
Self-aligned metal silicate layer is formed in body substrate.
18. according to the method for claim 11, which is characterized in that the step S6 includes:
Step S61: forming the second interlayer dielectric layer in the core cell area and the surrounding cells area and third interlayer is situated between
Electric layer, to cover the core cell area and the surrounding cells area；
Step S62: the 4th is formed in the surrounding cells area and covers floor, to remove the third in the core cell area
Interlayer dielectric layer；
Step S63: planarization second interlayer dielectric layer to the core space gate structure；
Step S64: patterning the first interlayer dielectric layer in the core cell area, in first interlayer dielectric layer
Via openings are formed between the core space gate structure；
Step S65: second interlayer dielectric layer patterned in the surrounding cells area is revealed respectively with forming end openings
The semiconductor substrate in the peripheral region floating gate, the peripheral region control gate and the surrounding cells area out；
Step S66: deposition conductive material forms through-hole, while filling the end openings to fill the via openings, with
It is formed in the semiconductor substrate in the peripheral region floating gate, the peripheral region control gate and the surrounding cells area respectively
The first terminal, the second terminal and the third terminal.
19. according to the method for claim 18, which is characterized in that the step S6 may further comprise:
Step S67: the 4th interlayer dielectric layer is formed in the core cell area and the surrounding cells area；
Step S68: forming contact hole in the 4th interlayer dielectric layer, to be electrically connected the through-hole, described first eventually
End, the second terminal and the third terminal.
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| CN108831842B (en) * | 2018-06-08 | 2020-06-16 | 上海华虹宏力半导体制造有限公司 | Method for detecting alignment shift |
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| CN112420719A (en) * | 2020-11-25 | 2021-02-26 | 华虹半导体(无锡)有限公司 | Testkey structure of flash memory device and manufacturing method thereof |
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| US6002609A (en) * | 1997-07-09 | 1999-12-14 | Kabushiki Kaisha Toshiba | Semiconductor device having a security circuit for preventing illegal access |
| CN101127329A (en) * | 2006-08-17 | 2008-02-20 | 海力士半导体有限公司 | Flash memory device and a method of fabricating the same |
| CN101894752A (en) * | 2009-05-19 | 2010-11-24 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor manufacture method |
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|---|---|---|---|---|
| US6002609A (en) * | 1997-07-09 | 1999-12-14 | Kabushiki Kaisha Toshiba | Semiconductor device having a security circuit for preventing illegal access |
| CN101127329A (en) * | 2006-08-17 | 2008-02-20 | 海力士半导体有限公司 | Flash memory device and a method of fabricating the same |
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