CN106469732A - Three-dimensional storage - Google Patents
Three-dimensional storage Download PDFInfo
- Publication number
- CN106469732A CN106469732A CN201510506194.7A CN201510506194A CN106469732A CN 106469732 A CN106469732 A CN 106469732A CN 201510506194 A CN201510506194 A CN 201510506194A CN 106469732 A CN106469732 A CN 106469732A
- Authority
- CN
- China
- Prior art keywords
- layer
- wordline
- active layer
- memory element
- electric charge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of three-dimensional storage, there is memory element laminated construction.Memory element laminated construction, is formed with multiple insulating barrier cross laminates by multiple memory cell array structures, each memory cell array structure has wordline, active layer, composite bed and source/drain regions.Wordline, active layer and composite bed extend in the Y direction.Active layer is arranged between adjacent wordline.Composite bed is arranged between adjacent wordline and active layer, and each composite bed sequentially includes the first dielectric layer, electric charge storage layer and the second dielectric layer by active layer.Source/drain regions, are arranged in active layer at equal intervals.Adjacent two described source/drain regions, the active layer between two source/drain regions and the first dielectric layer on active layer, electric charge storage layer, the second dielectric layer and wordline, collectively form memory element.
Description
Technical field
The invention relates to a kind of semiconductor element, and in particular to a kind of three-dimensional storage.
Background technology
More and more high with the requirement to storage subsystem for the consumer products, read or write speed to product or
The standard of capacity is also more and more high, and therefore high capacity dependent merchandise has become as the main flow of industry.Have
In consideration of it, also must be in response to this demand in terms of the exploitation of memorizer.
However, current flat memory (particularly nor gate formula (NOR) memorizer) be limited to integrated
In circuit (integrated circuits), the critical size of element, faces storage memory cells micro bottleneck.
So designer seeks there is multilevel three-dimensional storage (particularly NOR memorizer), with
Reach larger storage volume and the technology of relatively low cost of bit.
Content of the invention
The present invention provides a kind of three-dimensional storage, and it can be with the integrated level of lift elements.
A kind of three-dimensional storage of the present invention, has memory element laminated construction.Wherein, memory element
Laminated construction, is formed with multiple insulating barrier cross laminates by multiple memory cell array structures, each storage
Cell array structure has multiple wordline, multiple active layer, multiple composite bed and multiple source/drain pole region.
Multiple wordline, extend in the Y direction.Multiple active layers, extend in the Y direction, and active layer is arranged at
Between adjacent wordline.Multiple composite beds, extend in the Y direction, be arranged at adjacent wordline with active
Between layer, each composite bed sequentially includes the first dielectric layer, electric charge storage layer and second Jie by active layer
Electric layer.And multiple source/drain pole region, it is arranged at equal intervals in active layer, wherein adjacent two sources
Pole/drain region, the active layer between two source/drain regions and first Jie on active layer
Electric layer, electric charge storage layer, the second dielectric layer and wordline, collectively form memory element.
In one embodiment of this invention, above-mentioned three-dimensional storage further includes multiple conductor pins, in Z
Direction extends, and is electrically connected with the described source/drain regions in described memory element laminated construction.
In one embodiment of this invention, above-mentioned three-dimensional storage further includes multiple bit lines, in X side
To extension, bit line is electrically connected at the conductor pin of X-direction.
In one embodiment of this invention, the material of above-mentioned bit line include polysilicon, DOPOS doped polycrystalline silicon,
Metal silicide or metal.
In one embodiment of this invention, the material of above-mentioned electric charge storage layer includes silicon nitride.
In one embodiment of this invention, the material of above-mentioned electric charge storage layer includes polysilicon or doping
Polysilicon, and further include multiple sealing coats, it is arranged in electric charge storage layer, to isolate adjacent depositing
The electric charge storage layer of storage unit.
In one embodiment of this invention, the material of above-mentioned sealing coat includes silicon oxide.
In one embodiment of this invention, above-mentioned wordline and the material of active layer include polysilicon respectively
Or DOPOS doped polycrystalline silicon.
In one embodiment of this invention, the admixture of the admixture of above-mentioned active layer and source/drain regions is not
With.
In one embodiment of this invention, above-mentioned source/drain regions and the material of conductor pin include polycrystalline
Silicon, DOPOS doped polycrystalline silicon, germanide, metal silicide or metal.
In one embodiment of this invention, the admixture of the admixture of above-mentioned active layer and source/drain regions is not
With.
In one embodiment of this invention, the first above-mentioned dielectric layer, the second dielectric layer and insulating barrier
Material includes silicon oxide respectively.
In one embodiment of this invention, in each memory cell array structure, in the X direction, phase
Two adjacent memory element shared word line or shared active layer and source/drain regions.
In one embodiment of this invention, in each memory cell array structure, in the Y direction, many
Individual memory element series connection connects and shared word line.
Based on above-mentioned, in the three-dimensional storage of the present invention, two adjacent memory element shared word line or
Shared active layer and source/drain regions, therefore can lift elements integrated level.
It is that the features described above of the present invention and advantage can be become apparent, special embodiment below, and join
Close institute's accompanying drawings to be described in detail below.
Brief description
Figure 1A is the profile according to a kind of three-dimensional storage depicted in one embodiment of the invention.
Figure 1B is the profile of the A-A ' tangent line of Figure 1A.
Fig. 1 C is the top view of Figure 1A.
Fig. 1 D is the circuit diagram of Figure 1A.
Fig. 2A is the profile according to a kind of three-dimensional storage depicted in another embodiment of the present invention.
Fig. 2 B is the profile of the A-A ' tangent line of Fig. 2A.
Fig. 3 A to Fig. 3 I is the system according to a kind of three-dimensional storage depicted in one embodiment of the invention
Make the profile of flow process.
Fig. 4 A to Fig. 4 I is the profile of the A-A ' tangent line of Fig. 3 A to Fig. 3 I respectively.
Fig. 5 A and Fig. 5 B is according to a kind of three-dimensional storage depicted in another embodiment of the present invention
Part Making programme profile.
Fig. 6 A and Fig. 6 B is the profile of the A-A ' tangent line of Fig. 5 A and Fig. 5 B respectively.
【Symbol description】
100、200：Substrate
110：Three-dimensional storage
120、252：Memory element laminated construction
124、224：Conductor pin
126、230：Interlayer insulating film
128、232：Connector
130、234：Bit line
132、222：Memory cell array structure
134、202：Insulating barrier
136、204：Wordline
138：Active layer
140、211：Composite bed
142、146、206、210：Dielectric layer
144、208：Electric charge storage layer
148、240：Sealing coat
150、225：Source/drain regions
154、154a、154b、154c、154d、154e、154f、254、254a、254b、254c：
Memory element
156：Contact
212：Sacrifice layer
214：Laminated structural layers
216：Hole
218：Groove
220：Conductor layer
Specific embodiment
Figure 1A is the profile according to a kind of three-dimensional storage depicted in one embodiment of the invention.
Figure 1B is the profile of the A-A ' tangent line of Figure 1A.Fig. 1 C is the top view of Figure 1A.Fig. 1 D is
The circuit diagram of Figure 1A.
Refer to Figure 1A and Figure 1B, three-dimensional storage 110 include memory element laminated construction 120,
Multiple conductor pins 124, interlayer insulating film 126, connector 128 and multiple bit lines 130.
Memory element laminated construction 120 is by multiple memory cell array structures 132 and multiple insulating barriers
134 cross laminates form.Each memory cell array structure 132 includes multiple wordline 136, Duo Geyou
Active layer 138, multiple composite bed 140 and multiple source/drain pole region 150.
Multiple wordline 136 e.g. extend in the Y direction, are set parallel to each other.The material of wordline 136
Including conductor material, e.g. polysilicon or DOPOS doped polycrystalline silicon.Wordline 136 e.g. doubles as simultaneously
The control gate of memory element.
Multiple active layers 138 e.g. extend in the Y direction, are set parallel to each other.138 points of active layer
It is not arranged between adjacent wordline 136.The material of active layer 138 includes conductor material, e.g.
Polysilicon or DOPOS doped polycrystalline silicon.
Multiple composite beds 140 e.g. extend in the Y direction, are set parallel to each other.140 points of composite bed
It is not arranged between adjacent wordline 136 and active layer 138.Each composite bed 140 is by active layer 138
Rise and sequentially include dielectric layer 142, electric charge storage layer 144 and dielectric layer 146.
Dielectric layer 142 is for example to extend in the Y direction respectively, is set parallel to each other.Dielectric layer 142
Material includes dielectric material, e.g. silicon oxide.Dielectric layer 142 is for example as tunnel dielectric layer.
Electric charge storage layer 144 e.g. extends in the Y direction, is set parallel to each other.Electric charge storage layer
144 material includes making electric charge to be trapped in material therein, e.g. silicon nitride, tantalum oxide,
Strontium titanates and hafnium oxide etc..The material of electric charge storage layer 144 is, for example, silicon nitride in the present embodiment.
(and in another embodiment, the material of electric charge storage layer 144 includes conductor material, e.g. polysilicon
Or DOPOS doped polycrystalline silicon, below, Fig. 2A and Fig. 2 B can describe in detail again).Electric charge storage layer 144
In this way as floating grid.
Dielectric layer 146 is for example to extend in the Y direction respectively, is set parallel to each other.Dielectric layer 146
Material includes dielectric material, e.g. silicon oxide, silicon nitride, silicon oxynitride.Dielectric layer 146 is permissible
It is single layer structure or more than one layer of multiple structure, such as silicon oxide/silicon nitride or silicon oxide
/ silicon nitride/silicon oxide layer etc..In the present embodiment, the material of dielectric layer 146 is, for example, silicon oxide.
Source/drain regions 150 are e.g. arranged in active layer 138 at equal intervals.Source/drain regions 150
Material include conductor material, e.g. DOPOS doped polycrystalline silicon, germanide, metal silicide or metal.
The admixture of active layer 138 is different from the admixture of source/drain regions 150.For example, work as active layer
138 when being the polysilicon containing N-type admixture, and source/drain regions 150 are the polycrystalline containing p-type admixture
Silicon；And when active layer 138 is the polysilicon containing p-type admixture, source/drain regions 150 be containing
The polysilicon of N-type admixture.
Adjacent two source/drain regions 150, active between above-mentioned two source/drain regions 150
Layer 138 and the dielectric layer 142 on above-mentioned active layer 138, electric charge storage layer 144, dielectric layer
146 with wordline 136, collectively form memory element 154.
Multiple insulating barriers 134, for example, be disposed between adjacent memory cell array structure 132.
The material of insulating barrier 134 includes insulant, e.g. silicon oxide.
Conductor pin 124 e.g. extends in Z-direction, is electrically connected with memory element laminated construction 120
The source/drain regions 150 of relative position in each memory cell array structure 132.Conductor pin 124
Material include conductor material, e.g. polysilicon, DOPOS doped polycrystalline silicon, germanide, metal silicide
Or metal.
Interlayer insulating film 126 is for example provided on memory element laminated construction 120.Interlayer insulating film
126 material includes insulant, e.g. silicon oxide, phosphorosilicate glass, boron-phosphorosilicate glass or other
Suitable dielectric material.
Connector 128 is for example disposed in interlayer insulating film 126.The material of connector 128 includes conductor
Material, e.g. polysilicon, DOPOS doped polycrystalline silicon, metal silicide or metal.
Multiple bit lines 130 e.g. extend in X-direction, are set parallel to each other.Bit line 130 is through slotting
Plug 128 is electrically connected with conductor pin 124.And, refer to Fig. 1 C, bit line 130 is electrically connected with
Conductor pin 124 in X-direction.The material of bit line 130 includes conductor material, e.g. polysilicon,
DOPOS doped polycrystalline silicon, metal silicide or metal.
Referring to Figure 1A to Fig. 1 D, in memory cell array structure 132, multiple storages are single
Meta-rule arranges, and/the column array that is arranged in rows.In the X direction, as shown in Figure 1B, adjacent two
Individual memory element shared word line 136 (as memory element 154 and memory element 154a) or shared active layer
138 with source/drain regions 150 (as memory element 154 and memory element 154b).And, in X side
Upwards, as shown in Figure 1 C, bit line 130 is electrically connected with the source/drain regions 150 in X-direction.?
In Y-direction, as shown in Figure 1B, multiple memory element series connection connect and shared word line is (as memory element
154b, memory element 154c and memory element 154e and memory element 154a, memory element 154d
With memory element 154f).In z-direction, as shown in Figure 1A, conductor pin is electrically connected with memory element
Source/drain regions 150 in laminated construction 120.By above-mentioned electric connection mode, as Fig. 1 D institute
Show, form three-dimensional storage 110.Wherein, in order to clearly show that circuit in Fig. 1 D, using becoming
To contact 156 represent same conductor pin 124 (source/drain regions 150).Electrically connected by above-mentioned
The mode connecing, applies suitable voltage to corresponding bit line with wordline under different operation modes, with
Three-dimensional storage is controlled to execute the steps such as programming, reading, erasing.
In the three-dimensional storage of the present invention, two adjacent memory element shared word line are (as shown in Figure 1B
Memory element 154 and memory element 154a) or shared active layer with source/drain regions (as Figure 1B institute
The memory element 154 shown and memory element 154b), therefore can lift elements integrated level.
Fig. 2A is the profile according to a kind of three-dimensional storage depicted in another embodiment of the present invention.
Fig. 2 B is the profile of the A-A ' tangent line of Fig. 2A.
Refer to Fig. 2A and Fig. 2 B, in this embodiment, the material of electric charge storage layer 144 includes leading
Body material, e.g. polysilicon or DOPOS doped polycrystalline silicon, and further include multiple sealing coats 148, setting
In electric charge storage layer 144, to isolate adjacent in the Y direction memory element (depositing as shown in Figure 2 B
Storage unit 154 and memory element 154c) electric charge storage layer 144.The material of sealing coat 148 is, for example,
Silicon oxide.Remaining component is same as the previously described embodiments.
Fig. 3 A to Fig. 3 I is the system according to a kind of three-dimensional storage depicted in one embodiment of the invention
Make the profile of flow process.Fig. 4 A to Fig. 4 I is the section of the A-A ' tangent line of Fig. 3 A to Fig. 3 I respectively
Figure.
Refer to Fig. 3 A and Fig. 4 A, substrate 200 is provided first.Then formed absolutely in substrate 200
Edge layer 202.The material of insulating barrier 202 includes insulant, e.g. silicon oxide.Insulating barrier 202
Forming method be, for example, chemical vapour deposition technique.
Then, wordline 204 is formed on insulating barrier 202.The material of wordline 204 includes conductor material,
E.g. polysilicon or DOPOS doped polycrystalline silicon.The forming method of wordline 204 is, for example, on insulating barrier 202
Form conductor layer (not illustrating), then chemical wet etching is carried out to this conductor layer and form wordline 204.Lead
The forming method of body layer is, for example, chemical vapour deposition technique.
Refer to Fig. 3 B and Fig. 4 B, to the side wall less than wordline 204 sequentially form dielectric layer 206 with
Electric charge storage layer 208.The material of dielectric layer 206 includes dielectric material, e.g. silicon oxide, nitridation
Silicon, silicon oxynitride.Dielectric layer 206 can be the multilamellar knot of single layer structure or more than a layer
Structure, such as silicon oxide/silicon nitride or silicon oxide/silicon nitride/silicon oxide layer etc..In the present embodiment, it is situated between
The material of electric layer 206 is, for example, silicon oxide.The material of electric charge storage layer 208 includes making electric charge fall into
Enter material therein, e.g. silicon nitride, tantalum oxide, strontium titanates and hafnium oxide etc..In this enforcement
In example, the material of electric charge storage layer 208 is, for example, that (and in another embodiment, electric charge stores silicon nitride
The material of layer 208 includes conductor material, e.g. polysilicon or DOPOS doped polycrystalline silicon, in Fig. 5 A below
Can describe in detail again to Fig. 6 B).Dielectric layer 206 with the forming method of electric charge storage layer 208 is, for example,
The dielectric materials layer (not illustrating) covering insulating barrier 202 and wordline 204 is sequentially formed on substrate 200
With charge storage layers (not illustrating), then remove the dielectric materials layer in wordline 204 and electric charge storage
Deposit material layer, until exposing wordline 204 and forming dielectric layer 206 and electric charge storage layer 208.It is situated between
Material layer is, for example, chemical vapour deposition technique with the forming method of charge storage layers.Remove wordline
Dielectric materials layer on 204 is, for example, chemical mechanical milling method with the method for charge storage layers.
Refer to Fig. 3 C and Fig. 4 C, remove the electric charge storage on the dielectric layer 206 between wordline 204
Layer 208.Remove the method for electric charge storage layer 208 on the dielectric layer 206 between wordline 204 for example
It is dry etching method.
Refer to Fig. 3 D and Fig. 4 D, form dielectric layer 210 to the side wall less than electric charge storage layer 208,
And sacrifice layer 212 is formed on the dielectric layer 210 between wordline 204.The material of dielectric layer 210
Including dielectric material, e.g. silicon oxide.The material of sacrifice layer 212 need to insulating barrier 202 and with
Dielectric layer 210 has enough etching selection ratio, and there is no particular restriction in addition.In the present embodiment,
The material of sacrifice layer 212 is, for example, silicon nitride.Dielectric layer 210 and the forming method example of sacrifice layer 212
Covering wordline 204, dielectric layer 206 and electric charge storage layer 208 are sequentially formed in this way on substrate 200
Dielectric materials layer (not illustrating) and sacrificial material layer (not illustrating), then remove the dielectric in wordline 204
Material layer and sacrificial material layer, until exposing wordline 204 and forming dielectric layer 210 and sacrifice layer 212.
Dielectric materials layer is, for example, chemical vapour deposition technique with the forming method of sacrificial material layer.Remove wordline
Dielectric materials layer on 204 is, for example, chemical mechanical milling method with the method for sacrificial material layer.
Now, lamination layer 214 is defined on insulating barrier 202, lamination layer 214 include wordline 204,
Composite bed 211 and sacrifice layer 212.Composite bed 211 includes dielectric layer 210, electric charge storage layer 208
With dielectric layer 206.
Refer to Fig. 3 E and Fig. 4 E, the step repeating Fig. 3 A (Fig. 4 A) to Fig. 3 D (Fig. 4 D), Yu Ji
Multilayer dielectric layer 202 and multi-laminate layer by layer 214 is formed on bottom 200.
Refer to Fig. 3 F and Fig. 4 F, in the sacrifice layer 212 of lamination layer 214, along the Y direction etc.
Interval forms multiple holes 216.Hole 216 extends in Z-direction, and multi-laminate layer by layer 214 is run through in hole 216
With multilayer dielectric layer 202, and expose every stacking layer by layer 214 sacrifice layer 212.Form hole 216
Method be e.g. initially formed patterning photoresist layer (not illustrating) and define the predetermined position in hole 216, then
Photoresist layer is patterned as mask with this, remove lamination layer 214 under the predetermined position in hole 216 with absolutely
Edge layer 202.Remove the method example of the lamination layer 214 under the predetermined position in hole 216 and insulating barrier 202
Wet etching method or dry etching method in this way.
Refer to Fig. 3 G and Fig. 4 G, via hole 216 remove every stacking layer by layer 214 sacrifice layer 212,
With the groove 218 forming active layer predetermined after being formed.The method removing sacrifice layer 212 is e.g. wet
Method etching method or dry etching method.
Refer to Fig. 3 H and Fig. 4 H, conductor layer 220 is formed on substrate to be filled in hole 216 and ditch
Groove 218.The material of conductor layer 220 includes conductor material, e.g. polysilicon or DOPOS doped polycrystalline silicon.
The forming method of conductor layer 220 is, for example, chemical vapour deposition technique.
Refer to Fig. 3 I and Fig. 4 I, remove the conductor layer 220 positioned at hole 216.Remove positioned at hole 216
The method of conductor layer 220 be e.g. initially formed patterning photoresist layer (not illustrating) and expose hole 216
Region, then photoresist layer is patterned as mask with this, remove the conductor layer 220 of the position positioned at hole 216.
The method removing the conductor layer 220 of position positioned at hole 216 is, for example, wet etching method or dry etching
Method.
Then, form conductor pin 224 in hole 216.The material of conductor pin 224 includes conductor material,
E.g. polysilicon or DOPOS doped polycrystalline silicon, germanide, metal silicide or metal.Conductor pin 224
Forming method is, for example, chemical vapour deposition technique.Conductor pin 224 is in memory cell array structure 222
Part as source/drain regions 225.
The admixture of conductor layer 220 is different from the admixture of conductor pin 224.For example, when conductor layer 220 is
During the polysilicon containing N-type admixture, conductor pin 224 is the polysilicon containing p-type admixture；And work as and lead
When body layer 220 is the polysilicon containing p-type admixture, conductor pin 224 is the polycrystalline containing N-type admixture
Silicon.
Now, that is, form memory element laminated construction 252.Memory element laminated construction 252 is by multiple
Memory cell array structure 222 is formed with multiple insulating barrier 202 cross laminates.Each memory cell array
Structure 222 includes multiple wordline 204, multiple conductor layer 220, multiple composite bed 211, multiple source electrode
/ drain region 225.Composite bed 211 includes dielectric layer 210, electric charge storage layer 208 and dielectric layer 206.
Adjacent two source/drain regions 225, the conductor between above-mentioned two source/drain regions 225
Layer 220 and the dielectric layer 210 in above-mentioned conductor layer 220, electric charge storage layer 208, dielectric layer
206 with wordline 204, collectively form memory element 254.Wherein conductor layer 220 is for example as active
Layer, for example as tunnel dielectric layer, electric charge storage layer 208 is for example as floating for dielectric layer 210
Grid, dielectric layer 206 for example as grid between dielectric layer, wordline 204 e.g. doubles as depositing simultaneously
The control gate of storage unit.
Then, interlayer insulating film 230 is formed on memory element laminated construction 252.Interlayer insulating film
230 material is, for example, silicon oxide, phosphorosilicate glass, boron-phosphorosilicate glass or other suitable dielectric materials,
Its forming method is, for example, chemical vapour deposition technique.Then, formed respectively in interlayer insulating film 230
It is electrically connected with multiple connectors 232 of conductor pin 224.The material of connector 232 includes conductor material, example
Polysilicon, DOPOS doped polycrystalline silicon, metal silicide or metal in this way.
The step forming connector 232 in interlayer insulating film 230 is as follows.Remove part interlayer first exhausted
Edge layer 232 exposes multiple openings of conductor pin 224 respectively to be formed.Then, shape in substrate 200
Become one layer of conductor material layer (not illustrating) filling up opening.Afterwards, removed using chemical mechanical milling method
Part conductor material layer, until exposing interlayer insulating film 230.The forming method of its split shed is for example
It is chemical wet etching method.
Then, bit line 234 is formed on interlayer insulating film 230.Bit line 234, extends in X-direction,
It is set parallel to each other.Bit line 234 is electrically connected with conductor pin 224 by connector 232.And, position
Line 234 is electrically connected at the conductor pin 224 (refer to Fig. 1 C) of X-direction.The material example of bit line 234
Polysilicon, DOPOS doped polycrystalline silicon, metal silicide or metal in this way.The forming method of bit line 234 is for example
It is prior to conductor material layer (not illustrating), then patterned conductor material are formed on substrate 200 in substrate
The bed of material and form bit line 234.The forming method of conductor material layer is, for example, chemical vapour deposition technique.
Fig. 5 A and Fig. 5 B is according to a kind of three-dimensional storage depicted in another embodiment of the present invention
Part Making programme profile.Fig. 6 A and Fig. 6 B is the A-A ' of Fig. 5 A and Fig. 5 B respectively
The profile of tangent line.
In another embodiment, after the steps being Fig. 3 D and Fig. 4 D different from above-described embodiment,
The step adding Fig. 5 A and Fig. 5 B, step afterwards is same as the previously described embodiments.
Refer to Fig. 5 A and Fig. 6 A, in the electric charge storage layer 208 of lamination layer 214, along Y
Direction forms multiple sealing coats 240 at equal intervals, and sealing coat 240 isolates adjacent memory element (as Fig. 6 A
Shown memory element 254 and memory element 254c) electric charge storage layer 208.The material of sealing coat 240
Material is, for example, silicon oxide.The forming method of sealing coat 240 is e.g. initially formed patterning photoresist layer (not
Illustrate) define the predetermined position of sealing coat 240, then photoresist layer is patterned as mask with this, remove every
After electric charge storage layer 208 under the predetermined position of absciss layer 240, then spacer material layer (not illustrating) is filled out
Enter, and remove part spacer material layer using chemical mechanical milling method, until exposing wordline 204
And form sealing coat 240.The method inserting spacer material layer is, for example, chemical vapour deposition technique.
Refer to Fig. 5 B and Fig. 6 B, remove remaining electric charge storage layer 208, and in the storage of script electric charge
Electric charge storage layer 242 is inserted in the position depositing layer 208.The material of electric charge storage layer 242 is, for example, polycrystalline
Silicon or DOPOS doped polycrystalline silicon.Remove remaining electric charge storage layer 208 method be, for example, dry etching method or
Wet etching method.The method inserting electric charge storage layer 242 is not e.g. by charge storage layers (illustrating)
Insert the position of script electric charge storage layer 208, and remove Partial charge using chemical mechanical milling method
Storage material layer, until exposing wordline 204 and forming electric charge storage layer 242.Insert electric charge storage
The method of material layer is, for example, chemical vapour deposition technique.
In sum, in the three-dimensional storage of the present invention, two adjacent memory element shared word line are (such as
Memory element 254 shown in Fig. 4 I and memory element 254a) or shared active layer is with source/drain regions (such as
Memory element 254 shown in Fig. 4 I and memory element 254b), therefore can lift elements integrated level.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, Ren Hesuo
Belong to and in technical field, have usually intellectual, without departing from the spirit and scope of the present invention, when can make
A little change and retouching, therefore protection scope of the present invention ought be defined depending on appended claims scope
Be defined.
Claims (10)
1. a kind of three-dimensional storage, including：
Memory element laminated construction, by multiple memory cell array structures and multiple insulating barrier cross laminates
Form, each described memory cell array structure includes：
Multiple wordline, extend in the Y direction；
Multiple active layers, extend in described Y-direction, and described active layer is arranged at adjacent described
Between wordline；
Multiple composite beds, described Y-direction extend, be arranged at adjacent described wordline with described
Between active layer, each described composite bed sequentially includes the first dielectric layer, electric charge storage by described active layer
Deposit layer and the second dielectric layer；And
Multiple source/drain pole region, is arranged in described active layer at equal intervals, wherein adjacent two
Described source/drain regions, the active layer between two described source/drain regions and have in described
Described first dielectric layer in active layer, described electric charge storage layer, described second dielectric layer and described wordline,
Collectively form memory element.
2. three-dimensional storage according to claim 1, further includes multiple conductor pins, in Z side
To extension, it is electrically connected with the described source/drain regions in described memory element laminated construction.
3. three-dimensional storage according to claim 1, further includes multiple bit lines, in X-direction
Extend, described bit line is electrically connected at the described conductor pin of described X-direction.
4. three-dimensional storage according to claim 3, the material of wherein said bit line includes many
Crystal silicon, DOPOS doped polycrystalline silicon, metal silicide or metal.
5. three-dimensional storage according to claim 1, the material of wherein said electric charge storage layer
Including silicon nitride, polysilicon or DOPOS doped polycrystalline silicon, and further include multiple sealing coats, be arranged at described
In electric charge storage layer, to isolate the described electric charge storage layer of adjacent described memory element.
6. three-dimensional storage according to claim 1, wherein said wordline and described active layer
Material include polysilicon or DOPOS doped polycrystalline silicon respectively.
7. three-dimensional storage according to claim 1, wherein said source/drain regions with described
The material of conductor pin includes polysilicon, DOPOS doped polycrystalline silicon, germanide, metal silicide or metal.
8. three-dimensional storage according to claim 1, wherein said first dielectric layer, described
Second dielectric layer includes silicon oxide respectively with the material of described insulating barrier.
9. three-dimensional storage according to claim 1, wherein in each described memory cell array
In structure, in described X-direction, two adjacent described memory element shared word line or shared active
Layer and source/drain regions.
10. three-dimensional storage according to claim 1, wherein in each described memory cell array
In structure, in described Y-direction, multiple described memory element series connection connect and shared word line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510506194.7A CN106469732B (en) | 2015-08-18 | 2015-08-18 | Three-dimensional storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510506194.7A CN106469732B (en) | 2015-08-18 | 2015-08-18 | Three-dimensional storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106469732A true CN106469732A (en) | 2017-03-01 |
| CN106469732B CN106469732B (en) | 2019-05-31 |
Family
ID=58214220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510506194.7A Active CN106469732B (en) | 2015-08-18 | 2015-08-18 | Three-dimensional storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106469732B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112117272A (en) * | 2017-03-07 | 2020-12-22 | 长江存储科技有限责任公司 | Trench structure for three-dimensional memory device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101271868A (en) * | 2007-03-22 | 2008-09-24 | 力晶半导体股份有限公司 | Non-volatile memory and its manufacturing method |
| US20080237602A1 (en) * | 2007-03-27 | 2008-10-02 | Sandisk 3D Llc | Three dimensional nand memory |
| CN101681884A (en) * | 2007-03-27 | 2010-03-24 | 桑迪士克3D公司 | Three dimensional NAND memory and method of making thereof |
| CN104040633A (en) * | 2010-12-14 | 2014-09-10 | 桑迪士克3D有限责任公司 | Continuous mesh three dimensional non-volatile storage with vertical select devices |
-
2015
- 2015-08-18 CN CN201510506194.7A patent/CN106469732B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101271868A (en) * | 2007-03-22 | 2008-09-24 | 力晶半导体股份有限公司 | Non-volatile memory and its manufacturing method |
| US20080237602A1 (en) * | 2007-03-27 | 2008-10-02 | Sandisk 3D Llc | Three dimensional nand memory |
| CN101681884A (en) * | 2007-03-27 | 2010-03-24 | 桑迪士克3D公司 | Three dimensional NAND memory and method of making thereof |
| CN104040633A (en) * | 2010-12-14 | 2014-09-10 | 桑迪士克3D有限责任公司 | Continuous mesh three dimensional non-volatile storage with vertical select devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112117272A (en) * | 2017-03-07 | 2020-12-22 | 长江存储科技有限责任公司 | Trench structure for three-dimensional memory device |
| CN112117272B (en) * | 2017-03-07 | 2024-04-26 | 长江存储科技有限责任公司 | Trench structure of three-dimensional memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106469732B (en) | 2019-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111742368B (en) | Three-dimensional NOR memory arrays with very fine pitch: apparatus and method | |
| TWI713203B (en) | Memory device and method for fabricating the same | |
| CN110114881B (en) | Through array contact structure for three-dimensional memory device | |
| CN102610616B (en) | Low cost scalable 3d memory and its manufacture method | |
| CN104465496B (en) | There is the device and manufacture method of multiple vertically extending conductors for three-dimensional devices | |
| TWI447851B (en) | Multilayer connection structure and making method | |
| US10566348B1 (en) | Tilted hemi-cylindrical 3D NAND array having bottom reference conductor | |
| CN104867930A (en) | Method for manufacturing storage device | |
| CN105280606A (en) | CONTACT STRUCTURE, FORMING METHOD and LOOP EMPLOYING SAME | |
| JP2019067825A (en) | Semiconductor device | |
| CN109300907A (en) | 3D memory device and its manufacturing method | |
| CN104051331B (en) | Damascus semiconductor device of 3D array and forming method thereof | |
| TWI575714B (en) | Three-dimensional memory | |
| CN104051467A (en) | 3-D IC Device with Enhanced Contact Area | |
| CN109686740A (en) | 3D memory device and its manufacturing method | |
| KR20120121171A (en) | Semiconductor device and method for manufacturing resistor of semiconductor device and 3d structured non-volatile memory device | |
| CN208690260U (en) | 3D memory device | |
| TWI602281B (en) | 3d capacitor and manufacturing method for the same | |
| CN106469732A (en) | Three-dimensional storage | |
| US9437612B1 (en) | Three-dimensional memory | |
| CN207529977U (en) | Integrated circuit and electronic device | |
| CN105304573A (en) | Three-dimensional memory element and manufacturing method thereof | |
| US20150325585A1 (en) | Method for forming three-dimensional memory and product thereof | |
| TWI532148B (en) | Semiconductor device and method for manufacturing the same | |
| TWI580086B (en) | Memory device and manufacturing method of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |