CN105990314B - Semiconductor device structure and forming method thereof - Google Patents
Semiconductor device structure and forming method thereof Download PDFInfo
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- CN105990314B CN105990314B CN201510783049.3A CN201510783049A CN105990314B CN 105990314 B CN105990314 B CN 105990314B CN 201510783049 A CN201510783049 A CN 201510783049A CN 105990314 B CN105990314 B CN 105990314B
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Abstract
The present invention provides a kind of semiconductor device structures.Semiconductor device structure includes substrate and the first dielectric layer above substrate.Semiconductor device structure includes the second dielectric layer positioned at the first dielectric layer.First dielectric layer and the second dielectric layer are made from a variety of materials.Semiconductor device structure includes across the first dielectric layer and penetrating the conductivity through-hole structure in the second dielectric layer.Conductivity through-hole structure has first part and second part, and first part and second part are located in the first dielectric layer and the second dielectric layer.First part has the first end towards substrate, and the first width of first end is more than the second width of second part.
Description
Cross reference to related applications
The application in " SEMICONDUCTOR DEVICE STRUCTURE submitting and entitled on March 16th, 2015
The common generation of AND METHOD FOR FORMING THE SAME " in, determines and commonly assigned U.S. Patent Application No. 14658,525
Number, entire contents are hereby expressly incorporated by reference.
Technical field
The present invention relates to semiconductor device structures and forming method thereof.
Background technology
Semiconductor integrated circuit (IC) industry experienced fast development.Technological progress in IC materials and design has generated
The IC in several generations.Often all have than previous generation IC smallers and more complicated circuit for IC.However, these progress increase processing and
Produce the complexity of IC
In IC development process, the functional density quantity of interconnection devices (that is, on each chip area) has usually increased
And geometric dimension (that is, the minimum component (or line) that can be manufactured using manufacturing process) has been reduced.Usually it is this in proportion
Reduction process brings benefit by improving production efficiency and reducing relevant cost.
However, since part dimension continues to reduce, manufacturing process continues to become difficult to implement.Therefore, it is formed smaller and smaller
The reliable semiconductor devices of size is a kind of challenge.
Invention content
In order to solve the problems in the prior art, according to some embodiments of the present invention, a kind of semiconductor devices is provided
Structure, including：Substrate；First dielectric layer is located above the substrate；Second dielectric layer is located at first dielectric layer,
Wherein, first dielectric layer and second dielectric layer are made from a variety of materials；And conductivity through-hole structure, it passes through described
It first dielectric layer and is penetrated into second dielectric layer, wherein the conductivity through-hole structure has first part and second
Part, the first part and the second part are located in first dielectric layer and second dielectric layer, described
First part has the first end towards the substrate, and the first width of the first end is more than the second part
The second width.
Other embodiments according to the present invention provide a kind of semiconductor device structure, including：Substrate；First dielectric
Layer is located above the substrate；Second dielectric layer is located at first dielectric layer, wherein first dielectric layer and institute
The second dielectric layer is stated to be made from a variety of materials；And conductivity through-hole structure, across first dielectric layer and it is penetrated into institute
It states in the second dielectric layer, wherein the conductivity through-hole structure has first part and second part, the first part and described
Second part is located in first dielectric layer and second dielectric layer, and the first width of the first part exists
Continuously increase from second dielectric layer to the direction of the substrate.
Other embodiment according to the present invention provides a kind of method being used to form semiconductor device structure, including：
It is rectangular at the first dielectric layer on substrate；The second dielectric layer is formed in first dielectric layer, wherein first dielectric
Layer and second dielectric layer are made from a variety of materials；Through-hole is formed in first dielectric layer and is situated between described second
Hole is formed in electric layer, wherein the through-hole is connected to the hole, and the through-hole has the first end opening and the second end opening, institute
The first end opening is stated towards the substrate, for second end opening towards the hole, the first width of first end opening is big
In the second width of second end opening；And form conductivity through-hole structure in the through-hole and the hole.
Description of the drawings
When reading in conjunction with the accompanying drawings, each aspect of the present invention is best understood from described in detail below.It should note
Meaning, according to the standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, all parts
Size can arbitrarily increase or reduce.
Figure 1A to Fig. 1 H is each stage of the technique in accordance with some embodiments for being used to form semiconductor device structure
Sectional view.
Fig. 2A to Fig. 2 C is the top view of the structure in Figure 1A to Figure 1B and Fig. 1 H respectively in accordance with some embodiments.
Fig. 3 is the sectional view of semiconductor device structure in accordance with some embodiments.
Fig. 4 is the sectional view of semiconductor device structure in accordance with some embodiments.
Specific implementation mode
Following disclosure provides the different embodiments or reality of many different characteristics for realizing the theme provided
Example.The specific example of component and arrangement is described below to simplify the present invention.Certainly, these are only example, and are not intended to limit
System.For example, in the following description, above second component or the upper formation first component may include the first component and second
Part to be in direct contact the embodiment to be formed, and can also be included between the first component and second component can be formed it is additional
Component, so that the embodiment that the first component and second component can be not directly contacted with.In addition, the present invention can be in each example
Middle repeat reference numerals and/or character.The repetition is for purposes of simplicity and clarity, and itself not indicate to be discussed
Relationship between each embodiment and/or configuration.
Moreover, for ease of description, can use herein such as " ... under ", " in ... lower section ", " lower part ", " ... it
On ", the spatially relative term on " top " etc., to describe an element as shown in the figure or component and another (or other) member
The relationship of part or component.Other than orientation shown in figure, spatially relative term be intended to include device in use or operation
Different direction.Device can otherwise orient (be rotated by 90 ° or in other directions), and space used herein is opposite
Descriptor can be explained similarly accordingly.It should be appreciated that before the process per se, during and after additional behaviour can be provided
Make, and for the other embodiment of this method, some operations of description can be substituted or eliminated.
Figure 1A to Fig. 1 H is each stage of the technique in accordance with some embodiments for being used to form semiconductor device structure 100
Sectional view.Fig. 2A to Fig. 2 C is the top view of the structure in Figure 1A to Figure 1B and Fig. 1 H respectively in accordance with some embodiments.
Figure 1A to Figure 1B and Fig. 1 H be it is in accordance with some embodiments show respectively along in Fig. 2A to Fig. 2 C hatching 1A-1A ',
The sectional view of the structure of 1B-1B ', 1H-1H ' interception.
As shown in Figure 1A, according to some embodiments, substrate 110 is provided.Substrate 110 can be the semiconductor of such as Silicon Wafer
Wafer.Alternatively or additionally, substrate 110 may include elemental semiconductors, compound semiconductor materials and/or alloy
Semi-conducting material.
The example of elemental semiconductors can be but not limited to crystalline silicon, polysilicon, non-crystalline silicon, germanium and/or diamond.Change
Silicon carbide, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or antimony can be but not limited to by closing the example of object semi-conducting material
Indium.The example of alloy semiconductor material can be but not limited to SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/
Or GaInAsP.
As shown in Figure 1A, according to some embodiments, isolation structure 111 is formed in semiconductor substrate 110.According to some realities
Example is applied, isolation structure 111 surrounds the device region of semiconductor substrate 110.According to some embodiments, the configuration of isolation structure 111 is limited
Determine and is electrically isolated the various components (not shown) formed in semiconductor substrate 110.
The example of element can include but is not limited to transistor, diode and/or other applicable elements.The reality of transistor
Example can include but is not limited to mos field effect transistor (MOSFET), complementary metal oxide semiconductor
(CMOS) transistor, bipolar junction transistor (BJT), high voltage transistor, high frequency transistor, p-channel and/or n-channel field effect
Answer transistor (PFET/NFET) etc..Implement the more of such as deposition, etching, injection, photoetching, annealing and/or other applicable techniques
Kind technique is to form components.
As shown in Figure 1A, according to some embodiments, dielectric layer is formed above semiconductor substrate 110 and isolation structure 111
120.According to some embodiments, dielectric layer 120 includes dielectric material.The example of dielectric material can include but is not limited to aoxidize
Object, SiO2, boron phosphorus silicate glass (BPSG), spin-coating glass (SOG), undoped silicate glass (USG), fluorinated silicate
The ethyl orthosilicate (PETEOS) of glass (FSG), high-density plasma (HDP) oxide or plasma enhancing.
Dielectric layer 120 may include a variety of dielectric materials by such as low-k or extremely low dielectric constant (ELK) material
Multilayer made of material.Chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating can be passed through
Or another applicable technique forms dielectric layer 120.
As shown in Figure 1A, according to some embodiments, groove 122 is formed in dielectric layer 120.According to some embodiments, make
Groove 122 is formed with photoetching process and etch process.As shown in Figure 1A, according to some embodiments, blocking is formed in groove 122
Layer 132.According to some embodiments, the inner wall 122a and bottom surface 122b of the conformally covering groove 122 of barrier layer 132.According to some
Embodiment, the metal material that barrier layer 132 is configured to prevent from being formed in groove 122 diffuse in dielectric layer 120.Barrier layer
132 include tantalum or another suitable material.According to some embodiments, barrier layer 132 is formed using physical vapor deposition process.
As shown in Figure 1A, according to some embodiments, seed layer 134 is formed above barrier layer 132.Seed layer 134 includes
Copper (Cu) and manganese (Mn) or other suitable materials.According to some embodiments, seed layer is formed using physical vapor deposition process
134.As shown in Figure 1A, according to some embodiments, conductor wire 136 is formed in groove 122 and above seed layer 134.It is conductive
Line 136 includes aluminium (Al), copper (Cu) or another suitable material.According to some embodiments, conductor wire is formed using depositing process
136。
As shown in Figure 1A, according to some embodiments, in dielectric layer 120, barrier layer 132, seed layer 134 and conductor wire 136
Top forms dielectric layer 140.According to some embodiments, dielectric layer 140 is configured to that the metal material of conductor wire 136 is prevented to be diffused into
In the dielectric layer for the side of being formed thereon.
According to some embodiments, dielectric layer 140 includes dielectric material.Dielectric layer 140 includes silicon carbide, silicon nitride or another
Suitable dielectric material.According to some embodiments, dielectric layer 120 and 140 is made from a variety of materials.Dielectric layer 140 can wrap
Include the multilayer made of different dielectric materials.Chemical vapor deposition (CVD), physical vapor deposition (PVD), atom can be passed through
Layer deposition (ALD), spin coating or another applicable technique form dielectric layer 140.
As shown in Figure 1A, according to some embodiments, adhesive layer 150 is formed above dielectric layer 140.Adhesive layer 150 configures
For dielectric layer 140 to be adhered to another dielectric layer on dielectric layer 140.Adhesive layer 150 includes ethyl orthosilicate (TEOS)
Or another suitable material.In some other embodiments, adhesive layer 150 is not formed.
As shown in Figure 1A, according to some embodiments, dielectric layer 160 is formed above adhesive layer 150.According to some implementations
Example, dielectric layer 160 and 140 is made from a variety of materials, so that dielectric layer 160 and 140 can be in subsequent etch process
In have etching selectivity.According to some embodiments, dielectric layer 160 and 140 and adhesive layer 150 be to be made from a variety of materials
's.
According to some embodiments, dielectric layer 160 includes dielectric material.The example of dielectric material can include but is not limited to oxygen
Compound, SiO2, boron phosphorus silicate glass (BPSG), spin-coating glass (SOG), undoped silicate glass (USG), fluorination silicic acid
The ethyl orthosilicate (PETEOS) of salt glass (FSG), high-density plasma (HDP) oxide or plasma enhancing.
Dielectric layer 160 may include a variety of dielectric materials by such as low-k or extremely low dielectric constant (ELK) material
Multilayer made of material.Chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating can be passed through
Or another applicable technique forms dielectric layer 120.
As shown in Figure 1A, according to some embodiments, etching stopping layer 170 is formed above dielectric layer 160.Etching stopping layer
170 include silicon nitride, silica or other suitable materials.According to some embodiments, formed using chemical vapor deposition process
Etching stopping layer 170.
As shown in Figure 1A, according to some embodiments, etching stopping layer 170 is formed above dielectric layer 160.Etching stopping layer
170 include silicon nitride, silica or other suitable materials.According to some embodiments, formed using chemical vapor deposition process
Etching stopping layer 170.
As shown in Figure 1A, according to some embodiments, mask layer 180 is formed above etching stopping layer 170.In some implementations
In example, mask layer 180 includes oxide, such as silica.In some embodiments, mask layer 180 includes silicon nitride, nitridation
Titanium, other applicable materials or combination thereof.In some embodiments, mask layer is formed using chemical vapor deposition process
18。
As shown in Figure 1A and Fig. 2A, according to some embodiments, hard mask layer 190 is formed above mask layer 180.According to one
A little embodiments, hard mask layer 190 have groove 192 and 194.According to some embodiments, groove 192 and 194 exposes mask layer
180 part.
The example of the material of hard mask layer 190 includes but not limited to silica, silicon nitride (for example, Si3N4)、SiON、SiC、
SiOC or combination thereof.Can by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD),
Spin coating or other applicable techniques form hard mask layer 190.In some embodiments, mask layer 180 and hard mask layer 190 be by
Made of different materials, so that mask layer 180 and hard mask layer 190 have etching selection in subsequent etch process
Property.
As shown in figs. ib and 2b, according to some embodiments, coating 210 is formed in 190 top of hard mask layer and fills
To groove 192 and 194.Coating 210 is made of polymer material or another suitable material.Pass through coating process, CVD works
Skill or another suitable technique form coating 210.
As shown in figs. ib and 2b, according to some embodiments, middle layer 220 is formed above coating 210.In some implementations
In example, middle layer 220 is made of material (for example, silicon-containing polymer material).In some embodiments, mask layer
180, hard mask layer 190, coating 210 and middle layer 220 are made from a variety of materials, so that they are real later
There is etching selectivity in the etch process applied.Middle layer is formed by coating process, CVD techniques or another suitable technique
220。
As shown in figs. ib and 2b, according to some embodiments, photoresist layer 230 is formed above middle layer 220.According to some
Embodiment, photoresist layer 230 have the opening 232 for the part for exposing middle layer 220.According to some embodiments, photoresist layer
230 be made of Other substrate materials.For example, forming photoresist layer 230 by coating process and photoetching process.
As shown in Figure 1 C, it according to some embodiments, is opened by 232 removal middle layer 220 of opening and being located at for coating 210
The part of 232 lower section of mouth.According to some embodiments, after removing technique, opening across middle layer 220 and coating 210 is formed
Mouth 212.According to some embodiments, opening 212 is connected to the part of opening 232 and exposure mask layer 180.According to some implementations
Example, opening 212 are arranged in groove 194.According to some embodiments, removal technique includes dry etching process.
As shown in figure iD, according to some embodiments, middle layer 220 and photoresist layer 230 are removed.According to some embodiments,
Removal technique includes dry etching process or wet etching process.Hereafter, according to some embodiments, pass through 212 removal mask layer of opening
180 part.According to some embodiments, after removing technique, opening 182 is formed in mask layer 180 and 182 exposures that are open
Go out the part of etching stopping layer 170.
According to some embodiments, removal technique includes dry etching process.According to some embodiments, dry etching process includes etc.
Plasma technique.According to some embodiments, under pressure in the range of from about 1 millitorr to about 100 millitorr and use
Implement plasma etch process from about 100W to the power of about 1500W.According to some embodiments, from about 10 DEG C to about 70 DEG C
In the range of at a temperature of implement the plasma etch process.According to some embodiments, plasma etch process uses packet
Include CF4、H2、N2、C4F8、O2And/or CH2F2Gas.
As referring to figure 1E, according to some embodiments, coating 210 is removed.According to some embodiments, removal technique includes dry
Etch process.According to some embodiments, dry etching process includes plasma etch process.According to some embodiments, from about 1
Implement plasma erosion under pressure in the range of millitorr to about 100 millitorrs and using from about 100W to the power of about 1500W
Carving technology.According to some embodiments, in the range of from about 10 DEG C to about 70 DEG C at a temperature of implement the plasma etching work
Skill.According to some embodiments, it includes CO that plasma etch process, which uses,2、C4H8、CF4、O2、N2And/or the gas of Ar.
As shown in fig. 1F, according to some embodiments, implement etch process to remove the mask layer for being located at 192 lower section of groove
180, etching stopping layer 170, the part of dielectric layer 160 and mask layer 180, etching stopping layer positioned at 194 lower section of groove
170, the part of dielectric layer 160, adhesive layer 150 and dielectric layer 140.
After the etch process, according to some embodiments, groove 162 and 164 and hole 166 are formed in dielectric layer 160, and
And through-hole 142 is formed in dielectric layer 140.Hole 166 is located at 164 lower section of groove and is connected to groove 164 and through-hole 142.
In some embodiments, hole 166 further passs through adhesive layer 150.According to some embodiments, through-hole 142 exposes the portion of conductor wire 136
Point.According to some embodiments, through-hole 142 further exposes the part of seed layer 134.
According to some embodiments, since dielectric layer 160 and 140 is made from a variety of materials, 160 He of dielectric layer
140 can have etching selectivity in the etch process.According to some embodiments, through-hole 142 have the first end opening 142a and
Second end opening 142b.According to some embodiments, the first end opening 142a is towards substrate 110.According to some embodiments, second end
142b be open towards hole 166.
According to some embodiments, the width W1 of the first end opening 142a is more than the width W2 of the second end opening 142b.According to
Some embodiments, the width W1 of the first end opening 142a are more than the width W3 in hole 166.According to some embodiments, the first end opening
The width W1 of 142a is less than the width W of groove 164T。
According to some embodiments, etch process includes dry etching process.According to some embodiments, dry etching process includes etc.
Plasma technique.According to some embodiments, under pressure in the range of from about 1 millitorr to about 100 millitorr and use
Implement plasma etch process from about 100W to the power of about 1500W.According to some embodiments, from about 10 DEG C to about 70 DEG C
In the range of at a temperature of implement the plasma etch process.According to some embodiments, plasma etch process uses packet
Include C4F8、CF4、O2、N2And/or the gas of Ar.
As shown in Figure 1 G, according to some embodiments, barrier layer is formed in groove 162 and 164, in hole 166 and through-hole 142
242.According to some embodiments, barrier layer 242 conformally the inner wall 162a of covering groove 162 and 164, hole 166 and through-hole 142,
164a, 166a and 142c and groove 162 and 164 bottom surface 162b and 164b.
According to some embodiments, barrier layer 242 is configured to prevent from being formed in groove 162 and 164, hole 166 and through-hole 142
Metal material diffuse in dielectric layer 140 and 160 and adhesive layer 150.Barrier layer 242 includes tantalum or another suitable material.
According to some embodiments, barrier layer 242 is formed using physical vapor deposition process.
As shown in Figure 1 G, according to some embodiments, seed layer 244 is formed above barrier layer 242.Seed layer 244 includes
Copper (Cu) and manganese (Mn) or other suitable materials.According to some embodiments, seed layer is formed using physical vapor deposition process
244。
As shown in Figure 1 G, according to some embodiments, in groove 162 and 164, hole 166 and through-hole 142 and in seed layer
244 tops form conductive layer 246.Conductive layer 246 includes aluminium (Al), copper (Cu) or another suitable material.According to some implementations
Example forms conductive layer 246 using depositing process.
As shown in Fig. 1 H and Fig. 2 C, according to some embodiments, removal positioned at groove 162 and 164, hole 166 and through-hole 142,
Barrier layer 242, seed layer 244 and the conductive layer 246 in 190 outside of mask layer 180 and hard mask layer.According to some embodiments,
Removal technique includes flatening process, such as CMP process.
According to some embodiments, the conductive layer 246 being retained in groove 162 forms conductor wire 252.According to some implementations
Example, the conductive layer 246 being retained in groove 164 form conductor wire 254.In some embodiments, the top surface of conductor wire 252
The top surface 168 of 252a, the top surface 254a of conductor wire 254 and dielectric layer 160 are coplanar with each other.According to some embodiments, it is retained in
Conductive layer 246 in hole 166 and through-hole 142 forms conductivity through-hole structure 260.According to some embodiments, conductivity through-hole structure 260
It is overall structure.According to some embodiments, conductor wire 254 and conductivity through-hole structure 260 are formed as overall structure.
According to some embodiments, conductivity through-hole structure 260 passes through dielectric layer 140 and penetrates in dielectric layer 160.According to one
A little embodiments, conductivity through-hole structure 260 further pass through the adhesive layer 150 between dielectric layer 140 and 160.According to some implementations
Example, conductivity through-hole structure 260 has first part 262 and second part 264, and first part 262 and second part 264 divide
It Wei Yu not be in dielectric layer 140 and dielectric layer 160.In some embodiments, the width W of first part 262 from dielectric layer 160 to
It is increased continuously on the direction A of substrate 110.
According to some embodiments, first part 262 has first end 262a and the second end 262b.According to some implementations
Example, the second end 262b is between first end 262a and second part 264.According to some embodiments, the second end 262b
Neighbouring second part 264.In some embodiments, the width W4 of first end 262a is more than the width W5 of the second end 262b.
According to some embodiments, conductor wire 254 is located in dielectric layer 160 and above conductivity through-hole structure 260.According to
Some embodiments, second part 264 and the conductor wire 254 of conductivity through-hole structure 260 are in direct contact.According to some embodiments,
The width W4 of one end 262a is less than the width W6 of conductor wire 254.Since first end 262a is narrower than conductor wire 254, drop
The probability of low first end 262a and other conductive structures short circuit in dielectric layer 140 and 120.
According to some embodiments, conductor wire 136 is located at 260 lower section of conductivity through-hole structure and is electrically connected to conductive through hole knot
Structure 260.According to some embodiments, the width W4 of first end 262a is less than the width W8 of conductor wire 136.Due to first end
262a is narrower than conductor wire 136, therefore, reduces first end 262a and other conductive structures short circuit in dielectric layer 140 and 120
Probability.
According to some embodiments, the width W4 of first end 262a is more than the width W7 of second part 264.That is, conductive logical
Pore structure 260 has widened end (that is, first end 262a).Therefore, it increases leading with widened end 262a
Electric through-hole structure 260 is connected to the probability of conductor wire 136.As a result yield is improved.In addition, widened end 262a can increase
Connection area between conductivity through-hole structure 260 and conductor wire 136, it reduce conductivity through-hole structure 260 and conductor wire 136 it
Between contact resistance.
In some embodiments, the difference between width W4 and width W7 is in the range of from about 2nm to about 10nm.One
In a little embodiments, the ratio of width W4 and width W7 are in the range of from about 1.2 to about 1.4.
As shown in fig. 1H, according to some embodiments, inner wall 142c is planar inner wall.In some other embodiments, inner wall
142c is curved inner wall (as shown in Figure 3).As shown in fig. 1H, according to some embodiments, conductor wire 252 and 254 and conductive logical
Pore structure 260 is formed in same dielectric layer 160.In some other embodiments, according to some embodiments, 252 He of conductor wire
254 and conductivity through-hole structure 260 be formed in different dielectric layers 410 and 160 (as shown in Figure 4).As shown in figure 4, according to
Some embodiments, conductivity through-hole structure 260 pass through dielectric layer 160, adhesive layer 150 and dielectric layer 140.
According to some embodiments, semiconductor device structure and forming method thereof is provided.Method (is used to form semiconductor device
Part structure) form the conductivity through-hole structure with widened end.Therefore, it increases and leads to the conduction with widened end
Pore structure is connected to the probability for the conductive structure being disposed below.As a result, improving yield.In addition, widened end can drop
Contact resistance between low conductivity through-hole structure and the conductive structure being disposed below.
According to some embodiments, a kind of semiconductor device structure is provided.Semiconductor device structure includes：Substrate and it is located at
The first dielectric layer above substrate.Semiconductor device structure includes the second dielectric layer positioned at the first dielectric layer.First is situated between
Electric layer and the second dielectric layer are made from a variety of materials.Semiconductor device structure includes across the first dielectric layer and penetrating second
Conductivity through-hole structure in dielectric layer.Conductivity through-hole structure has first part and second part, first part and second part
It is located in the first dielectric layer and the second dielectric layer.First part has the first end towards substrate, and first end
The first width be more than second part the second width.
According to some embodiments, a kind of semiconductor device structure is provided.The structure of semiconductor devices includes substrate.Partly lead
Body device architecture includes the first dielectric layer being located above substrate.Semiconductor device structure includes being located at the first dielectric layer
Second dielectric layer.First dielectric layer and the second dielectric layer are made from a variety of materials.Semiconductor device structure includes across first
Dielectric layer and penetrate the conductivity through-hole structure in the second dielectric layer.Conductivity through-hole structure has first part and second part,
First part and second part are located in the first dielectric layer and the second dielectric layer.First width of first part is from second
Continuously increase on dielectric layer to the direction of substrate.
According in some embodiments, providing a kind of method being used to form semiconductor device structure.This method is included in
The first dielectric layer is formed above substrate.This method is included in the first dielectric layer and forms the second dielectric layer.First dielectric layer and
Second dielectric layer is made from a variety of materials, and this method is included in forms through-hole and in the second dielectric layer in the first dielectric layer
Middle formation hole.Through-hole is connected to hole.Through-hole has the second end opening and the second end opening.First end opening is towards substrate.Second
End opening is towards hole.First width of the first end opening is more than the second width of the second end opening.This method be included in through-hole and
Conductivity through-hole structure is formed in hole.
Foregoing has outlined the features of several embodiments so that each of the present invention may be better understood in those skilled in the art
A aspect.It should be appreciated by those skilled in the art that they easily can design or modify use using based on the present invention
In other process and structures for realizing identical with embodiment defined herein purpose and/or the identical advantage of realization.This field skill
Art personnel it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and without departing substantially from the present invention
Spirit and scope in the case of, herein they can make it is a variety of variation, replace and change.
In order to solve the problems in the prior art, according to some embodiments of the present invention, a kind of semiconductor devices is provided
Structure, including：Substrate；First dielectric layer is located above the substrate；Second dielectric layer is located at first dielectric layer,
Wherein, first dielectric layer and second dielectric layer are made from a variety of materials；And conductivity through-hole structure, it passes through described
It first dielectric layer and is penetrated into second dielectric layer, wherein the conductivity through-hole structure has first part and second
Part, the first part and the second part are located in first dielectric layer and second dielectric layer, described
First part has the first end towards the substrate, and the first width of the first end is more than the second part
The second width.
In above-mentioned semiconductor device structure, further include：Conductor wire is located in second dielectric layer and positioned at described
Above conductivity through-hole structure.
In above-mentioned semiconductor device structure, further include：Conductor wire is located in second dielectric layer and positioned at described
Above conductivity through-hole structure；Wherein, the second part of the conductivity through-hole structure is in direct contact with the conductor wire.
In above-mentioned semiconductor device structure, further include：Conductor wire is located in second dielectric layer and positioned at described
Above conductivity through-hole structure；Wherein, first width of the first end is less than the third width of the conductor wire.
In above-mentioned semiconductor device structure, wherein the first part also has the second of the neighbouring second part
End, and first width of the first end is more than the third width of the second end.
In above-mentioned semiconductor device structure, further include：Third dielectric layer is located at the substrate and first dielectric layer
Between；And conductor wire, it is located in the third dielectric layer and below the conductivity through-hole structure, wherein described to lead
Electric wire is electrically connected to the conductivity through-hole structure.
In above-mentioned semiconductor device structure, further include：Third dielectric layer is located at the substrate and first dielectric layer
Between；And conductor wire, it is located in the third dielectric layer and below the conductivity through-hole structure, wherein described to lead
Electric wire is electrically connected to the conductivity through-hole structure；Wherein, first width of the first end is less than the conductor wire
Third width.
In above-mentioned semiconductor device structure, wherein the conductivity through-hole structure also extends through second dielectric layer.
Other embodiments according to the present invention provide a kind of semiconductor device structure, including：Substrate；First dielectric
Layer is located above the substrate；Second dielectric layer is located at first dielectric layer, wherein first dielectric layer and institute
The second dielectric layer is stated to be made from a variety of materials；And conductivity through-hole structure, across first dielectric layer and it is penetrated into institute
It states in the second dielectric layer, wherein the conductivity through-hole structure has first part and second part, the first part and described
Second part is located in first dielectric layer and second dielectric layer, and the first width of the first part exists
Continuously increase from second dielectric layer to the direction of the substrate.
In above-mentioned semiconductor device structure, wherein the first part has first end and a second end, and described the
One end is towards the substrate, and the second end is adjacent to the second part, and the second width of the first end is big
In the third width of the second end.
In above-mentioned semiconductor device structure, further include：Adhesive layer is located at first dielectric layer and second dielectric
Between layer, wherein the conductivity through-hole structure also extends through the adhesive layer.
In above-mentioned semiconductor device structure, further include：Adhesive layer is located at first dielectric layer and second dielectric
Between layer, wherein the conductivity through-hole structure also extends through the adhesive layer；Wherein, the adhesive layer, first dielectric layer and
Second dielectric layer is made from a variety of materials.
In above-mentioned semiconductor device structure, wherein first dielectric layer includes silicon carbide or silicon nitride.
In above-mentioned semiconductor device structure, further include：Conductor wire is located in second dielectric layer and positioned at described
Above conductivity through-hole structure.
In above-mentioned semiconductor device structure, further include：Third dielectric layer is located at the substrate and first dielectric layer
Between；And conductive structure, it is located in the third dielectric layer and below the conductivity through-hole structure, wherein described
Conductive structure is electrically connected to the conductivity through-hole structure.
Other embodiment according to the present invention provides a kind of method being used to form semiconductor device structure, including：
It is rectangular at the first dielectric layer on substrate；The second dielectric layer is formed in first dielectric layer, wherein first dielectric
Layer and second dielectric layer are made from a variety of materials；Through-hole is formed in first dielectric layer and is situated between described second
Hole is formed in electric layer, wherein the through-hole is connected to the hole, and the through-hole has the first end opening and the second end opening, institute
The first end opening is stated towards the substrate, for second end opening towards the hole, the first width of first end opening is big
In the second width of second end opening；And form conductivity through-hole structure in the through-hole and the hole.
It is used to form in the method for semiconductor device structure above-mentioned, wherein the formation of the through-hole and the hole includes：
Mask layer is formed in second dielectric layer, wherein the mask layer has first of exposure second dielectric layer
The opening divided；And implement dry etching process with remove second dielectric layer the first part and be located at described first
The second part of first dielectric layer below point.
It is used to form in the method for semiconductor device structure above-mentioned, wherein the formation of the through-hole and the hole includes：
Mask layer is formed in second dielectric layer, wherein the mask layer has first of exposure second dielectric layer
The opening divided；And implement dry etching process with remove second dielectric layer the first part and be located at described first
The second part of first dielectric layer below point；Wherein, the dry etching process includes plasma etch process.
It is used to form in the method for semiconductor device structure above-mentioned, further includes：Formed the conductivity through-hole structure it
Before, form groove in second dielectric layer, wherein the groove is connected to the hole；And it is described conductive logical being formed
During pore structure, conductor wire is formed in the trench.
It is used to form in the method for semiconductor device structure above-mentioned, further includes：Formed the conductivity through-hole structure it
Before, form groove in second dielectric layer, wherein the groove is connected to the hole；And it is described conductive logical being formed
During pore structure, conductor wire is formed in the trench；Wherein, first width of first end opening is less than the ditch
The third width of slot.
Claims (20)
1. a kind of semiconductor device structure, including：
Substrate；
First dielectric layer is located above the substrate；
Second dielectric layer is located at first dielectric layer, wherein first dielectric layer and second dielectric layer be not by
Same material is made；And
Conductivity through-hole structure across first dielectric layer and is penetrated into second dielectric layer, wherein described conductive logical
Pore structure has first part and second part, and the first part and the second part are located at first dielectric layer
In second dielectric layer, the first part has the first end towards the substrate, and the first end
First width be more than the second part the second width, and the width of the first part from second dielectric layer to
Continuously increase on the direction of the substrate.
2. semiconductor device structure according to claim 1, further includes：
Conductor wire is located in second dielectric layer and above the conductivity through-hole structure.
3. semiconductor device structure according to claim 2, wherein the second part of the conductivity through-hole structure with
The conductor wire is in direct contact.
4. semiconductor device structure according to claim 2, wherein first width of the first end is less than institute
State the third width of conductor wire.
5. semiconductor device structure according to claim 1, wherein the first part also has described second neighbouring
The second end divided, and first width of the first end is more than the third width of the second end.
6. semiconductor device structure according to claim 1, further includes：
Third dielectric layer, between the substrate and first dielectric layer；And
Conductor wire is located in the third dielectric layer and below the conductivity through-hole structure, wherein the conductor wire electricity
It is connected to the conductivity through-hole structure.
7. semiconductor device structure according to claim 6, wherein first width of the first end is less than institute
State the third width of conductor wire.
8. semiconductor device structure according to claim 1, wherein the conductivity through-hole structure also extends through described second and is situated between
Electric layer.
9. a kind of semiconductor device structure, including：
Substrate；
First dielectric layer is located above the substrate；
Second dielectric layer is located at first dielectric layer, wherein first dielectric layer and second dielectric layer be not by
Same material is made；And
Conductivity through-hole structure across first dielectric layer and is penetrated into second dielectric layer, wherein described conductive logical
Pore structure has first part and second part, and the first part and the second part are located at first dielectric layer
In second dielectric layer, and the first width of the first part is from second dielectric layer to the side of the substrate
Continuously increase upwards.
10. semiconductor device structure according to claim 9, wherein the first part has first end and second
End, the first end is towards the substrate, and the second end is adjacent to the second part, and the first end
Second width is more than the third width of the second end.
11. semiconductor device structure according to claim 9, further includes：
Adhesive layer, between first dielectric layer and second dielectric layer, wherein the conductivity through-hole structure also extends through
The adhesive layer.
12. semiconductor device structure according to claim 11, wherein the adhesive layer, first dielectric layer and institute
The second dielectric layer is stated to be made from a variety of materials.
13. semiconductor device structure according to claim 9, wherein first dielectric layer includes silicon carbide or nitridation
Silicon.
14. semiconductor device structure according to claim 9, further includes：
Conductor wire is located in second dielectric layer and above the conductivity through-hole structure.
15. semiconductor device structure according to claim 9, further includes：
Third dielectric layer, between the substrate and first dielectric layer；And
Conductive structure is located in the third dielectric layer and below the conductivity through-hole structure, wherein the conductive knot
Structure is electrically connected to the conductivity through-hole structure.
16. a kind of method being used to form semiconductor device structure, including：
It is rectangular at the first dielectric layer on substrate；
Form the second dielectric layer in first dielectric layer, wherein first dielectric layer and second dielectric layer by
Different materials are made；
Through-hole is formed in first dielectric layer and forms hole in second dielectric layer, wherein the through-hole connection
To the hole, the through-hole has the first end opening and the second end opening, and first end opening is towards the substrate, and described the
For two end openings towards the hole, the first width of first end opening is more than the second width of second end opening, and
The width of the through-hole continuously increases from second dielectric layer to the direction of the substrate；And
Conductivity through-hole structure is formed in the through-hole and the hole.
17. the method according to claim 16 for being used to form semiconductor device structure, wherein the through-hole and the hole
Formation include：
Mask layer is formed in second dielectric layer, wherein the mask layer has the of exposure second dielectric layer
The opening of a part；And
Implement dry etching process to remove the first part of second dielectric layer and below the first part
The second part of first dielectric layer.
18. the method according to claim 17 for being used to form semiconductor device structure, wherein the dry etching process packet
Include plasma etch process.
19. the method according to claim 16 for being used to form semiconductor device structure, further includes：
Before forming the conductivity through-hole structure, groove is formed in second dielectric layer, wherein the groove is connected to
The hole；And
During forming the conductivity through-hole structure, conductor wire is formed in the trench.
20. the method according to claim 19 for being used to form semiconductor device structure, wherein first end opening
First width is less than the third width of the groove.
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| US14/659,170 US9892957B2 (en) | 2015-03-16 | 2015-03-16 | Semiconductor device structure and method for forming the same |
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