CN105990314A - Semiconductor structure and formation method - Google Patents
Semiconductor structure and formation method Download PDFInfo
- Publication number
- CN105990314A CN105990314A CN201510783049.3A CN201510783049A CN105990314A CN 105990314 A CN105990314 A CN 105990314A CN 201510783049 A CN201510783049 A CN 201510783049A CN 105990314 A CN105990314 A CN 105990314A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- hole
- layer
- conductivity
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor structue. The semiconductor member structure comprises a substrate and a first dielectric layer arranged above a substrate; the semiconductor structure comprises a second dielectric layer positioned above the first dielectric layer; the first dielectric layer and the second dielectric layer are made of different materials; the semiconductor structure comprises a conductive through hole structure passing through the first dielectric layer and the second dielectric layer; the conductive through hole structure has a first part and a second part; the first part and the second pare are positioned in the first dielectric layer and the second dielectric layer; the first part has a first end facing the substrate, and the first width of the first end is greater than second width of the second part.
Description
Cross-Reference to Related Applications
The application and that submit on March 16th, 2015 and entitled " SEMICONDUCTOR
DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME " be total to
Determining with generation and commonly assigned U.S. Patent Application No. 14658,525, entire contents is hereby incorporated by
As reference.
Technical field
The present invention relates to semiconductor device structure and forming method thereof.
Background technology
Semiconductor integrated circuit (IC) industry experienced by fast development.Technology in IC material and design
The progressive IC having created several generation.Often all there is the electricity less and more more complicated than previous generation IC for IC
Road.But, these progressive complexities adding processing and producing IC
In IC development process, functional density (that is, the quantity of interconnection devices on each chip area)
Generally increased and physical dimension (that is, the minimum assembly that uses manufacturing process to manufacture (or
Line)) the most reduce.Usual this scaled technique is relevant with reduction by improving production efficiency
Cost and bring benefit.
But, owing to part dimension continues to reduce, manufacturing process continues to become to be difficult to carry out.Therefore,
Forming more and more undersized reliable semiconductor device is a kind of challenge.
Summary of the invention
In order to solve the problems of the prior art, according to some embodiments of the present invention, it is provided that a kind of
Semiconductor device structure, including: substrate；First dielectric layer, is positioned at above described substrate；Second is situated between
Electric layer, is positioned at described first dielectric layer, wherein, described first dielectric layer and described second dielectric
Layer is made from a variety of materials；And conductivity through-hole structure, through described first dielectric layer and penetrate
In described second dielectric layer, wherein, described conductivity through-hole structure has Part I and Part II,
Described Part I and described Part II lay respectively at described first dielectric layer and described second dielectric layer
In, described Part I has the first end towards described substrate, and the of described first end
One width is more than the second width of described Part II.
Other embodiments according to the present invention, it is provided that a kind of semiconductor device structure, including: lining
The end；First dielectric layer, is positioned at above described substrate；Second dielectric layer, is positioned at described first dielectric layer
Top, wherein, described first dielectric layer and described second dielectric layer are made from a variety of materials；And
Conductivity through-hole structure, through described first dielectric layer and be penetrated in described second dielectric layer, wherein,
Described conductivity through-hole structure has Part I and Part II, described Part I and described second
Lay respectively in described first dielectric layer and described second dielectric layer, and the of described Part I
One width increases on the direction from described second dielectric layer to described substrate continuously.
Other embodiment according to the present invention, it is provided that a kind of for forming semiconductor device structure
Method, including: above substrate, form the first dielectric layer；The is formed at described first dielectric layer
Two dielectric layers, wherein, described first dielectric layer and described second dielectric layer are made from a variety of materials；
In described first dielectric layer, form through hole and in described second dielectric layer, form hole, wherein, institute
Stating through hole and be connected to described hole, described through hole has the first end opening and the second end opening, and described first
End opening towards described substrate, described second end opening towards described hole, the of described first end opening
One width is more than the second width of described second end opening；And formed in described through hole and described hole
Conductivity through-hole structure.
Accompanying drawing explanation
When reading in conjunction with the accompanying drawings, from each side being best understood by the present invention described in detail below
Face.It should be noted that according to the standard practices in industry, all parts not drawn on scale.It practice,
In order to clearly discuss, the size of all parts can at random increase or reduce.
Figure 1A to Fig. 1 H be according to some embodiments for the technique forming semiconductor device structure
The sectional view in each stage.
Fig. 2 A to Fig. 2 C be according to some embodiments respectively in Figure 1A to Figure 1B and Fig. 1 H
The top view of structure.
Fig. 3 is the sectional view of the semiconductor device structure according to some embodiments.
Fig. 4 is the sectional view of the semiconductor device structure according to some embodiments.
Detailed description of the invention
It is real for the difference of the different characteristic of the theme that realization is provided that disclosure below provides many
Execute example or example.The instantiation of assembly and layout is described below to simplify the present invention.Certainly, this
A little is only example, and is not intended to limit.Such as, in the following description, above second component or
Person is upper formed first component can include first component and second component directly contact the embodiment of formation,
And can also be included between first component and second component and can form extra parts, so that
The embodiment that can be not directly contacted with of first component and second component.Additionally, the present invention can be at each
Repeat reference numerals and/or character in example.This repeats to be for purposes of simplicity and clarity, and its
Itself do not indicate the relation between each embodiment discussed and/or configuration.
And, for ease of describing, can use such as herein " ... under ", " ... lower section ",
" bottom ", " ... on ", the space relative terms on " top " etc., to describe as shown in the figure
An element or parts and another (or other) element or the relation of parts.Except institute in figure
Outside the orientation shown, space relative terms is intended to include device different azimuth in use or operation.Dress
Put and can otherwise orient (90-degree rotation or in other orientation), and space used herein
Relative descriptors can be explained the most accordingly.Should be appreciated that before the process per se, period and
Extra operation can be provided afterwards, and for other embodiments of the method, can substitute or disappear
Except the certain operations described.
Figure 1A to Fig. 1 H is the work for forming semiconductor device structure 100 according to some embodiments
The sectional view in each stage of skill.Fig. 2 A to Fig. 2 C be according to some embodiments respectively at Figure 1A
The top view of the structure to Figure 1B and Fig. 1 H.Figure 1A to Figure 1B and Fig. 1 H is real according to some
Execute showing respectively along the hatching 1A-1A ' in Fig. 2 A to Fig. 2 C, 1B-1B ', 1H-1H ' of example
The sectional view of the structure intercepted.
As shown in Figure 1A, according to some embodiments, it is provided that substrate 110.Substrate 110 can be such as
The semiconductor crystal wafer of Silicon Wafer.Alternatively or additionally, substrate 110 can include elemental semiconductor
Material, compound semiconductor materials and/or alloy semiconductor material.
The example of elemental semiconductors can be but not limited to crystalline silicon, polysilicon, non-crystalline silicon, germanium
And/or diamond.The example of compound semiconductor materials can be but not limited to carborundum, GaAs, phosphorus
Change gallium, indium phosphide, indium arsenide and/or indium antimonide.The example of alloy semiconductor material can be but not limit
In SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP.
As shown in Figure 1A, according to some embodiments, Semiconductor substrate 110 forms isolation structure
111.According to some embodiments, isolation structure 111 is around the device region of Semiconductor substrate 110.According to
Some embodiments, isolation structure 111 is configured to limit and electrically insulate shape in Semiconductor substrate 110
The various components (not shown) become.
The example of element can include but not limited to transistor, diode and/or other elements being suitable for.
The example of transistor can include but not limited to mos field effect transistor
(MOSFET), complementary metal oxide semiconductors (CMOS) (CMOS) transistor, bipolar junction transistor
(BJT), high voltage transistor, high frequency transistor, p-channel and/or n-channel field-effect transistor
(PFET/NFET) etc..Implement such as to deposit, etch, inject, photoetching, annealing and/or other fit
The kinds of processes of technique to form components.
As shown in Figure 1A, according to some embodiments, at Semiconductor substrate 110 and isolation structure 111
Top forms dielectric layer 120.According to some embodiments, dielectric layer 120 includes dielectric material.Medium
The example of material can include but not limited to oxide, SiO2, boron phosphorus silicate glass (BPSG),
Spin-coating glass (SOG), unadulterated silicate glass (USG), fluorinated silicate glass (FSG),
The tetraethyl orthosilicate (PETEOS) of high-density plasma (HDP) oxide or plasma enhancing.
Dielectric layer 120 can include by such as low-k or extremely low dielectric constant (ELK) material
The multilamellar made of multiple dielectric material.Chemical vapor deposition (CVD), physical vapor can be passed through
Deposition (PVD), ald (ALD), spin coating or another technique being suitable for form dielectric layer
120。
As shown in Figure 1A, according to some embodiments, dielectric layer 120 forms groove 122.According to
Some embodiments, use photoetching process and etch process to form groove 122.As shown in Figure 1A, according to
Some embodiments, form barrier layer 132 in groove 122.According to some embodiments, barrier layer 132
The conformally inwall 122a and bottom surface 122b of covering groove 122.According to some embodiments, barrier layer
132 metal materials being configured to prevent being formed in groove 122 diffuse in dielectric layer 120.Stop
Layer 132 includes tantalum or another suitable material.According to some embodiments, use physical vapor deposition work
Skill forms barrier layer 132.
As shown in Figure 1A, according to some embodiments, above barrier layer 132, form crystal seed layer 134.
Crystal seed layer 134 includes copper (Cu) and manganese (Mn) or other suitable materials.According to some embodiments,
Physical vapor deposition process is used to form crystal seed layer 134.As shown in Figure 1A, according to some embodiments,
Conductor wire 136 is formed in groove 122 and above crystal seed layer 134.Conductor wire 136 include aluminum (Al),
Copper (Cu) or another suitable material.According to some embodiments, depositing process is used to form conductor wire 136.
As shown in Figure 1A, according to some embodiments, at dielectric layer 120, barrier layer 132, crystal seed layer
134 and conductor wire 136 above formed dielectric layer 140.According to some embodiments, dielectric layer 140 configures
For preventing the metal material of conductor wire 136 to be diffused in the dielectric layer of the side of being formed thereon.
According to some embodiments, dielectric layer 140 includes dielectric material.Dielectric layer 140 include carborundum,
Silicon nitride or another suitable dielectric material.According to some embodiments, dielectric layer 120 and 140 is not by
Same material is made.Dielectric layer 140 can include the multilamellar being made up of different dielectric materials.Permissible
By chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD),
Spin coating or another technique being suitable for form dielectric layer 140.
As shown in Figure 1A, according to some embodiments, above dielectric layer 140, form adhesive layer 150.
Adhesive layer 150 is configured to another dielectric layer that dielectric layer 140 adheres to be positioned on dielectric layer 140.
Adhesive layer 150 includes tetraethyl orthosilicate (TEOS) or another suitable material.At some, other are implemented
In example, it is formed without adhesive layer 150.
As shown in Figure 1A, according to some embodiments, above adhesive layer 150, form dielectric layer 160.
According to some embodiments, dielectric layer 160 and 140 is made from a variety of materials, so that dielectric layer
160 and 140 can have etching selectivity in etch process subsequently.According to some embodiments,
Dielectric layer 160 and 140 and adhesive layer 150 be made from a variety of materials.
According to some embodiments, dielectric layer 160 includes dielectric material.The example of dielectric material can wrap
Include but be not limited to oxide, SiO2, boron phosphorus silicate glass (BPSG), spin-coating glass (SOG),
Unadulterated silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma
The tetraethyl orthosilicate (PETEOS) of body (HDP) oxide or plasma enhancing.
Dielectric layer 160 can include by such as low-k or extremely low dielectric constant (ELK) material
The multilamellar made of multiple dielectric material.Chemical vapor deposition (CVD), physical vapor can be passed through
Deposition (PVD), ald (ALD), spin coating or another technique being suitable for form dielectric layer
120。
As shown in Figure 1A, according to some embodiments, above dielectric layer 160, form etching stopping layer
170.Etching stopping layer 170 includes silicon nitride, silicon oxide, or other suitable materials.According to some
Embodiment, uses chemical vapor deposition process to form etching stopping layer 170.
As shown in Figure 1A, according to some embodiments, above dielectric layer 160, form etching stopping layer
170.Etching stopping layer 170 includes silicon nitride, silicon oxide, or other suitable materials.According to some
Embodiment, uses chemical vapor deposition process to form etching stopping layer 170.
As shown in Figure 1A, according to some embodiments, above etching stopping layer 170, form mask layer
180.In certain embodiments, mask layer 180 includes oxide, such as silicon oxide.Implement at some
In example, mask layer 180 includes silicon nitride, titanium nitride, other material being suitable for or combinations thereof.
In certain embodiments, chemical vapor deposition process is used to form mask layer 18.
As shown in Figure 1A and Fig. 2 A, according to some embodiments, formed above mask layer 180 and firmly cover
Mold layer 190.According to some embodiments, hard mask layer 190 has groove 192 and 194.According to some
Embodiment, groove 192 and 194 exposes the part of mask layer 180.
The example of the material of hard mask layer 190 includes but not limited to silicon oxide, silicon nitride (such as, Si3N4)、
SiON, SiC, SiOC or combinations thereof.Chemical vapor deposition (CVD), physics can be passed through
Gas deposition (PVD), ald (ALD), spin coating or other technique being suitable for are formed firmly
Mask layer 190.In certain embodiments, mask layer 180 and hard mask layer 190 are by different materials
Material is made, so that mask layer 180 and hard mask layer 190 have in etch process subsequently
Etching selectivity.
As shown in figs. ib and 2b, according to some embodiments, cover layer 210 is formed at hard mask layer 190
Top and fill to groove 192 and 194.Cover layer 210 is by polymeric material or another is suitable
Material make.Cover layer 210 is formed by coating process, CVD technique or another suitable technique.
As shown in figs. ib and 2b, according to some embodiments, above cover layer 210, form intermediate layer
220.In certain embodiments, intermediate layer 220 is by material (such as, silicon-containing polymer material)
Make.In certain embodiments, mask layer 180, hard mask layer 190, cover layer 210 and centre
Layer 220 is made from a variety of materials, so that have in they etch process of implementing later
There is etching selectivity.Intermediate layer 220 is formed by coating process, CVD technique or another suitable technique.
As shown in figs. ib and 2b, according to some embodiments, above intermediate layer 220, form photoresist
Layer 230.According to some embodiments, photoresist layer 230 has the part exposing intermediate layer 220
Opening 232.According to some embodiments, photoresist layer 230 is made up of Other substrate materials.Such as,
Photoresist layer 230 is formed by coating process and photoetching process.
As shown in Figure 1 C, according to some embodiments, remove intermediate layer 220 by opening 232 and cover
Layer 210 be positioned at the part below opening 232.According to some embodiments, after removing technique, shape
Become the opening 212 through intermediate layer 220 and cover layer 210.According to some embodiments, opening 212
It is connected to opening 232 and exposes the part of mask layer 180.According to some embodiments, opening 212
It is arranged in groove 194.According to some embodiments, remove technique and include dry etching process.
As shown in figure ip, according to some embodiments, remove intermediate layer 220 and photoresist layer 230.Root
According to some embodiments, remove technique and include dry etching process or wet etching process.Hereafter, according to some
Embodiment, removes the part of mask layer 180 by opening 212.According to some embodiments, removing
After technique, in mask layer 180, form opening 182 and opening 182 exposes etching stopping layer 170
Part.
According to some embodiments, remove technique and include dry etching process.According to some embodiments, dry corrosion
Carving technology includes plasma etch process.According to some embodiments, from about 1 millitorr to about 100
Under pressure in the range of millitorr and use power enforcement from about 100W to about 1500W etc. from
Daughter etch process.According to some embodiments, at a temperature of in the range of about 10 DEG C to about 70 DEG C
Implement this plasma etch process.According to some embodiments, plasma etch process uses and includes
CF4、H2、N2、C4F8、O2And/or CH2F2Gas.
As referring to figure 1e, according to some embodiments, remove cover layer 210.According to some embodiments,
Remove technique and include dry etching process.According to some embodiments, dry etching process includes that plasma loses
Carving technology.According to some embodiments, under the pressure in the range of about 1 millitorr to about 100 millitorrs
And use from about 100W to the power of about 1500W enforcement plasma etch process.According to one
A little embodiments, implement this plasma etching work at a temperature of in the range of about 10 DEG C to about 70 DEG C
Skill.According to some embodiments, plasma etch process uses and includes CO2、C4H8、CF4、O2、
N2And/or the gas of Ar.
As shown in fig. 1f, according to some embodiments, implement etch process and be positioned at groove 192 times to remove
Side mask layer 180, etching stopping layer 170, the part of dielectric layer 160 and be positioned at groove 194 times
Mask layer 180, etching stopping layer 170, dielectric layer 160, adhesive layer 150 and the dielectric layer 140 of side
Part.
After the etch process, according to some embodiments, dielectric layer 160 forms groove 162 and 164
And hole 166, and in dielectric layer 140, form through hole 142.Hole 166 is positioned at below groove 164
And it is connected to groove 164 and through hole 142.In certain embodiments, hole 166 further passs through viscous
Close layer 150.According to some embodiments, through hole 142 exposes the part of conductor wire 136.According to some
Embodiment, through hole 142 exposes the part of crystal seed layer 134 further.
According to some embodiments, owing to dielectric layer 160 and 140 is made from a variety of materials, because of
This dielectric layer 160 and 140 can have etching selectivity in the etch process.According to some embodiments,
Through hole 142 has the first end opening 142a and the second end opening 142b.According to some embodiments, first
End opening 142a is towards substrate 110.According to some embodiments, the second end opening 142b is towards hole 166.
According to some embodiments, the width W1 of the first end opening 142a is more than the second end opening 142b
Width W2.According to some embodiments, the width W1 of the first end opening 142a is more than hole 166
Width W3.According to some embodiments, the width W1 of the first end opening 142a is less than groove 164
Width WT。
According to some embodiments, etch process includes dry etching process.According to some embodiments, dry corrosion
Carving technology includes plasma etch process.According to some embodiments, from about 1 millitorr to about 100
Under pressure in the range of millitorr and use power enforcement from about 100W to about 1500W etc. from
Daughter etch process.According to some embodiments, at a temperature of in the range of about 10 DEG C to about 70 DEG C
Implement this plasma etch process.According to some embodiments, plasma etch process uses and includes
C4F8、CF4、O2、N2And/or the gas of Ar.
As shown in Figure 1 G, according to some embodiments, in groove 162 and 164, hole 166 and through hole
Barrier layer 242 is formed in 142.According to some embodiments, conformally covering groove 162, barrier layer 242
Inwall 162a, 164a, 166a and 142c and groove 162 with 164, hole 166 and through hole 142
With 164 bottom surface 162b and 164b.
According to some embodiments, barrier layer 242 is configured to prevent in groove 162 and 164, hole 166
With the metal material formed in through hole 142 diffuse to dielectric layer 140 and 160 and adhesive layer 150 in.
Barrier layer 242 includes tantalum or another suitable material.According to some embodiments, physical vapor is used to sink
Long-pending technique forms barrier layer 242.
As shown in Figure 1 G, according to some embodiments, above barrier layer 242, form crystal seed layer 244.
Crystal seed layer 244 includes copper (Cu) and manganese (Mn) or other suitable materials.According to some embodiments,
Physical vapor deposition process is used to form crystal seed layer 244.
As shown in Figure 1 G, according to some embodiments, at groove 162 and 164, hole 166 and through hole 142
In and above crystal seed layer 244 formed conductive layer 246.Conductive layer 246 includes aluminum (Al), copper
Or another suitable material (Cu).According to some embodiments, depositing process is used to form conductive layer 246.
As shown in Fig. 1 H and Fig. 2 C, according to some embodiments, remove be positioned at groove 162 and 164,
Barrier layer 242 outside hole 166 and through hole 142, mask layer 180 and hard mask layer 190, crystal seed
Layer 244 and conductive layer 246.According to some embodiments, remove technique and include flatening process, such as
CMP process.
According to some embodiments, the conductive layer 246 being retained in groove 162 forms conductor wire 252.
According to some embodiments, the conductive layer 246 being retained in groove 164 forms conductor wire 254.One
In a little embodiments, the end face 252a of conductor wire 252, the end face 254a of conductor wire 254 and dielectric layer
The end face 168 of 160 is coplanar with each other.According to some embodiments, it is retained in hole 166 and through hole 142
Conductive layer 246 form conductivity through-hole structure 260.According to some embodiments, conductivity through-hole structure 260
It it is overall structure.Be formed as whole according to some embodiments, conductor wire 254 and conductivity through-hole structure 260
Body structure.
According to some embodiments, conductivity through-hole structure 260 is through dielectric layer 140 and penetrates dielectric layer
In 160.According to some embodiments, conductivity through-hole structure 260 further passs through dielectric layer 140 and 160
Between adhesive layer 150.According to some embodiments, conductivity through-hole structure 260 has Part I 262
With Part II 264, and Part I 262 and Part II 264 lay respectively at dielectric layer 140
With in dielectric layer 160.In certain embodiments, the width W of Part I 262 is from dielectric layer 160
Increase continuously to the direction A of substrate 110.
According to some embodiments, Part I 262 has first end 262a and the second end 262b.
According to some embodiments, the second end 262b is between first end 262a and Part II 264.
According to some embodiments, the second end 262b is adjacent to Part II 264.In certain embodiments,
The width W4 of one end 262a is more than the width W5 of the second end 262b.
According to some embodiments, conductor wire 254 is positioned in dielectric layer 160 and at conductivity through-hole structure
Above in the of 260.According to some embodiments, the Part II 264 of conductivity through-hole structure 260 and conductor wire
254 directly contact.According to some embodiments, the width W4 of first end 262a is less than conductor wire 254
Width W6.Owing to first end 262a is narrower than conductor wire 254, therefore, reduce first end
The probability that 262a is short-circuit with other conductive structures in dielectric layer 140 and 120.
According to some embodiments, conductor wire 136 is positioned at below conductivity through-hole structure 260 and electrically connects
To conductivity through-hole structure 260.According to some embodiments, the width W4 of first end 262a is less than leading
The width W8 of electric wire 136.Owing to first end 262a is narrower than conductor wire 136, therefore, reduce
The probability that first end 262a is short-circuit with other conductive structures in dielectric layer 140 and 120.
According to some embodiments, the width W4 of first end 262a is more than the width of Part II 264
W7.That is, conductivity through-hole structure 260 has the end (that is, first end 262a) of expansion.Therefore,
The conductivity through-hole structure 260 increasing the end 262a by having expansion is connected to the general of conductor wire 136
Rate.Result improves yield.Additionally, the end 262a expanded can increase conductivity through-hole structure 260
And the connection area between conductor wire 136, it reduce conductivity through-hole structure 260 and conductor wire 136
Between contact resistance.
In certain embodiments, the difference between width W4 and width W7 from about 2nm to about
In the range of 10nm.In certain embodiments, the ratio of width W4 and width W7 is from about 1.2
In the range of about 1.4.
As shown in fig. 1h, according to some embodiments, inwall 142c is planar inner wall.At some other
In embodiment, inwall 142c is curved inner wall (as shown in Figure 3).As shown in fig. 1h, according to one
A little embodiments, conductor wire 252 and 254 and conductivity through-hole structure 260 are formed at same dielectric layer 160
In.In some other embodiments, according to some embodiments, conductor wire 252 and 254 and conduction
Through-hole structure 260 is formed in different dielectric layers 410 and 160 (as shown in Figure 4).Such as Fig. 4
Shown in, according to some embodiments, conductivity through-hole structure 260 is through dielectric layer 160, adhesive layer 150
With dielectric layer 140.
According to some embodiments, it is provided that semiconductor device structure and forming method thereof.Method (is used for
Form semiconductor device structure) define the conductivity through-hole structure of the end with expansion.Therefore, increase
The conductive structure that the conductivity through-hole structure of the big end by having expansion is connected to be disposed below general
Rate.As a result, improve yield.Additionally, the end expanded can reduce conductivity through-hole structure and be positioned at
The contact resistance between conductive structure below.
According to some embodiments, it is provided that a kind of semiconductor device structure.Semiconductor device structure includes:
Substrate and be positioned at the first dielectric layer above substrate.Semiconductor device structure includes being positioned at the first dielectric layer
Second dielectric layer of top.First dielectric layer and the second dielectric layer are made from a variety of materials.Quasiconductor
Device architecture includes through the first dielectric layer and penetrates the conductivity through-hole structure in the second dielectric layer.Lead
Electric through-hole structure has Part I and Part II, Part I and Part II and lays respectively at first
In dielectric layer and the second dielectric layer.Part I has the first end towards substrate, and the first end
First width in portion is more than the second width of Part II.
According to some embodiments, it is provided that a kind of semiconductor device structure.The structure bag of semiconductor device
Include substrate.Semiconductor device structure includes the first dielectric layer being positioned at above substrate.Junction of semiconductor device
Structure includes the second dielectric layer being positioned at the first dielectric layer.First dielectric layer and the second dielectric layer be not by
Same material is made.Semiconductor device structure includes through the first dielectric layer and penetrates the second dielectric layer
Interior conductivity through-hole structure.Conductivity through-hole structure has Part I and a Part II, Part I and
Part II lays respectively in the first dielectric layer and the second dielectric layer.First width of Part I from
Second dielectric layer increases to the direction of substrate continuously.
According in some embodiments, it is provided that a kind of method for forming semiconductor device structure.Should
Method is included in above substrate and forms the first dielectric layer.The method is included in the first dielectric layer and is formed
Second dielectric layer.First dielectric layer and the second dielectric layer are made from a variety of materials, and the method is included in
In the first dielectric layer, form through hole and in the second dielectric layer, form hole.Through hole is connected to hole.Logical
Hole has the second end opening and the second end opening.First end opening is towards substrate.Second end opening towards
Hole.First width of the first end opening is more than the second width of the second end opening.The method is included in logical
Hole and hole are formed conductivity through-hole structure.
Foregoing has outlined the feature of some embodiments so that those skilled in the art may be better understood
Various aspects of the invention.It should be appreciated by those skilled in the art that they can readily use this
Design based on bright or revise for realize the purpose identical with embodiment defined herein and/or
Realize other techniques and the structure of identical advantage.Those skilled in the art are it should also be appreciated that this etc.
Isostructure is without departing from the spirit and scope of the present invention, and without departing substantially from the spirit and scope of the present invention
In the case of, at this, they can make multiple change, replace and change.
In order to solve the problems of the prior art, according to some embodiments of the present invention, it is provided that a kind of
Semiconductor device structure, including: substrate；First dielectric layer, is positioned at above described substrate；Second is situated between
Electric layer, is positioned at described first dielectric layer, wherein, described first dielectric layer and described second dielectric
Layer is made from a variety of materials；And conductivity through-hole structure, through described first dielectric layer and penetrate
In described second dielectric layer, wherein, described conductivity through-hole structure has Part I and Part II,
Described Part I and described Part II lay respectively at described first dielectric layer and described second dielectric layer
In, described Part I has the first end towards described substrate, and the of described first end
One width is more than the second width of described Part II.
In above-mentioned semiconductor device structure, also include: conductor wire, be positioned in described second dielectric layer
And it is positioned at above described conductivity through-hole structure.
In above-mentioned semiconductor device structure, also include: conductor wire, be positioned in described second dielectric layer
And it is positioned at above described conductivity through-hole structure；Wherein, described second of described conductivity through-hole structure
Divide and directly contact with described conductor wire.
In above-mentioned semiconductor device structure, also include: conductor wire, be positioned in described second dielectric layer
And it is positioned at above described conductivity through-hole structure；Wherein, described first width of described first end is little
The 3rd width in described conductor wire.
In above-mentioned semiconductor device structure, wherein, described Part I also has neighbouring described second
The second end of part, and described first width of described first end is more than described the second end
3rd width.
In above-mentioned semiconductor device structure, also include: the 3rd dielectric layer, be positioned at described substrate and institute
State between the first dielectric layer；And conductor wire, be positioned in described 3rd dielectric layer and be positioned at described in lead
Below electric through-hole structure, wherein, described conductor wire is electrically connected to described conductivity through-hole structure.
In above-mentioned semiconductor device structure, also include: the 3rd dielectric layer, be positioned at described substrate and institute
State between the first dielectric layer；And conductor wire, be positioned in described 3rd dielectric layer and be positioned at described in lead
Below electric through-hole structure, wherein, described conductor wire is electrically connected to described conductivity through-hole structure；Wherein,
Described first width of described first end is less than the 3rd width of described conductor wire.
In above-mentioned semiconductor device structure, wherein, described conductivity through-hole structure also extends through described second
Dielectric layer.
Other embodiments according to the present invention, it is provided that a kind of semiconductor device structure, including: lining
The end；First dielectric layer, is positioned at above described substrate；Second dielectric layer, is positioned at described first dielectric layer
Top, wherein, described first dielectric layer and described second dielectric layer are made from a variety of materials；And
Conductivity through-hole structure, through described first dielectric layer and be penetrated in described second dielectric layer, wherein,
Described conductivity through-hole structure has Part I and Part II, described Part I and described second
Lay respectively in described first dielectric layer and described second dielectric layer, and the of described Part I
One width increases on the direction from described second dielectric layer to described substrate continuously.
In above-mentioned semiconductor device structure, wherein, described Part I has first end and second
End, described first end towards described substrate, described the second end adjacent to described Part II, and
And the second width of described first end is more than the 3rd width of described the second end.
In above-mentioned semiconductor device structure, also include: adhesive layer, be positioned at described first dielectric layer and
Between described second dielectric layer, wherein, described conductivity through-hole structure also extends through described adhesive layer.
In above-mentioned semiconductor device structure, also include: adhesive layer, be positioned at described first dielectric layer and
Between described second dielectric layer, wherein, described conductivity through-hole structure also extends through described adhesive layer；Wherein,
Described adhesive layer, described first dielectric layer and described second dielectric layer are all made from a variety of materials.
In above-mentioned semiconductor device structure, wherein, described first dielectric layer includes carborundum or nitridation
Silicon.
In above-mentioned semiconductor device structure, also include: conductor wire, be positioned in described second dielectric layer
And it is positioned at above described conductivity through-hole structure.
In above-mentioned semiconductor device structure, also include: the 3rd dielectric layer, be positioned at described substrate and institute
State between the first dielectric layer；And conductive structure, it is positioned in described 3rd dielectric layer and is positioned at described
Below conductivity through-hole structure, wherein, described conductive structure is electrically connected to described conductivity through-hole structure.
Other embodiment according to the present invention, it is provided that a kind of for forming semiconductor device structure
Method, including: above substrate, form the first dielectric layer；The is formed at described first dielectric layer
Two dielectric layers, wherein, described first dielectric layer and described second dielectric layer are made from a variety of materials；
In described first dielectric layer, form through hole and in described second dielectric layer, form hole, wherein, institute
Stating through hole and be connected to described hole, described through hole has the first end opening and the second end opening, and described first
End opening towards described substrate, described second end opening towards described hole, the of described first end opening
One width is more than the second width of described second end opening；And formed in described through hole and described hole
Conductivity through-hole structure.
In the above-mentioned method for forming semiconductor device structure, wherein, described through hole and described hole
Formation include: described second dielectric layer formed mask layer, wherein, described mask layer has
Expose the opening of the Part I of described second dielectric layer；And it is described to remove to implement dry etching process
The described Part I of the second dielectric layer and described first dielectric layer being positioned at below described Part I
Part II.
In the above-mentioned method for forming semiconductor device structure, wherein, described through hole and described hole
Formation include: described second dielectric layer formed mask layer, wherein, described mask layer has
Expose the opening of the Part I of described second dielectric layer；And it is described to remove to implement dry etching process
The described Part I of the second dielectric layer and described first dielectric layer being positioned at below described Part I
Part II；Wherein, described dry etching process includes plasma etch process.
In the above-mentioned method for forming semiconductor device structure, also include: forming described conduction
Before through-hole structure, forming groove in described second dielectric layer, wherein, described groove is connected to institute
State hole；And during forming described conductivity through-hole structure, form conductor wire in the trench.
In the above-mentioned method for forming semiconductor device structure, also include: forming described conduction
Before through-hole structure, forming groove in described second dielectric layer, wherein, described groove is connected to institute
State hole；And during forming described conductivity through-hole structure, form conductor wire in the trench；Its
In, described first width of described first end opening is less than the 3rd width of described groove.
Claims (10)
1. a semiconductor device structure, including:
Substrate；
First dielectric layer, is positioned at above described substrate；
Second dielectric layer, is positioned at described first dielectric layer, wherein, described first dielectric layer and institute
State the second dielectric layer to be made from a variety of materials；And
Conductivity through-hole structure, through described first dielectric layer and be penetrated in described second dielectric layer,
Wherein, described conductivity through-hole structure has Part I and a Part II, described Part I and described
Part II lays respectively in described first dielectric layer and described second dielectric layer, and described Part I has
There is the first end towards described substrate, and the first width of described first end is more than described second
Second width of part.
Semiconductor device structure the most according to claim 1, also includes:
Conductor wire, is positioned in described second dielectric layer and is positioned at above described conductivity through-hole structure.
Semiconductor device structure the most according to claim 2, wherein, described conductivity through-hole structure
Described Part II directly contact with described conductor wire.
Semiconductor device structure the most according to claim 2, wherein, the institute of described first end
State first width the 3rd width less than described conductor wire.
Semiconductor device structure the most according to claim 1, wherein, described Part I also has
There is the second end of neighbouring described Part II, and described first width of described first end is more than
3rd width of described the second end.
Semiconductor device structure the most according to claim 1, also includes:
3rd dielectric layer, between described substrate and described first dielectric layer；And
Conductor wire, is positioned in described 3rd dielectric layer and is positioned at below described conductivity through-hole structure, its
In, described conductor wire is electrically connected to described conductivity through-hole structure.
Semiconductor device structure the most according to claim 6, wherein, the institute of described first end
State first width the 3rd width less than described conductor wire.
Semiconductor device structure the most according to claim 1, wherein, described conductivity through-hole structure
Also extend through described second dielectric layer.
9. a semiconductor device structure, including:
Substrate；
First dielectric layer, is positioned at above described substrate；
Second dielectric layer, is positioned at described first dielectric layer, wherein, described first dielectric layer and institute
State the second dielectric layer to be made from a variety of materials；And
Conductivity through-hole structure, through described first dielectric layer and be penetrated in described second dielectric layer,
Wherein, described conductivity through-hole structure has Part I and a Part II, described Part I and described
Part II lays respectively in described first dielectric layer and described second dielectric layer, and described first
The first width divided increases on the direction from described second dielectric layer to described substrate continuously.
10. for the method forming semiconductor device structure, including:
The first dielectric layer is formed above substrate；
The second dielectric layer, wherein, described first dielectric layer and institute is formed at described first dielectric layer
State the second dielectric layer to be made from a variety of materials；
In described first dielectric layer, form through hole and in described second dielectric layer, form hole, wherein,
Described through hole is connected to described hole, and described through hole has the first end opening and the second end opening, and described
One end open towards described substrate, described second end opening towards described hole, described first end opening
First width is more than the second width of described second end opening；And
Conductivity through-hole structure is formed in described through hole and described hole.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/659,170 | 2015-03-16 | ||
| US14/659,170 US9892957B2 (en) | 2015-03-16 | 2015-03-16 | Semiconductor device structure and method for forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990314A true CN105990314A (en) | 2016-10-05 |
| CN105990314B CN105990314B (en) | 2018-10-26 |
Family
ID=57042620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510783049.3A Active CN105990314B (en) | 2015-03-16 | 2015-11-16 | Semiconductor device structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990314B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080026564A1 (en) * | 2006-07-31 | 2008-01-31 | Kai Frohberg | Method of forming an electrically conductive line in an integrated circuit |
| US20120211883A1 (en) * | 2011-02-17 | 2012-08-23 | Uehling Trent S | Anchored conductive via and method for forming |
| US20130280879A1 (en) * | 2012-04-20 | 2013-10-24 | Infineon Technologies Austria Ag | Method for Producing a Conductor Line |
| CN104103623A (en) * | 2013-04-02 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and formation method thereof |
-
2015
- 2015-11-16 CN CN201510783049.3A patent/CN105990314B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080026564A1 (en) * | 2006-07-31 | 2008-01-31 | Kai Frohberg | Method of forming an electrically conductive line in an integrated circuit |
| US20120211883A1 (en) * | 2011-02-17 | 2012-08-23 | Uehling Trent S | Anchored conductive via and method for forming |
| US20130280879A1 (en) * | 2012-04-20 | 2013-10-24 | Infineon Technologies Austria Ag | Method for Producing a Conductor Line |
| CN104103623A (en) * | 2013-04-02 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and formation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990314B (en) | 2018-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI764411B (en) | Packaged semiconductor devices and methods of forming the same | |
| CN103633042B (en) | Semiconductor device package and methods of packaging thereof | |
| US10825737B2 (en) | Prevention of contact bottom void in semiconductor fabrication | |
| TWI579969B (en) | Semiconductor device structure and method forming the same | |
| CN107546203A (en) | Semiconductor devices and its manufacture method | |
| CN106469717A (en) | Three-dimensional integrated circuit structure and its manufacture method | |
| CN105870102A (en) | Damascene structure and formation method of damascene structure | |
| US11217482B2 (en) | Method for forming semiconductor device with resistive element | |
| TWI749986B (en) | Semiconductor device and methods of forming same | |
| TWI646643B (en) | Contact scheme for landing at different levels of contact areas | |
| TW201729379A (en) | Structure and formation method of interconnect structure of semiconductor device | |
| US10002933B1 (en) | Semiconductor device structure with cap layer with top and bottom portions over gate electrode | |
| TWI817408B (en) | Semiconductor device structure and method of forming the same | |
| US11694923B2 (en) | Method for preparing semiconductor device with air spacer | |
| CN105990314A (en) | Semiconductor structure and formation method | |
| US9576847B2 (en) | Method for forming integrated circuit structure with thinned contact | |
| US20230352433A1 (en) | Semiconductor device structure with composite bottle-shaped through silicon via and method for prepriang the same | |
| US10985051B2 (en) | Semiconductor device with air spacer and method for forming the same | |
| US20240274485A1 (en) | Heat dissipation in semiconductor devices | |
| US10840136B1 (en) | Method for preparing conductive via | |
| CN118116973A (en) | Semiconductor device and method for manufacturing the same | |
| TW202433694A (en) | Semiconductor device and method for forming the same | |
| CN106206414A (en) | For the method forming semiconductor device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |