CN105990094A - Preparation method of PSM alignment mark structure - Google Patents
Preparation method of PSM alignment mark structure Download PDFInfo
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- CN105990094A CN105990094A CN201510061273.1A CN201510061273A CN105990094A CN 105990094 A CN105990094 A CN 105990094A CN 201510061273 A CN201510061273 A CN 201510061273A CN 105990094 A CN105990094 A CN 105990094A
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Abstract
The invention relates to the technical field of semiconductor device manufacturing, and specifically relates to a preparation method of a PSM (Phase Shift Mask) alignment mark structure. The preparation method of a PSM alignment mark structure comprises the steps: setting a sample gate above a shallow trench isolation structure to prepare mask layer stacking on the top of the sample gate; and in the technology of a high dielectric constant metal gate, as the shallow trench isolation structure and the step height of an active region enable part of the mask layer stacking to be maintained, and as the residual mask layer stacking on the sample gate is used to guarantee that a second sample gate is free from damaging during the polishing process, the thickness of the sample gate can be completely maintained and then the alignment quality between a contact hole and the metal gate can be improved. The preparation method of a PSM alignment mark structure has the advantages of being simple and convenient in the technology, being higher in the compatibility compared with a traditional technology, and being high in practicality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of PSM alignment mark
The preparation method of structure.
Background technology
With the development of technology, semiconductor technology has infiltrated into each neck in life
Territory, such as space flight, Medical treatment device are guarded against, mobile communication all be unable to do without the chip prepared by semiconductor.
A lot of in the past chips were all to use silica as gate dielectric, but from 65nm
Start, owing to technology node is very little, it is impossible to allow gate dielectric continue shortening thinning, with
When constantly reducing with transistor size, source electrode and drain electrode between distance also less and less,
And then easily cause short-channel effect.Therefore, for the problems referred to above, those skilled in the art's warp
Unremitting research, HKMG (High-K Metal Gate, high dielectric metal gate) technique is developed
Out.It is the gate dielectric using one to have high-k (or claiming high K), and
Using metal material to be used as grid, the device using HKMG technique to prepare is compared more traditional
It for device, is greatly reduced leakage current, effectively improve driving electric current, therefore simultaneously
HKMG has become the mainstream technology that current high-performance transistor is used.
Particularly in the HKMG technique of 28nm, as it is shown in figure 1, contact hole alignment
The thickness of quality and metal gate (Metal Gate is called for short MG) has very strong correlation,
And contact hole alignment metal gate, metal gate phase shift mask (phase shift mask is called for short PSM)
The thickness of mark become affect a vital factor of wafer quality vital because of
Element, in FIG, abscissa represents metal gate thickness (MG thickness), and ordinate represents
Wafer quality (wafer quality), the region representation bit line performance (BL of 1 indication
performance).At present, existing PSM alignment mark through ILD CMP and
After DPRM and AL-CMP, its thickness is greatly reduced, and then affects contact hole and metal
The alignment quality of grid.
For example, at pressure adjacent to technology (Stress proximity technology is called for short SPT)
Afterwards, the thickness of sample grid is 670 angstroms, but due to blocking layer of metal silicide (Salicide
Block, is called for short SAB) and PMOS germanium silicon silicon nitride layer (PMOS SiGe Nitride,
It is called for short PSR) mask layer opens, at interlayer dielectric layer CMP (ILD CMP) and sample
Grid remove (Dummy poly remove is called for short DPRM) filling metal and carry out CMP
Afterwards, its thickness is greatly reduced, and only remains 200 Izods right, and this will affect contact hole and gold
Belonging to the alignment quality of grid, this is that those skilled in the art are not expected to see.
Content of the invention
For the problem of above-mentioned existence, the present invention discloses the system of a kind of PSM alignment mark structure
Preparation Method, with solve in prior art the design of PSM alignment mark through ILD CMP and
After the step of DPRM and metal CMP, its thickness is greatly reduced, and then affects contact hole
Problem with the alignment quality of metal gate.
To achieve these goals, the invention provides a kind of PSM alignment mark structure
Preparation method, is applied in the technique of high-dielectric constant metal grid pole, wherein, comprises the steps:
Step S1, provides a substrate with fleet plough groove isolation structure and active area, described lining
The surface configuration at the end has dielectric layer, is formed and is positioned at described active region in described dielectric layer
First grid groove and be positioned at the second gate groove above described fleet plough groove isolation structure, described first grid groove
It is inside provided with the first sample grid, in described second gate groove, be provided with the second sample grid, and described
The length of one sample grid is equal to the degree of depth of described first grid groove, and the length of described second sample grid is little
The degree of depth in described second gate groove；
Step S2, prepare a mask stack superimposition and cover at described first sample grid and described second sample
The top of these grid, and the gap sky on described second sample grid in described second gate groove, will be positioned at
Between filled completely；
Step S3, completely remove be positioned on the first sample grid mask stacking, remove simultaneously
A part of mask on second sample grid stacks and member-retaining portion is covered on the second sample grid
Membrane stack；
Step S4, described dielectric layer is ground, to remove the described first sample grid of part
And carry out partly removing to the remaining mask stacking on the second sample grid；
Step S5, etching are with remaining first sample grid in removing first grid groove completely；
Step S6, filling metal in first grid groove and be ground, nationality is by the second sample grid
On residual mask stacking ensure the second sample grid in process of lapping from damage.
The preparation method of above-mentioned PSM alignment mark structure, wherein, described mask stacking bag
Include oxide skin(coating) and cover the silicon nitride layer of described oxide skin(coating).
The preparation method of above-mentioned PSM alignment mark structure, wherein, in described step S3
In, remove a part of mask stack poststack on the second sample grid, protect on the second sample grid
Staying in part mask stacking, the thickness of described silicon nitride layer is 450-500 angstrom, oxide skin(coating)
Thickness is 50-90 angstrom.
The preparation method of above-mentioned PSM alignment mark structure, wherein, in described step S4
In, after carrying out partly removing to the remaining mask stacking on the second sample grid, described second
The thickness of the remaining silicon nitride layer on sample grid is 50-100 angstrom.
The preparation method of above-mentioned PSM alignment mark structure, wherein, described shallow trench is isolated
The degree of depth of structure is 150-250 angstrom.
The preparation method of above-mentioned PSM alignment mark structure, wherein, the material of described dielectric layer
Matter is oxide.
The preparation method of above-mentioned PSM alignment mark structure, wherein, in step S4 and step
In rapid S6, described grinding is cmp.
The preparation method of above-mentioned PSM alignment mark structure, wherein, described sample grid are many
Crystal silicon or amorphous carbon.
The preparation method of above-mentioned PSM alignment mark structure, wherein, described metal is Al.
The preparation method of above-mentioned PSM alignment mark structure, wherein, is removing the first sample
After grid, and before filling metal, first prepare a floor height K dielectric layer and cover in the first grid
The surface that groove exposes.
The preparation method of above-mentioned PSM alignment mark structure, wherein, described method is applied to
In the technique of 28nm high-dielectric constant metal grid pole.
The invention discloses the preparation method of a kind of PSM alignment mark structure, by shallow ridges
Recess isolating structure (shallow trench isolation is called for short STI) is provided above sample grid,
Prepare mask stacking at the top of this sample grid, and in the technique of high-dielectric constant metal grid pole
In, owing to the shoulder height of fleet plough groove isolation structure and active area makes this mask of part stack
With reservation, and nationality is ensured the second sample grid by the mask stacking of the residual being positioned on this sample grid
From damage in process of lapping, so that the thickness of this sample grid is completely retained, enter
And improve the alignment quality of contact hole and metal gate.
Concrete brief description
By reading the detailed description made non-limiting example with reference to the following drawings, this
Bright and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawings
The identical part of note instruction.Can not be drawn to scale accompanying drawing, it is preferred that emphasis is this is shown
Bright purport.
Fig. 1 is the relation schematic diagram of metal gate thickness and wafer quality in background of invention；
Fig. 2 is the flow chart of the preparation method of PSM alignment mark structure in the embodiment of the present invention；
Fig. 3 a-3g is the stream of the preparation method of PSM alignment mark structure in the embodiment of the present invention
Journey structural representation.
Detailed description of the invention
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not
Restriction as the present invention.
As in figure 2 it is shown, the present embodiment relates to the preparation side of a kind of PSM alignment mark structure
Method, can be applicable to, in the technique of high-dielectric constant metal grid pole, be particularly applied to 28nm Gao Jie
In the technique of dielectric constant metal grid, concrete, the method comprises the steps:
Step one, first, provides one to be provided with fleet plough groove isolation structure 22 and active area 21
Substrate (this substrate is not shown in figure), and be positioned at the substrate of fleet plough groove isolation structure 22
The height of upper surface, less than the height of the substrate top surface being positioned at active area 21, needs at this
Bright, height described herein refers to be positioned at the substrate top surface of fleet plough groove isolation structure 22
With the height relative to same level for the substrate top surface being positioned at active area 21.
Secondly, on substrate, upper surface dielectric layer (this medium in same level is prepared
Layer is not shown in figure) after, the upper surface of eat-back this dielectric layer of part to substrate, to form
Run through some grid grooves of dielectric layer；This some grid grooves include being positioned on fleet plough groove isolation structure 22
Some second gate grooves 32 of side and be positioned at the some first grid grooves 31 above active area 21, and
First grid groove 31 is concordant with the upper surface of second gate groove 32, it is clear that, first grid groove
The degree of depth of 31 is less than the degree of depth of second gate groove 32；Form structure as shown in Figure 3 a.
Again, some grid grooves are filled sample grid material, with in described first grid groove 31
Form the first sample grid 41, in second gate groove 32, form the second sample grid 42, and the first sample
These grid 41 from bottom end face to top end face between length L1 (the i.e. first sample grid 41
Length) and the second sample grid 42 from bottom end face to top end face between length L2 (i.e.
The length of two sample grid 42) identical, owing to the degree of depth of first grid groove 31 is less than second gate groove
The degree of depth of 32, and the first sample grid 41 are identical with the length of the second sample grid 42, so
Allowing for the second sample grid 42 when being arranged on substrate, its upper surface is relative to the position of substrate
Will be different in the height of the top surface of same level, say, that the first sample grid
The top end face of 41 is greater than the second sample grid 42 top end face relative to the height h1 of substrate
Relative to the height h2 of substrate, the length of the i.e. first sample grid 41 is equal to first grid groove 31
The degree of depth, the length of the second sample grid 42 is less than the degree of depth of second gate groove 32, as shown in Figure 3 b
Structure.
In a preferred embodiment of the invention, the degree of depth of second gate groove 32 and the second sample
The difference of the length of these grid 42 (is i.e. positioned at the height of clearance space on the second sample grid 42)
It is just equal to the degree of depth of fleet plough groove isolation structure 22.
Preferably, the degree of depth of fleet plough groove isolation structure 22 be 150-250 angstrom (such as 150 angstroms,
200 angstroms, 210 angstroms or 250 angstroms), then the degree of depth of second gate groove 32 and the second sample grid 42
The difference of length be 150-250 angstrom (such as 150 angstroms, 200 angstroms, 210 angstroms or 250 angstroms).
Preferably, the material of the first sample grid 41 and the second sample grid 42 be polysilicon or
Amorphous carbon.
Preferably, the material of above-mentioned dielectric layer is oxide.
Step 2, prepare one mask stacking 5 covering at the first sample grid 41 and the second sample grid
The top of 42, and the clearance space on the second sample grid 42 in second gate groove 32, will be positioned at
Being filled completely, in one preferred embodiment of the present invention, mask stacking 5 includes oxidation
(this oxide skin(coating) and silicon nitride layer be not in figure for the silicon nitride layer of nitride layer and covering oxide skin(coating)
Identify)；Structure as shown in Figure 3 c.
Optionally, the method using chemical gaseous phase deposition prepares mask stacking 5 covering the
One sample grid 41 and the top of the second sample grid 42.
Step 3, employing etching technics remove the mask being positioned on the first sample grid 41 completely
Stacking 5, removes a part of mask stacking 5 on the second sample grid 42 and second simultaneously
Member-retaining portion mask stacking 5 on sample grid 42；Structure as shown in Figure 3 d.
In one preferred embodiment of the present invention, in step 3, remove the second sample grid
A part of mask stack poststack on 42, member-retaining portion mask stack on the second sample grid 42
In folded 5, the thickness of silicon nitride layer be 450-550 angstrom (such as 450 angstroms, 490 angstroms, 500
Angstrom or 550 angstroms etc.), the thickness of oxide skin(coating) be 50-90 angstrom (such as 50 angstroms, 65 angstroms,
70 angstroms or 90 angstroms etc.).
Optionally, use dry etch process to remove completely to be positioned on the first sample grid 41
Mask stacking 5, remove simultaneously on the second sample grid 42 a part of mask stacking 5 and
Member-retaining portion mask stacking 5 on second sample grid 42.
It step 4, is ground (ILD CMP) to dielectric layer, to remove part the first sample
Remaining mask stacking 5 on second sample grid 42 simultaneously is carried out partly removing by grid 41, as
Structure shown in Fig. 3 e.
In one preferred embodiment of the present invention, in step 4, to the second sample grid 42
On remaining mask stacking 5 carry out after part removes, remaining on the second sample grid
The thickness of silicon nitride layer is 50-100 angstrom of (such as 50 angstroms, 70 angstroms, 80 angstroms or 100 angstroms
Deng).
Optionally, use chemical mechanical milling tech to be ground dielectric layer, remove part
Remaining mask stacking 5 on second sample grid 42 is simultaneously carried out part by the first sample grid 41
Remove.
Step 5, etching are with remaining first sample grid 41 in removing first grid groove 31 completely
(DPRM), in the process, due to the difference of different material etch rates, the second sample
On these grid 42, remaining mask stacking 5 only part is removed, due to remaining mask stacking
The protection of 5, the second sample grid 42 are fully retained, and form structure as illustrated in figure 3f.
In one preferred embodiment of the present invention, dry etch process is used to etch with completely
Remaining first sample grid 41 in removing first grid groove 31.At this it should be noted that use
Dry etch process is carried out in the case of being polysilicon for the first sample grid 41 material,
If sample grid are amorphous carbon, then use ashing to process and remove sample grid.
Step 6, filling metal are interior to first grid groove 31 and are ground, and nationality is by the second sample
Residual on grid 42 mask stacking 5 guarantee the second sample grid 42 in process of lapping from
Damage, and then forming metal gates 6, and second sample during forming metal gates 6
These grid 42 are completely retained.
In one preferred embodiment of the present invention, fill metal and go forward side by side to first grid groove 31
It is cmp that row grinds used grinding technics.
In one preferred embodiment of the present invention, the material of this metal is Al.
In one preferred embodiment of the present invention, after removing the first sample grid 41, and
Before filling metal, first prepare a floor height K dielectric layer and cover in first grid groove 31 exposure
Surface, with after filling metal, forms high-K metal gate in first grid groove 31.
The invention discloses the preparation method of a kind of PSM alignment mark structure, by shallow ridges
Recess isolating structure is provided above sample grid, prepares mask at the top of this sample grid and stacks, and
In the technique of high-dielectric constant metal grid pole, due to the step of fleet plough groove isolation structure and active area
Highly make part this mask stacking be retained, and nationality is by the residual being positioned on this sample grid
Mask stacking ensure the second sample grid in process of lapping from damage so that this sample
The thickness of grid is completely retained, and then improves the alignment quality of contact hole and metal gate, and
This technique is simple and convenient, strong with the compatibility of traditional handicraft, has very strong practicality.
It should be appreciated by those skilled in the art that those skilled in the art combine prior art and
Above-described embodiment can realize change case, does not repeats at this.Such change case has no effect on
The flesh and blood of the present invention, does not repeats them here.
Above presently preferred embodiments of the present invention is described.It is to be appreciated that the present invention
Being not limited to above-mentioned particular implementation, the equipment and the structure that wherein do not describe in detail to the greatest extent should
It is interpreted as being practiced with the common mode in this area；It any is familiar with those skilled in the art
Member, without departing under technical solution of the present invention ambit, may utilize the method for the disclosure above
Make many possible variations and modification to technical solution of the present invention with technology contents, or be revised as
The Equivalent embodiments of equivalent variations, this has no effect on the flesh and blood of the present invention.Therefore, every
Without departing from the content of technical solution of the present invention, the technical spirit of the foundation present invention is to above example
Any simple modification, equivalent variations and the modification done, all still falls within technical solution of the present invention and protects
In the range of protecting.
Claims (11)
1. a preparation method for PSM alignment mark structure, is applied to high-k gold
Belong in grid technology, it is characterised in that comprise the steps:
Step S1, offer one have the substrate of fleet plough groove isolation structure and active area, described lining
The surface configuration at the end has dielectric layer, is formed and is positioned at described active region in described dielectric layer
First grid groove and be positioned at the second gate groove above described fleet plough groove isolation structure, described first grid groove
It is inside provided with the first sample grid, in described second gate groove, be provided with the second sample grid, and described
The length of one sample grid is equal to the degree of depth of described first grid groove, and the length of described second sample grid is little
The degree of depth in described second gate groove；
Step S2, prepare a mask stack superimposition and cover at described first sample grid and described second sample
The top of these grid, and the gap sky on described second sample grid in described second gate groove, will be positioned at
Between filled completely；
Step S3, completely remove be positioned on the first sample grid mask stacking, remove simultaneously
A part of mask on second sample grid stacks and member-retaining portion is covered on the second sample grid
Membrane stack；
Step S4, described dielectric layer is ground, to remove the described first sample grid of part
And carry out partly removing to the remaining mask stacking on the second sample grid；
Step S5, etching are with remaining first sample grid in removing first grid groove completely；
Step S6, filling metal in first grid groove and be ground, nationality is by the second sample grid
On residual mask stacking ensure the second sample grid in process of lapping from damage.
2. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levying and being, described mask stacking includes oxide skin(coating) and covers the silicon nitride of described oxide skin(coating)
Layer.
3. the preparation method of PSM alignment mark structure as claimed in claim 2, it is special
Levy and be, in described step S3, remove a part of mask stacking on the second sample grid
After, on the second sample grid in member-retaining portion mask stacking, the thickness of described silicon nitride layer is
450-500 angstrom, the thickness of oxide skin(coating) is 50-90 angstrom.
4. the preparation method of PSM alignment mark structure as claimed in claim 2, it is special
Levy and be, in described step S4, the remaining mask on the second sample grid is stacked into
After row part removes, the thickness of the remaining silicon nitride layer on described second sample grid is
50-100 angstrom.
5. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levying and being, the degree of depth of described fleet plough groove isolation structure is 150-250 angstrom.
6. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levying and being, the material of described dielectric layer is oxide.
7. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levying and being, in step S4 and step S6, described grinding is cmp.
8. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levying and being, described sample grid are polysilicon or amorphous carbon.
9. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levying and being, described metal is Al.
10. the preparation method of PSM alignment mark structure as claimed in claim 1, it is special
Levy and be, after removing the first sample grid, and before filling metal, first prepare a floor height
K dielectric layer covers the surface exposing at first grid groove.
The preparation method of 11. PSM alignment mark structures as claimed in claim 1, it is special
Levying and being, described method is applied in the technique of 28nm high-dielectric constant metal grid pole.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111199981A (en) * | 2018-11-16 | 2020-05-26 | 合肥鑫晟光电科技有限公司 | Array substrate, preparation method thereof and display device |
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| CN104037118A (en) * | 2013-03-04 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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| US20070196986A1 (en) * | 2006-02-21 | 2007-08-23 | Masayuki Ichige | Method for manufacturing semiconductor device |
| US20110147812A1 (en) * | 2009-12-23 | 2011-06-23 | Steigerwald Joseph M | Polish to remove topography in sacrificial gate layer prior to gate patterning |
| CN103137657A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated device and forming method thereof |
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| CN111199981A (en) * | 2018-11-16 | 2020-05-26 | 合肥鑫晟光电科技有限公司 | Array substrate, preparation method thereof and display device |
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| CN111199981B (en) * | 2018-11-16 | 2023-04-07 | 合肥鑫晟光电科技有限公司 | Array substrate, preparation method thereof and display device |
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