CN105989798B - A kind of bilateral scanning transmitting signal circuit - Google Patents
A kind of bilateral scanning transmitting signal circuit Download PDFInfo
- Publication number
- CN105989798B CN105989798B CN201510067624.XA CN201510067624A CN105989798B CN 105989798 B CN105989798 B CN 105989798B CN 201510067624 A CN201510067624 A CN 201510067624A CN 105989798 B CN105989798 B CN 105989798B
- Authority
- CN
- China
- Prior art keywords
- transistor
- control
- signal
- efferent duct
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of bilateral scannings to emit signal circuit, including：First control module has a pair of transistor, and the opening and closing to transistor are controlled respectively by the first, second opposite control signal of two logical states, by one forward or backwards scanning signal be transported at the first node between transistor；Second control module, the control pipe with a pair of series, is conveyed to the control terminal to control pipe by one group of clock signal, thereby determines the unlatching and closed state to control pipe, this is connected to the first node to one of control pipe respectively；Output module, it connects the second control module and there is the first, second efferent duct and output end, nationality selects turning on or off for the first, second efferent duct by the unlatching and closed state to control pipe, and in the handoff procedure of the first, second efferent duct turned on or off, the first reference voltage or the second reference voltage are exported by output end；To improve the competitiveness of product.
Description
Technical field
The present invention relates to circuit design fields, and in particular to a kind of bilateral scanning transmitting signal circuit.
Background technology
With people's pursuit almost harsh to mobile phone screen, computer screen, AMOLED (Active Matrix/
Organic Light Emitting Diode, active-matrix organic light emitting diode (AMOLED) panel) traditional liquid crystal display panel is compared,
AMOLED has many advantages, such as very fast reaction speed, contrast higher, visual angle is wider, is gradually favored by consumer, major
Display technology enterprise all attaches great importance to this new display technology.
AMOLED is simple scanning pattern at present, in order to improve the competitiveness of AMOLED, it is also desirable to be swept using positive and negative
Pattern is retouched, bilateral scanning needs to design bilateral scanning circuit.
Invention content
The present invention devise a kind of scanning transmitting signal circuit can be applicable to AMOLED, it can be achieved that AMOLED circuits it is double
To scanning, product competitiveness is improved.
The technical solution adopted by the present invention is：
A kind of bilateral scanning transmitting signal circuit, wherein including：
First control module has a pair of transistor, passes through the opposite first control signal of two logical states, the second control
Signal controls the opening and closing of the pair of transistor respectively, by one of the connection of one of the pair of transistor
Scanning signal is transported at the first node connected between the pair of transistor forward or backwards；And
Second control module, the control pipe with a pair of series, the first clock signal, second clock signal are conveyed respectively
To the control terminal of the pair of control pipe, unlatching and the closed state of the pair of control pipe are thereby determined, wherein the pair of
One of control pipe is connected to the first node；
Output module is connect with second control module, and the output module has the first efferent duct, the second output
Pipe and an output end, nationality are selected first efferent duct, described by the unlatching and closed state of the pair of control pipe
Second efferent duct turns on or off, and in the switching of first efferent duct, second efferent duct turned on or off
Cheng Zhong exports one first reference voltage or one second reference voltage by the output end.
Above-mentioned bilateral scanning emits signal circuit, wherein in first control module, the source of one of transistor
It holds to receive forward scan signal and be controlled by the second control signal；The source of another transistor is anti-to receive
It is controlled to scanning signal and by the first control signal；
Wherein, when the first control signal is high level and the second control signal is low level, described first
Control module provides forward scan signal to the first node.
Above-mentioned bilateral scanning emits signal circuit, wherein when the first control signal is low level and described second
When control signal is high level, first control module provides reverse scan signal to the first node.
Above-mentioned bilateral scanning emits signal circuit, wherein second control module includes first to be cascaded
Control pipe and the second control pipe have second node between first control pipe and second control pipe；
Wherein, the on off state of first control pipe is controlled by first clock signal, and controllably will
Scanning signal forward or backwards at the first node is exported；And it is controlled by the second clock signal described
The on off state of second control pipe.
Above-mentioned bilateral scanning emits signal circuit, wherein further includes one the 5th transistor, source is connected to described the
One reference voltage, drain terminal are connected to second control module.
Above-mentioned bilateral scanning emits signal circuit, wherein between the second clock signal and second efferent duct
It is in series with the 7th transistor and the 6th transistor；
The control terminal of 7th transistor is connected with source, and the control terminal is also connected to the 5th transistor
Control terminal；
There is third node between 7th transistor and the 5th transistor.
Above-mentioned bilateral scanning emits signal circuit, wherein further includes one the 9th transistor, is located at described second with reference to electricity
Between pressure and the third node, the 9th transistor is controlled by first clock signal.
Above-mentioned bilateral scanning emits signal circuit, wherein the control of first reference voltage and second efferent duct
One the 8th transistor is provided between end processed, the control terminal of the 8th transistor is connected to the second node.
Above-mentioned bilateral scanning emits signal circuit, wherein further includes 1 the tenth transistor, the control of the tenth transistor
End processed connects second reference voltage, drain terminal is directly connected to the control terminal of the 8th transistor, source connection described first
The control terminal of efferent duct.
Above-mentioned bilateral scanning emits signal circuit, wherein first clock signal by be sequentially connected in series the 11st
Transistor and the tenth two-transistor provide high level signal or low level signal to the third node；
The control terminal of 11st transistor and the tenth two-transistor is all connected to the second node.
Above-mentioned bilateral scanning emits signal circuit, wherein the control of the 6th transistor and first efferent duct
The first capacitance is provided between end.
Above-mentioned bilateral scanning emits signal circuit, wherein the control of first reference voltage and second efferent duct
The second capacitance is provided between end processed.
Above-mentioned bilateral scanning emits signal circuit, wherein is arranged between the source and control terminal of the 7th transistor
There is third capacitance.
Description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical label indicates identical part in whole attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is the purport of the present invention is shown.
Fig. 1 is a kind of schematic diagram of AMOLED bilateral scannings circuit provided by the invention；
Fig. 2A is the break-make situation schematic diagram of each device of the first step in sequence diagram shown in corresponding diagram 2B；
The break-make situation schematic diagram of first step device in sequence diagram shown in Fig. 2 B；
Fig. 3 A are the break-make situation schematic diagram of each device of second step in sequence diagram shown in corresponding diagram 3B；
The break-make situation schematic diagram of second step device in sequence diagram shown in Fig. 3 B；
Fig. 4 A are the break-make situation schematic diagram that third walks each device in sequence diagram shown in corresponding diagram 4B；
The break-make situation schematic diagram of third step device in sequence diagram shown in Fig. 4 B；
Fig. 5 A are the break-make situation schematic diagram of the 4th each device of step in sequence diagram shown in corresponding diagram 5B；
The break-make situation schematic diagram of 4th step device in sequence diagram shown in Fig. 5 B；
Fig. 6 A are the break-make situation schematic diagram of the 5th each device of step in sequence diagram shown in corresponding diagram 6B；
The break-make situation schematic diagram of 5th step device in sequence diagram shown in Fig. 6 B；
Fig. 7 A are the break-make situation schematic diagram of the 6th each device of step in sequence diagram shown in corresponding diagram 7B；
The break-make situation schematic diagram of 6th step device in sequence diagram shown in Fig. 7 B；
Fig. 8 A-8B are analogous diagram of the present invention under up sequential；
Fig. 9 A-9B are analogous diagram of the present invention under down sequential.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical scheme of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiment.
A kind of bilateral scanning transmitting signal circuit, it is shown referring to Fig.1, including：
First control module A1 has a pair of transistor M13 and M14, is believed by the first opposite control of two logical states
Number down and second control signal up controls the opening and closing to transistor M13 and M14 respectively, by this to transistor
A forward scan signal en+1 or reverse scan signal en-1 for one of M13 and M14 connection is transported to this to crystal
At the first node NET1 connected between pipe；
Second control module A2, control pipe M3 and M4 with a pair of series, the source of one of control pipe are connected to
One group of clock signal cke1, cke2 is conveyed to the control terminal to control pipe M3 and M4, thereby determined by first node NET1 respectively
Determine the unlatching and closed state to control pipe M3 and M4, wherein this is connected to first segment to one of control pipe M3 and M4
Point NET1；
Output module A3 is connect with the second control module A2, and output module A3 has the first efferent duct M1, the second output
A pipe M2 and output end en, output module A3 nationalitys are selected first defeated by the unlatching and closed state of each control pipe M3 and M4
Outlet pipe M1, the second efferent duct M2 are turned on or off, and the first efferent duct M1, the second efferent duct M2 turn on or off cut
During changing, one first reference voltage VDD or one second reference voltage VEE are exported by output end en.Wherein, first
Reference voltage VDD is in a high levle, and the second reference voltage VEE first reference voltage VDD that compare are in a low level, therefore
Second reference voltage VEE is lower than the first reference voltage VDD.
As a kind of preferred embodiment of the present invention, in the first control module A1, the source of one of transistor M14
To receive forward scan signal en+1, and transistor M14 is controlled by second control signal down；Another transistor
The source of M13 is to receive a reverse scan signal en-1, and the transistor is controlled by first control signal up；When the first control
When signal up processed is high level and second control signal down is low level, transistor M14 is opened, and the first control module A1 is provided
One forward scan signal en+1 to first node NET1.
On this basis, further, when first control signal up is low level and second control signal down is high electricity
Usually, transistor M14 is opened, and the first control module A1 provides a reverse scan signal en-1 to first node NET1.
As a kind of preferred embodiment of the present invention, the second control module A2 includes the first control pipe being cascaded
M3 and the second control pipe M4 has second node NET4 between the first control pipe M3 and the second control pipe M4；
Wherein, the on off state of the first control pipe M3 is controlled by the first clock signal cke1, and controllably by
Scanning signal forward or backwards at one node NET1 is exported；And the second control is controlled by second clock signal cke2
The on off state of tubulation M4.
Further include one the 5th transistor M5, source is connected to the first ginseng as a kind of preferred embodiment of the present invention
Voltage VDD is examined, drain terminal is connected to the second control module A2, has node between the 5th transistor M5 and the second control module A2
NET5。
As a kind of preferred embodiment of the present invention, it is in series between second clock signal cke2 and the second efferent duct M2
7th transistor M7 and the 6th transistor M6 has node NET9 between the 7th transistor M7 and the 6th transistor M6；
The control terminal of 7th transistor M7 is connected with source, and control terminal is also connected to the control terminal of the 5th transistor M5；
There is third node NET6 between 7th transistor M7 and the 5th transistor M5.
Further include one the 9th transistor M9 as a kind of preferred embodiment of the present invention, is located at the second reference voltage VEE
Between third node NET6, the 9th transistor M9 is controlled by the first clock signal cke1.
As a kind of preferred embodiment of the present invention, the control terminal of the first reference voltage VDD and the second efferent duct M2 it
Between be provided with one the 8th transistor M8, the control terminal of the 8th transistor M8 is connected to second node NET4.
Further include 1 the tenth transistor M10 as a kind of preferred embodiment of the present invention, the tenth transistor M10's
Control terminal connects the second reference voltage VEE, and drain terminal is directly connected to the control terminal of the 8th transistor M8, and source connects the first efferent duct
The control terminal of M1.
As a kind of preferred embodiment of the present invention, the first clock signal cke1 passes through the 11st crystal that is sequentially connected in series
Pipe M11 and the tenth two-transistor M12 offer high level signals or low level signal give third node NET6；
The control terminal of 11st transistor M11 and the tenth two-transistor M12 is all connected to second node NET4.
As a kind of preferred embodiment of the present invention, set between the 6th transistor M6 and the control terminal of the first efferent duct M1
It is equipped with the first capacitance C2.
As a kind of preferred embodiment of the present invention, the control terminal of the first reference voltage VDD and the second efferent duct M2 it
Between be provided with one second capacitance C3, between the second efferent duct M2 and the second capacitance C3 have node NET8.
As a kind of preferred embodiment of the present invention, third is provided between the source and control terminal of the 7th transistor M7
Capacitance C4.
Below in conjunction with circuit diagram shown in Fig. 2A to Fig. 7 B and oscillogram, such as to specific control procedure declaration of the invention
Under：
The first step (Step1)：With reference to shown in Fig. 2A and Fig. 2 B：First clock signal cke1 input low level signals, second
Clock signal cke2 input high level signals, therefore the first control pipe M3 is opened, the second control pipe M4 is closed；First control signal
Down input high level signals, second control signal up input low level signals so that transistor M14 is opened, and transistor M13
It closes, the forward scan signal en-1 (i.e. Ste signals in Fig. 2 B) of high level signal is able to be flowed by transistor M14
It is logical, and it is connected to second node NET4.Due to the conducting of the first control pipe M3, the forward scan signal en-1 of high level signal makes
Obtain the 11st transistor M11 and the tenth two-transistor M12 shutdowns；Since the tenth transistor M10 is by the second ginseng of low level signal
The effect for examining voltage VEE is in the open state, therefore the forward scan signal en-1 of high level signal can continue through the tenth crystalline substance
Body pipe M10 reaches the control terminal of the first efferent duct M1, makes the first efferent duct M1 shutdowns；And the second efferent duct M2 is in high level
Off state so that circuit is maintained at the low level state at moment, and it is low level that third capacitance C4 keeps NET6 herein.
Second step (Step2)：With reference to shown in Fig. 3 A and Fig. 3 B, the first clock signal cke1 input high level signals, second
Clock signal cke2 input low level signals, therefore the second control pipe M4 is opened, the first control pipe M3 is closed；First control signal
Down input high level signals, second control signal up input low level signals so that the 14th transistor M14 is opened, and second
Efferent duct M13 is closed, but since the first control pipe M3 is closed, causes forward scan signal en-1 that can not lead to
It crosses the first control pipe M3 to circulate, therefore is seldom repeated for the second control module A2.Due to the 5th transistor M5 and second
Control pipe M4 is opened, therefore the first reference voltage VDD of high level is able to be connected and be conveyed to by transistor M5, M4
Second node NET4 so that first efferent duct M11, M12 shutdown.The first reference voltage VDD of high level passes through open simultaneously
Tenth transistor M10 is turned off the first efferent duct M1.And simultaneously, low level second clock signal cke2 passes through open
Transistor M7, M6 reach the control terminal of the second efferent duct M2, i.e. node NET8 is low level, and then opens the second efferent duct M2,
So that the first reference voltage VDD of output end en output high level；Wherein, third capacitance C4 plays coupling, because second
Clock signal cke2 voltages, which are lower, is output to node NET9, and then couples third node NET6 voltages by third capacitance C4 and become
It is low, so that lower voltage can be output to node NET9 and NET8.
Third walks (Step3)：With reference to shown in Fig. 4 A and Fig. 4 B, the first clock signal cke1 input low level signals, second
Clock signal cke2 input high level signals, therefore the first control pipe M3 is opened, the second control pipe M4 is closed；First control signal
Down input high level signals, second control signal up input low level signals so that the 14th transistor M14 is opened, and second
Efferent duct M13 is closed, and the forward scan signal en-1 of high level signal is able to circulate by the 14th transistor M14, and
It is connected to second node NET4.Due to the conducting of the first control pipe M13, the forward scan signal en-1 of high level signal makes
11 transistor M11 and the tenth two-transistor M12 shutdowns；Since the tenth transistor M10 is by low level second reference voltage VEE
Effect it is in the open state, therefore the forward scan signal en-1 of high level signal can continue through the tenth transistor M10 and arrive
Up to the control terminal of the first efferent duct M1, make the first efferent duct M1 shutdowns, wherein the effect of the second capacitance C3 is to maintain node NET8
Voltage be low level, so as to open the second efferent duct M2.
4th step (Step4)：With reference to shown in Fig. 5 A and Fig. 5 B, the first clock signal cke1 input high level signals, second
Clock signal cke2 input low level signals, therefore the second control pipe M4 is opened, the first control pipe M3 is closed, due to the first control
Pipe M3 is closed, therefore causes forward scan signal en-1 that can not circulate by the first control pipe M3, therefore needle
Second control module A2 is seldom repeated.Since the 5th transistor M5 and the second control pipe M4 are opened, the of high level
One reference voltage VDD is able to that second node NET4 is connected and be conveyed to by transistor M5, M4 so that the first efferent duct
M11, M12 are turned off.Simultaneously the first reference voltage VDD of high level by the tenth open transistor M10 by the first efferent duct M1
It is turned off.And simultaneously, low level second clock signal cke2 reaches the second efferent duct M1 by open transistor M7, M6
Control terminal, and then open the second efferent duct M1 so that the first reference voltage VDD of output end en output high level, wherein the
Three capacitance C4 roles are identical as its effect played in second step, and specific descriptions please refer to second step, to reduce weight
Multiple, just it will not go into details herein.
5th step (Step5)：With reference to shown in Fig. 6 A and Fig. 6 B, the first clock signal cke1 input low level signals, second
Clock signal cke2 input high level signals, therefore the first control pipe M3 is opened, the second control pipe M4 is closed, while opening crystalline substance
Body pipe M9；First control signal down input high level signals, second control signal up input low level signals so that the 14th
Transistor M14 is opened, and the second efferent duct M13 is closed, and the forward scan signal en-1 of low level signal is able to through the 14th crystalline substance
Body pipe M14 circulates, and is connected to second node NET4, and low level signal reaches the first output by the tenth transistor M10
The control terminal of pipe M1, makes the first efferent duct M1 open, and the second reference voltage VEE is exported by output end en.
6th step (Step6)：With reference to shown in Fig. 7 A and Fig. 7 B, the first clock signal cke1 input high level signals, second
Clock signal cke2 input low level signals, with reference to shown in Fig. 7 B, the first efferent duct M1's break-make situation of each device exists in circuit
It is opened in the state of low level, and the second efferent duct M1 is closed in the state of high level so that output end en exports low level
The second reference voltage VEE, wherein the effect of the first capacitance C2 be coupling because second clock signal cke2 voltages are lower, and
Node NET12 floats (floating) at this time, so node NET12 can follow second clock signal cke2 voltages to be lower and drop
Low, the control terminal voltage of such first efferent duct M1 can be lower, thereby may be ensured that the low-voltage of the second reference voltage VEE can be with
It is input to output end En.And the effect of the tenth transistor M10 can ensure that second transistor NET4 not will produce lower voltage,
Keep a constant low level, can protect in this way control pipe M3, the 11st transistor M11 and the tenth two-transistor M12 with
And the 8th transistor M8 do not influenced by big cross-pressure.
Bilateral scanning may be implemented in circuit provided by the present invention, is to control scanning direction by the signal of up and down
From top to bottom still from the bottom up, it is controlled using the sequential of Fig. 8 A and Fig. 9 A, generates up and the down sequence of Fig. 8 B and Fig. 9 B
Sequential, it can be seen that the sequential of up and down is just in turn, to solve the problems, such as that the present invention is desired and solve.
Bilateral scanning provided by the present invention transmitting signal circuit can be applied in the fields AMOLED, with drive AMOLED into
Row work, improves product competitiveness.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (14)
1. a kind of bilateral scanning emits signal circuit, which is characterized in that including：
First control module has a pair of transistor, passes through the opposite first control signal of two logical states, second control signal
The opening and closing of the pair of transistor are controlled respectively, forward direction that one of the pair of transistor is connected
Or reverse scan signal is transported at the first node connected between the pair of transistor；
Second control module, the control pipe with a pair of series, institute is conveyed to by the first clock signal, second clock signal respectively
The control terminal of a pair of control pipe is stated, thereby determines unlatching and the closed state of the pair of control pipe, wherein the pair of control
The source of one of pipe is connected to the first node；And
Output module is connect with second control module, and the output module have the first efferent duct, the second efferent duct with
And an output end, nationality are selected first efferent duct, described second by the unlatching and closed state of the pair of control pipe
Efferent duct turns on or off, and first efferent duct, second efferent duct the handoff procedure turned on or off in,
One first reference voltage or one second reference voltage are exported by the output end.
2. bilateral scanning as described in claim 1 emits signal circuit, which is characterized in that in first control module,
In a transistor source receiving forward scan signal and be controlled by the second control signal；Another transistor
Source receiving reverse scan signal and be controlled by the first control signal；
Wherein, when the first control signal is high level and the second control signal is low level, first control
Module provides forward scan signal to the first node.
3. bilateral scanning as claimed in claim 2 emits signal circuit, which is characterized in that when the first control signal is low
When level and the second control signal are high level, first control module provides reverse scan signal to the first segment
Point.
4. bilateral scanning as described in claim 1 emits signal circuit, which is characterized in that second control module includes string
The first control pipe and the second control pipe being linked togather have second between first control pipe and second control pipe
Node；
Wherein, the on off state of first control pipe is controlled by first clock signal, and controllably will be described
Scanning signal forward or backwards at first node is exported；And control described second by the second clock signal
The on off state of control pipe.
5. bilateral scanning as described in claim 1 emits signal circuit, which is characterized in that further include one the 5th transistor,
Source is connected to first reference voltage, and drain terminal is connected to second control module.
6. bilateral scanning as claimed in claim 4 emits signal circuit, which is characterized in that further include one the 5th transistor,
Source is connected to first reference voltage, and drain terminal is connected to second control module；
It is in series with the 7th transistor and the 6th transistor between the second clock signal and second efferent duct；
The control terminal of 7th transistor is connected with source, and the control terminal of the 7th transistor is also connected to the described 5th
The control terminal of transistor；
There is third node between 7th transistor and the 5th transistor.
7. bilateral scanning as claimed in claim 5 emits signal circuit, which is characterized in that
It is in series with the 7th transistor and the 6th transistor between the second clock signal and second efferent duct；
The control terminal of 7th transistor is connected with source, and the control terminal of the 7th transistor is also connected to the described 5th
The control terminal of transistor；
There is third node between 7th transistor and the 5th transistor.
8. bilateral scanning as claimed in claims 6 or 7 emits signal circuit, which is characterized in that further include one the 9th transistor,
Between second reference voltage and the third node, the 9th transistor is controlled by first clock signal
System.
9. bilateral scanning as claimed in claim 4 emits signal circuit, which is characterized in that first reference voltage with it is described
One the 8th transistor is provided between the control terminal of second efferent duct, the control terminal of the 8th transistor is connected to described second
Node.
10. bilateral scanning as claimed in claim 9 emits signal circuit, which is characterized in that further include 1 the tenth transistor, institute
The control terminal for stating the tenth transistor connects second reference voltage, drain terminal be directly connected to the 8th transistor control terminal,
Source connects the control terminal of first efferent duct.
11. bilateral scanning as claimed in claim 6 emits signal circuit, which is characterized in that first clock signal passes through
The 11st transistor being sequentially connected in series and the tenth two-transistor provide high level signal or low level signal to the third node；
The control terminal of 11st transistor and the tenth two-transistor is all connected to the second node.
12. bilateral scanning as claimed in claims 6 or 7 emits signal circuit, which is characterized in that the control of the 6th transistor
It is provided with the first capacitance between end processed and the control terminal of first efferent duct.
13. bilateral scanning as described in claim 1 emits signal circuit, which is characterized in that first reference voltage and institute
It states and is provided with the second capacitance between the control terminal of the second efferent duct.
14. bilateral scanning as claimed in claims 6 or 7 emits signal circuit, which is characterized in that the source of the 7th transistor
It is provided with third capacitance between end and control terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510067624.XA CN105989798B (en) | 2015-02-09 | 2015-02-09 | A kind of bilateral scanning transmitting signal circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510067624.XA CN105989798B (en) | 2015-02-09 | 2015-02-09 | A kind of bilateral scanning transmitting signal circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105989798A CN105989798A (en) | 2016-10-05 |
| CN105989798B true CN105989798B (en) | 2018-10-16 |
Family
ID=57040997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510067624.XA Active CN105989798B (en) | 2015-02-09 | 2015-02-09 | A kind of bilateral scanning transmitting signal circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105989798B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109243352B (en) * | 2017-07-11 | 2021-10-26 | 上海和辉光电股份有限公司 | Driving circuit, driving method thereof and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079243A (en) * | 2006-05-25 | 2007-11-28 | 三菱电机株式会社 | Shift register circuit and image display apparatus equipped with the same |
| JP2008287753A (en) * | 2007-05-15 | 2008-11-27 | Mitsubishi Electric Corp | Shift register circuit and image display device provided with the same |
| CN103714792A (en) * | 2013-12-20 | 2014-04-09 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130137860A (en) * | 2012-06-08 | 2013-12-18 | 삼성디스플레이 주식회사 | Stage circuit and emission driver using the same |
-
2015
- 2015-02-09 CN CN201510067624.XA patent/CN105989798B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079243A (en) * | 2006-05-25 | 2007-11-28 | 三菱电机株式会社 | Shift register circuit and image display apparatus equipped with the same |
| JP2008287753A (en) * | 2007-05-15 | 2008-11-27 | Mitsubishi Electric Corp | Shift register circuit and image display device provided with the same |
| CN103714792A (en) * | 2013-12-20 | 2014-04-09 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105989798A (en) | 2016-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106652911B (en) | OLED pixel driving circuit and OLED display | |
| CN106531076B (en) | A kind of pixel circuit, display panel and its driving method | |
| CN104183219B (en) | Scanning drive circuit and organic light-emitting displayer | |
| CN106601190B (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN105609041B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN105741781B (en) | AMOLED pixel-driving circuits and image element driving method | |
| CN106104664B (en) | Display device and its driving method | |
| CN104766580B (en) | Shift register cell and driving method, gate driving circuit and display device | |
| CN104464628B (en) | Shifting register unit, driving method of shifting register unit, grid drive circuit and display device | |
| CN103280200B (en) | Shift register unit, gate drive circuit and display device | |
| CN107993615B (en) | GOA circuit unit, GOA circuit and display panel | |
| CN105632403B (en) | A kind of pixel circuit, driving method, display panel and display device | |
| CN105139801B (en) | Array base palte horizontal drive circuit, shift register, array base palte and display | |
| US20150171833A1 (en) | Gate driver circuit outputting superimposed pulses | |
| CN109427285A (en) | Gating drive circuit and the electroluminescent display for using the gating drive circuit | |
| CN109147635A (en) | A kind of shift register, its driving method and display device | |
| CN104835465B (en) | Shift register, gate driving circuit and liquid crystal display panel | |
| CN106652918A (en) | GOA unit, driving method of GOA unit, GOA circuit and display device | |
| US20160189652A1 (en) | Scan driving circuit | |
| US10115338B2 (en) | Driving circuit and display device using the same | |
| CN107123397B (en) | AMOLED pixel-driving circuit and image element driving method | |
| CN105632446A (en) | GOA unit, driving method thereof, GOA circuit and display device | |
| CN103927982A (en) | Pixel circuit and driving method and display device thereof | |
| CN106710522A (en) | OLED pixel drive circuit and pixel drive method | |
| CN102655145A (en) | Static releasing protection circuit and working method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 201506, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee after: Shanghai Hehui optoelectronic Co., Ltd Address before: 201506, building two, building 100, 1, Jinshan Industrial Road, 208, Shanghai, Jinshan District Patentee before: EverDisplay Optronics (Shanghai) Ltd. |