CN105989788B - Display device - Google Patents
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- CN105989788B CN105989788B CN201510085306.6A CN201510085306A CN105989788B CN 105989788 B CN105989788 B CN 105989788B CN 201510085306 A CN201510085306 A CN 201510085306A CN 105989788 B CN105989788 B CN 105989788B
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Abstract
The present invention discloses a kind of display device, comprising: viewing area has the multiple pixels being located on a substrate；And neighboring area is located on the outside of viewing area, neighboring area includes multiple first circuit regions and multiple second circuit areas on the substrate, and the first circuit region drives pixel according to first direction, and second circuit area drives pixel according to second direction；Wherein at least one of one of one of first circuit region and second circuit area are a pentagons, with sequentially connected first while, second while, third in, third while, with the 4th side, wherein the first side is parallel with second direction, wherein the second side is parallel with first direction, wherein third side is parallel with the diagonal line of the one of pixel, wherein the 4th side substrate edges corresponding with pentagon are substantial parallel, and the 4th side length be greater than pixel at least one of side length, and it is wherein the 5th parallel while with third.
Description
Technical field
The present invention relates to display devices, and design more particularly to the shape of the circuit region of its neighboring area.
Background technique
General display device is rectangle, is broadly divided into the neighboring area of viewing area and periphery.Contain multiple in neighboring area
The circuit region of rectangle, to drive the pixel in viewing area.However in the display device of other shapes, rectangular circuit Qu Yuzhou
Space between the substrate edges of border region is excessive and can not properly utilize.In general, the area of circuit region is bigger, in circuit
There is bigger elasticity in design.In order to reduce the space between circuit region and substrate edges, existing circuit region design is often
There is different shape in irregular type, and as position is different, causes the circuit design of a certain circuit region that can not be suitable for other
Circuit region.
In conclusion needing new circuit region shape at present to reduce the space between circuit region and substrate edges, and this
Circuit region shape should apply to any position of neighboring area.
Summary of the invention
The display device that one embodiment of the invention provides, comprising: viewing area has the multiple pixels being located on substrate；With
And neighboring area is located on the outside of viewing area, neighboring area includes multiple first circuit regions and multiple second circuits on substrate
Area, the first circuit region drives pixel according to first direction, and second circuit area drives pixel according to second direction；Wherein the first circuit region
Pentagon at least one of second circuit area, have sequentially connected first while, second while, third while, the 4th while, with the
Five sides, wherein the first side is parallel with second direction, wherein the second side is parallel with first direction, the wherein one on third side and pixel
Diagonal line it is parallel, wherein the 4th side substrate edges corresponding with pentagon are substantial parallel, and the length on the 4th side is greater than picture
The length of at least one of the side of element, and it is wherein the 5th parallel while with third.
The display device that one embodiment of the invention provides, comprising: viewing area has the multiple pixels being located on substrate；With
And neighboring area is located on the outside of viewing area, neighboring area includes multiple first circuit regions and multiple second circuits on substrate
Area, the first circuit region drive pixel according to first direction, and second circuit area drives pixel according to second direction；Wherein the first circuit region with
At least one of second circuit area is heptagon, have sequentially connected first while, second while, third while, the 4th while, the 5th
While, the 6th while, with the 7th side, wherein the first side is parallel with second direction, wherein the second side is parallel with first direction, wherein the 4th
Side substrate edges corresponding with heptagon are substantial parallel, and the length on the 4th side is greater than the length of at least one of side of pixel
Degree, wherein the 6th is parallel while with first, and it is wherein the 7th parallel while with second.
Detailed description of the invention
Fig. 1 is the schematic diagram of the display device in one embodiment of the invention；
Fig. 2 and Fig. 3 is the distribution map of the first circuit region and second circuit area in the embodiment of the present invention；
Fig. 4 to Fig. 9 is the schematic diagram of the shape of the first circuit region and second circuit area in the embodiment of the present invention；
Figure 10 A to Figure 10 D is the layout of the first circuit region and second circuit area in the embodiment of the present invention；
Figure 11 is the circuit diagram of the shift register in one embodiment of the invention；
Figure 12 is the circuit diagram of the multiplexing controller in one embodiment of the invention.
Symbol description
CLR, CLG, CLB timing signal line
D data line
Mn1, Mn2, Mn3, Mn4, Mn10, Mn11, Mn12, Mn13, Mn14 transistor
The side P
S scan line
VH, VL power supplying line
The first side V-1, VI-1, VII-1
The second side V-2, VI-2, VII-2
V-3, VI-3, VII-3 third side
The 4th side V-4, VI-4, VII-4
The 5th side V-5, VI-5, VII-5
The 6th side VI-6, VII-6
The 7th side VII-7
10 substrates
11 viewing areas
11A first direction
11B second direction
11C diagonal line
13 neighboring areas
13E substrate edges
15 wiring
100 display devices
110 pixels
131 first circuit regions
133 second circuit areas
Specific embodiment
Fig. 1 is the schematic diagram of a display device of the invention.Display device 100 has circular substrate edges, is broadly divided into
Viewing area 11 and neighboring area 13.Viewing area 11 has the pixel 110 being located on substrate 10.In the embodiment in figure 1, pixel
110 be rectangular, and first direction 11A is perpendicular to second direction 11B.In other embodiments, pixel can be hexagon, and first
The angle of direction 11A and second direction 11B is 60 degree.
The neighboring area 13 of Fig. 1, which has, is located at multiple first circuit regions 131 and second circuit area 133 on substrate 10.First
Circuit region 131 drives pixel 110 according to first direction 11A, and second circuit area 133 drives pixel 110 according to second direction 11B.It lifts
For example, the first circuit region 131 can be shift register (SR), and the first single circuit region 131 drive single-row pixel
110 (and connecting its scan line S).Second circuit area 133 can be the switch (MUX switch) of multiplexing controller, and single
The pixel 110 (and connecting its data line D) of the driving of second circuit area 133 at least a line.
First circuit region 131 contained by the neighboring area 13 of Fig. 1 can be as shown in Figure 2 or Figure 3 with second circuit area 133.?
In Fig. 2, there is the neighboring area 13 of part that the first circuit region 131 and 133rd area of second circuit are all set.In Fig. 3, there is the week of part
Border region 13 is only arranged the first circuit region 131 and has the neighboring area 13 of part that second circuit area 133 is only arranged.
Fig. 4 is the enlarged drawing in the region 200 of Fig. 1, to the first circuit region 131 and second circuit in the design of explanatory diagram 3
The shape in area 133.It is understood that although the lower left corner of Fig. 3 is second circuit area 133, the shape in second circuit area 133
Design can also be applied to first circuit region 131 in the lower right corner.
As shown in figure 4, there are three sub-pixel (R, G and B) for each tool of pixel 110.It is understood that pixel 110 can have
There are design of more sub-pixels without being limited to three common sub-pixels, and the arrangement mode of three sub-pixels and size
It can adjust according to need.In Fig. 4, second circuit area 133 is pentagon.By taking intermediate second circuit area 133 as an example, pentagon tool
There is sequentially connected first V-2, third V-4 and the 5th side V-5 in V-3, the 4th in V-1, second.First side V-1 and
Two direction 11B are parallel, and the second side V-2 is parallel with first direction 11A, and third side V-3 is parallel with the diagonal line 11C of pixel 110.
The substrate edges 13E of the neighboring area 13 corresponding with pentagon 4th side V-4 is substantial parallel, and the 4th side V-4 is greater than pixel
At least one of 110 side P.For example, the 4th side V-4 be greater than the right edge of pixel 110, left side, upper side edge or under
Side.5th when V-5 is with third V-3 it is parallel.In an embodiment of the present invention, second circuit area 133 and substrate edges 13E it
Between can accompany wiring 15, to connect different second circuit areas 133 to external circuit.Embodiment as shown in Figure 4, the first side V-
1 with viewing area 11 in outermost pixel 110 one side (such as left side of the pixel 110 of 133 right of second circuit area)
It is adjacent, and in the second side V-2 and the viewing area 11 another one of outermost pixel 110 side (in such as second circuit area 133
The downside of the pixel 110 of side) it is adjacent.
In Fig. 4, third length of V-5 when V-3 is with the 5th is identical.But in other embodiments, third side V-3 and
The length of five side V-5 can not be identical, keeps the substrate edges 13E of the 4th side V-4 and different location substantial parallel, as shown in Figure 5.
Similarly, first when V-1 is with second the length of V-2 it is also not necessarily identical, hold depending on its corresponding number of pixels.No matter such as
What, the 4th side V-4 is substantial parallel with substrate edges 13E.At this it should be noted that, although macroscopic upper substrate edge 13E
For circle, but it is microcosmic such as Pixel Dimensions when, the substrate edges 13E in corresponding second circuit area 133 may be regarded as straight line.
Fig. 6 is the enlarged drawing in the region 200 of Fig. 1, and the neighboring area 13 to part in the design of explanatory diagram 2 is all arranged the
The shape of one circuit region 131 and second circuit area 133 (lower half).Only it is arranged first as the neighboring area 13 of part in Fig. 2
Aforementioned pentagonal design can be used in circuit region 131 (upper half).It is understood that although the design of Fig. 6 corresponds to the lower left corner
The first circuit region 131 and second circuit area 133 is all arranged in the neighboring area 13 of middle part, but can also be applied to part in the lower right corner
Neighboring area 13 first circuit region 131 and second circuit area 133 are all set.In other embodiments, the neighboring area of part
13 are all arranged other regions that the first circuit region 131 can be located at other than the lower half of neighboring area 13 with second circuit area 133, but
It is all suitable for the design of Fig. 6.
In Fig. 6, second circuit area 133 is between the first circuit region 131 and viewing area 11.Pentagonal first circuit
Area 131 has sequentially connected first V-2, third V-4 and the 5th side V-5 in V-3, the 4th in V-1, second.First side
V-1 is parallel with second direction 11B, and the second side V-2 is parallel with first direction 11A, and the diagonal line of third side V-3 and pixel 110
11C is parallel.The substrate edges 13E of the neighboring area 13 corresponding with pentagon 4th side V-4 is substantial parallel, and the 4th side V-4
Greater than at least one of the side P of pixel 110.For example, the 4th side V-4 be greater than the right edge of pixel 110, left side, on
Side or lower side.5th when V-5 is with third V-3 it is parallel.In an embodiment of the present invention, the first circuit region 131 and substrate
Wiring 15 can be accompanied between edge 13E, to connect the first different circuit regions 131 to external circuit.
As shown in fig. 6, the second circuit area 133 of hexagon has sequentially connected first VI-2, the in VI-1, second
Three in VI-3, the 4th VI-4, the 5th while VI-5, with the 6th while VI-6.First side VI-1 is parallel with second direction 11B, and with
Side (such as left side of the pixel 110 of 133 right of second circuit area) phase of the one of outermost pixel 110 in viewing area 11
It is adjacent.Second side VI-2 is parallel with first direction 11A, and with the side of the another one of outermost pixel in viewing area 11 (such as
The downside of the pixel 110 of two circuit regions, 133 top) it is adjacent.Third side VI-3 is parallel with the diagonal line 11C of the one of pixel 110.
4th when VI-4 is with first VI-1 it is parallel and adjacent with the first side V-1 of pentagonal first circuit region 131 on the left of it.
5th when VI-5 is with second VI-2 it is parallel and adjacent with the second side V-2 of pentagonal first circuit region 131 on the downside of it.
6th when VI-6 is with third VI-3 it is parallel.
Fig. 7 is the enlarged drawing in the region 200 of Fig. 1, to the first circuit region 131 and second circuit in the design of explanatory diagram 3
The shape in area 133.It is understood that although the lower left corner of Fig. 7 is second circuit area 133, the shape in second circuit area 133
Design can also be applied to first circuit region 131 in the lower right corner.
As shown in fig. 7, second circuit area 133 is heptagon, there is the VII- in VII-1, second of sequentially connected first
2, third VII-6 while VII-4, the 5th are in VII-5, the 6th in VII-3, the 4th, with the 7th side VII-7.First side VII-1 with
Second direction 11B is parallel, and with the first side of the one of pixel 110 outermost in viewing area 11 (as intermediate in Fig. 7
The left side of pixel 110) it is adjacent.Second side VII-2 is parallel with first direction 11A, and with pixel 110 outermost in viewing area 11
Both the side (downside of the pixel 110 of top in such as Fig. 7) it is adjacent.The periphery corresponding with heptagon 4th side VII-4
The substrate edges 13E in region 13 is substantial parallel, and the 4th side VII-4 is greater than at least one of the side P of pixel 110.Citing
For, the length of the 4th side VII-4 is greater than upper side edge, lower side, left side or the right edge of pixel 110.6th side VII-6
It is parallel with the first side VII-1, and with the side of the third party of pixel 110 outermost in viewing area 11 (in such as Fig. 7 lower section picture
The left side of element) it is adjacent.7th when VII-7 is with second VII-2 it is parallel, and with pixel 110 outermost in viewing area 11
The second side (downside of intermediate pixel 110 in such as Fig. 7) of one is adjacent.In an embodiment of the present invention, second circuit area
Wiring 15 can be accompanied between 133 and substrate edges 13E, to connect different second circuit areas 133 to external circuit.
In Fig. 7, it can adjust the length of third VII-5 in VII-3 and the 5th, make the 4th side VII-4 and different location
Substrate edges 13E it is substantial parallel, as shown in Figure 8.Similarly, first in VII-1, second VII-2, the 6th side VII-6,
It is also not necessarily identical as the length of the 7th side VII-7, it holds depending on its corresponding number of pixels.Anyway, the 4th side VII-4
It is substantial parallel with substrate edges 13E.At this it should be noted that, although macroscopic upper substrate edge 13E be circle, micro-
When seeing such as Pixel Dimensions, the substrate edges 13E in corresponding second circuit area 133 may be regarded as straight line.
Fig. 9 is the enlarged drawing in the region 200 of Fig. 1, and the neighboring area 13 to part in the design of explanatory diagram 2 is all arranged the
The shape of one circuit region 131 and second circuit area 133 (lower half).Only it is arranged first as the neighboring area 13 of part in Fig. 9
Aforementioned pentagonal design can be used in circuit region (upper half).It is understood that although the design of Fig. 9 corresponds in the lower left corner
The first circuit region 131 and second circuit area 133 is all arranged in partial neighboring area 13, but can also be applied to part in the lower right corner
The first circuit region 131 and second circuit area 133 is all arranged in neighboring area 13.In other embodiments, the neighboring area 13 of part
Other regions that first circuit region 131 can be located at other than the lower half of neighboring area 13 with second circuit area 133 are all set, but all
It is applicable in the design of Fig. 9.
In Fig. 9, second circuit area 133 is between the first circuit region 131 and viewing area 11.Heptagonal first circuit
Area 131 has sequentially connected first VII-2, third VII-4, the 5th side VII- in VII-3, the 4th in VII-1, second
5, the 6th while VII-6, with the 7th while VII-7.First side VII-1 is parallel with second direction 11B.Second side VII-2 and first party
It is parallel to 11A.The substrate edges 13E of the neighboring area 13 corresponding with heptagon 4th side VII-4 is substantial parallel, and the 4th side
VII-4 is greater than at least one of the side P of pixel 110.For example, the length of the 4th side VII-4 is greater than the upside of pixel 110
Side, lower side, left side or right edge.6th when VII-6 is with first VII-1 it is parallel.7th in VII-7 and second
VII-2 is parallel.In an embodiment of the present invention, wiring 15 can be accompanied between the first circuit region 131 and substrate edges 13E, with even
The first different circuit regions 131 is connect to external circuit.
As shown in figure 9, the second circuit area 133 of hexagon has sequentially connected first VI-2, the in VI-1, second
Three in VI-3, the 4th VI-4, the 5th while VI-5, with the 6th while VI-6.First side VI-1 is parallel with second direction 11B, and with
Side (such as left side of the pixel 110 of 133 right of second circuit area) phase of the one of outermost pixel 110 in viewing area 11
It is adjacent.Second side VI-2 is parallel with first direction 11A, and with the side of the another one of outermost pixel in viewing area 11 (such as
The downside of the pixel 110 of two circuit regions, 133 top) it is adjacent.Third side VI-3 is parallel with the diagonal line 11C of the one of pixel 110.
4th when VI-4 is with first VI-1 it is parallel and adjacent with the first side VII-1 of heptagonal first circuit region 131.5th side
VI-5 is parallel with the second side VI-2, and adjacent with the 7th side VII-7 of heptagonal first circuit region 131.6th side VI-6 with
Third side VI-3 is parallel.
In an embodiment of the present invention, its layout is such as pentagonal first circuit region 131 (design of such as Fig. 4 or Fig. 5)
Shown in Figure 10 A, for multiple shift registors of corresponding driving multi-strip scanning line S, one of shift registor includes power supply
Line VH and VL, power supplying line VH is adjacent with pentagonal 4th side V-4 with VL, and substrate edges corresponding with pentagon
13E is substantial parallel.The circuit diagram of above-mentioned shift register is as shown in figure 11.In general, there are four brilliant for shift register tool
Body pipe Mn1, Mn2, Mn3 and Mn4, to drive the grid in single-row pixel 110.
In an embodiment of the present invention, its layout is such as pentagonal second circuit area 133 (design of such as Fig. 4 or Fig. 5)
Shown in Figure 10 B, for multiple multiplexing controllers of corresponding driving multiple data lines.The clock signal that one of multiplexing controller includes
It is line CLR, CLG, adjacent with pentagonal 4th side V-4 with CLB, and substrate edges 13E corresponding with pentagon is substantial parallel.
The circuit diagram of above-mentioned multiplexing controller is as shown in figure 12.In general, three transistor Mn10, Mn11 of multiplexing controller,
The data line of Mn12 RGB sub-pixel in the pixel 110 that different phases can switch respectively uniline.If pixel 110 has more times
Pixel (such as RGBY), then the number of transistor is more (such as 4).On the other hand, the transistor Mn13 of multiplexing controller with
Mn14 is the protection circuit of static discharge.
In an embodiment of the present invention, the first circuit region 131 is pentagon, and second circuit area 133 is hexagon, and the
Two circuit regions 133 are located between the first circuit region 131 and pixel 110 (design of such as Fig. 6).First circuit region 131 is displacement
Register, layout can refer to Figure 10 A.Second circuit area 133 is multiple multiplexing controllers of corresponding driving multiple data lines,
Its layout is as illustrated in figure 10 c.One of multiplexing controller includes power supplying line VL, and the of power supplying line VL and hexagon
Five side VI-5 are adjacent.The circuit diagram of above-mentioned multiplexing controller is as shown in figure 12.
In an embodiment of the present invention, heptagonal first circuit region 131 (design of such as Fig. 7 or Fig. 8) is corresponding driving
Multiple shift registors of multi-strip scanning line, layout are as shown in Figure 10 D.The power supplying line that one of shift registor includes
VL is adjacent with heptagonal 4th side VII-4, and substrate edges 13E corresponding with heptagon is substantial parallel.Above-mentioned displacement is posted
The circuit diagram of storage is as shown in figure 11.
In an embodiment of the present invention, heptagonal first circuit region 131 (design of such as Fig. 7 or Fig. 8) is corresponding driving
Multiple shift registors of multi-strip scanning line, layout are as shown in Figure 10 D.The power supplying line that one of shift registor includes
VL is adjacent with heptagonal 5th side VII-5.The circuit diagram of above-mentioned shift register is as shown in figure 11.
In an embodiment of the present invention, heptagonal first circuit region 131 (design of such as Fig. 7 or Fig. 8) is corresponding driving
Multiple shift registors of multi-strip scanning line, layout are as shown in Figure 10 D.The power supplying line that one of shift registor includes
VH with heptagonal first in VII-1 and the 7th VII-7 it is adjacent.The circuit diagram of above-mentioned shift register is as shown in figure 11.
In an embodiment of the present invention, the first circuit region 131 is heptagon, and second circuit area 133 is hexagon, and the
Two circuit regions 133 are located between the first circuit region 131 and pixel 110 (design of such as Fig. 9).First circuit region 131 is displacement
Register, layout can refer to Figure 10 D.Second circuit area 133 is multiple multiplexing controllers of corresponding driving multiple data lines,
The power supplying line VL that one of multiplexing controller includes is adjacent with the 5th side VI-5 of hexagon.The circuit of above-mentioned multiplexing controller
Figure is as shown in figure 12.It is worth noting that, circuit diagram shown in the layout of Figure 10 A to Figure 10 D and Figure 11 and Figure 12 only to
It illustrates rather than limits to the present invention.As long as the shift register of pixel or the layout or circuit of multiplexing controller can be driven,
It can be used as the layout or circuit of the first circuit region 131 or second circuit area 133 of the invention.
In conclusion novel circuit region shape design has been provided in the present invention.Foregoing circuit area shape can reduce circuit region
Space between substrate edges, and can be applied to any position of neighboring area.
Although disclosing the present invention in conjunction with several of the above embodiment, it is not intended to limit the invention, any skill
Have usually intellectual in art field, without departing from the spirit and scope of the present invention, can arbitrarily change and retouch, therefore
Protection scope of the present invention should be subject to what the appended claims were defined.
Claims (17)
1. a kind of display device, comprising:
Viewing area has the multiple pixels being located on a substrate；And
Neighboring area is located on the outside of the viewing area, which has multiple first circuit regions and more being located on the substrate
A second circuit area, those first circuit regions drive those pixels according to a first direction, and those second circuit areas are according to one second
Direction drives those pixels；
Wherein at least one of one of one of those first circuit regions and those second circuit areas are a pentagon, pentagon tool
Have sequentially connected first while, second while, third while, the 4th while, with the 5th side,
Wherein pentagonal first side is parallel with the second direction,
Wherein pentagonal second side is parallel with the first direction,
Wherein the pentagonal third side is parallel with the diagonal line of the one of those pixels,
Wherein pentagonal 4th side substrate edges corresponding with the pentagon are substantial parallel, and this pentagonal 4th
The length on side is greater than the length of at least one of side of those pixels, and
Wherein this is the pentagonal 5th parallel while with the pentagonal third.
2. display device as described in claim 1, wherein outermost pixel in pentagonal first side and the viewing area
One side it is adjacent, and the side phase on pentagonal second side and the another one of outermost pixel in the viewing area
It is adjacent.
3. display device as described in claim 1, wherein those pixels are rectangles, the first direction is perpendicular to the second party
To each of first circuit region drives single-row pixel, and the pixel of each of second circuit area driving at least a line.
4. display device as described in claim 1, wherein the viewing area is substantially rounded.
5. display device as described in claim 1, wherein those first circuit regions are the multiple of corresponding driving multi-strip scanning line
Shift registor, one of those shift registors include a power supplying line, the power supplying line and pentagonal 4th side
It is adjacent, and the substrate edges corresponding with the pentagon are substantial parallel.
6. display device as described in claim 1, wherein those second circuit areas are the multiple of corresponding driving multiple data lines
Multiplexing controller, one of those multiplexing controllers include a timing signal line, the timing signal line and pentagonal 4th side
It is adjacent, and the substrate edges corresponding with the pentagon are substantial parallel.
7. display device as described in claim 1, wherein in one of one of those first circuit regions and those second circuit areas
Another one be a hexagon, and be located between the pentagon and the viewing area,
Wherein the hexagon have sequentially connected first while, second while, third while, the 4th while, the 5th while, with the 6th while,
Wherein the first side of the hexagon is parallel with the second direction, and the side with the one of outermost pixel in the viewing area
Side is adjacent,
Wherein the second side of the hexagon is parallel with the first direction, and the side with the another one of pixel outermost in viewing area
Side is adjacent,
Wherein the third side of the hexagon is parallel with the diagonal line of the one of those pixels,
Wherein the 4th of the hexagon while with the hexagon first while it is parallel and parallel with pentagonal first side,
Wherein the 5th of the hexagon while with the hexagon second while it is parallel and parallel with pentagonal second side,
Wherein the 6th of the hexagon is parallel while with the third of the hexagon.
8. display device as claimed in claim 7, wherein those second circuit areas are the multiple of corresponding driving multiple data lines
Multiplexing controller, one of those multiplexing controllers include a power supplying line, the 5th side of the power supplying line and the hexagon
It is adjacent.
9. a kind of display device, comprising:
Viewing area has the multiple pixels being located on a substrate；And
Neighboring area is located on the outside of the viewing area, the neighboring area include multiple first circuit regions on the substrate with it is multiple
Second circuit area, those first circuit regions drive those pixels according to a first direction, those second circuits Qu Yiyi second direction
Drive those pixels；
Wherein at least one of one of one of those first circuit regions and those second circuit areas are a heptagon, heptagon tool
Have sequentially connected first while, second while, third while, the 4th while, the 5th while, the 6th while, with the 7th side,
Wherein heptagonal first side is parallel with the second direction,
Wherein heptagonal second side is parallel with the first direction,
Wherein heptagonal 4th side substrate edges corresponding with the heptagon are substantial parallel, and this heptagonal 4th
The length on side is greater than the length of at least one of side of those pixels,
Wherein this heptagonal 6th while with this heptagonal first while it is parallel, and
Wherein this heptagonal 7th while with this heptagonal second while it is parallel.
10. display device as claimed in claim 9, wherein outermost pixel in heptagonal first side and the viewing area
One first side it is adjacent, in heptagonal second side and the viewing area side of both the of outermost pixel
It is adjacent, and heptagonal 6th side is adjacent with the side of the third party of outermost pixel in the viewing area, and the heptagon
The 7th side it is adjacent with the second side of one of outermost pixel in the viewing area.
11. display device as claimed in claim 9, wherein those pixels are rectangles, the first direction is perpendicular to the second party
To each of first circuit region drives single-row pixel, and the pixel of each of second circuit area driving at least a line.
12. display device as claimed in claim 9, wherein the viewing area is substantially rounded.
13. display device as claimed in claim 9, wherein those first circuit regions are the multiple of corresponding driving multi-strip scanning line
Shift registor, one of those shift registors include a power supplying line, the power supplying line and heptagonal 4th side
It is adjacent, and the substrate edges corresponding with the heptagon are substantial parallel.
14. display device as claimed in claim 9, wherein those first circuit regions are the multiple of corresponding driving multi-strip scanning line
Shift registor, one of those shift registors include a power supplying line, the power supplying line and heptagonal 5th side
It is adjacent.
15. display device as claimed in claim 9, wherein those first circuit regions are the multiple of corresponding driving multi-strip scanning line
Shift registor, one of those shift registors include a power supplying line, the power supplying line and heptagonal first side
It is adjacent and adjacent with heptagonal 7th side.
16. display device as claimed in claim 9, wherein in one of one of those first circuit regions and those second circuit areas
Another one be a hexagon, and be located between the heptagon and the viewing area,
Wherein the hexagon have sequentially connected first while, second while, third while, the 4th while, the 5th while, with the 6th while,
Wherein the first side of the hexagon is parallel with the second direction, and the side with the one of outermost pixel in the viewing area
Side is adjacent,
Wherein the second side of the hexagon is parallel with the first direction, and the side with the another one of pixel outermost in viewing area
Side is adjacent,
Wherein the third side of the hexagon is parallel with the diagonal line of the one of those pixels,
Wherein the 4th of the hexagon while with the hexagon first while it is parallel and adjacent with heptagonal first side,
Wherein the 5th of the hexagon while with the hexagon second while it is parallel and adjacent with heptagonal 7th side,
Wherein the 6th of the hexagon is parallel while with the third of the hexagon.
17. display device as claimed in claim 16, wherein those second circuit areas are the more of corresponding driving multiple data lines
A multiplexing controller, one of those multiplexing controllers include a power supplying line, the power supplying line and the 5th of the hexagon
Side is adjacent.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201462082672P | 2014-11-21 | 2014-11-21 | |
| US62/082,672 | 2014-11-21 |
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| Publication Number | Publication Date |
|---|---|
| CN105989788A CN105989788A (en) | 2016-10-05 |
| CN105989788B true CN105989788B (en) | 2019-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510085306.6A Active CN105989788B (en) | 2014-11-21 | 2015-02-17 | Display device |
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| CN (1) | CN105989788B (en) |
| TW (1) | TWI570683B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034218A (en) * | 2006-03-06 | 2007-09-12 | 日本电气株式会社 | Display apparatus |
| CN101290550A (en) * | 2007-04-19 | 2008-10-22 | 三星Sdi株式会社 | Display for a keypad and electronic device having the same |
| JP2009092981A (en) * | 2007-10-10 | 2009-04-30 | Epson Imaging Devices Corp | Display panel |
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| JP4003714B2 (en) * | 2003-08-11 | 2007-11-07 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
| TWI267058B (en) * | 2004-10-08 | 2006-11-21 | Ind Tech Res Inst | Non-rectangular display device |
| CN103559838B (en) * | 2008-05-11 | 2016-03-23 | Nlt科技股份有限公司 | The pel array of non-rectangle and there is the display device of this array |
| JP5112961B2 (en) * | 2008-06-11 | 2013-01-09 | 三菱電機株式会社 | Display device |
| TWI504969B (en) * | 2014-10-27 | 2015-10-21 | Au Optronics Corp | Display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101034218A (en) * | 2006-03-06 | 2007-09-12 | 日本电气株式会社 | Display apparatus |
| CN101290550A (en) * | 2007-04-19 | 2008-10-22 | 三星Sdi株式会社 | Display for a keypad and electronic device having the same |
| JP2009092981A (en) * | 2007-10-10 | 2009-04-30 | Epson Imaging Devices Corp | Display panel |
Also Published As
| Publication number | Publication date |
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| CN105989788A (en) | 2016-10-05 |
| TW201619941A (en) | 2016-06-01 |
| TWI570683B (en) | 2017-02-11 |
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