CN105988732B - Method for reading data, memorizer control circuit unit and memory storage apparatus - Google Patents

Method for reading data, memorizer control circuit unit and memory storage apparatus Download PDF

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Publication number
CN105988732B
CN105988732B CN201510096002.XA CN201510096002A CN105988732B CN 105988732 B CN105988732 B CN 105988732B CN 201510096002 A CN201510096002 A CN 201510096002A CN 105988732 B CN105988732 B CN 105988732B
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serial data
data
decoded
control circuit
those
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CN105988732A (en
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林纬
王天庆
赖国欣
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The present invention provides a kind of method for reading data, memorizer control circuit unit and memory storage apparatus.Method for reading data of the invention, including received from host system and read instruction；The first reading instruction sequence is sent according to instruction is read to obtain the first serial data from multiple storage units of reproducible nonvolatile memorizer module；Error correction translator is executed to the first serial data and has decoded the first serial data to generate；And, if having decoded in the first serial data and having had error bit, it sends second and reads instruction sequence to obtain the second serial data from these storage units, logical operation is carried out to the first serial data and the second serial data has been decoded to obtain adjustment serial data, has decoded the first serial data according to adjustment serial data adjustment to obtain and adjust the first serial data, and to adjusted the first serial data execute error correction translator again and using serial data obtained after decoding as having decoded the first serial data.The present invention can provide reading data correctness.

Description

Method for reading data, memorizer control circuit unit and memory storage apparatus
Technical field
The invention relates to a kind of method for reading data more particularly to a kind of method for reading data, memory control electricity Road unit and memory storage apparatus.
Background technique
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, so that consumer is to storage The demand of media also rapidly increases.Since reproducible nonvolatile memorizer module (for example, flash memory) has data non-volatile It is property, power saving, small in size, and without characteristics such as mechanical structures, so being very suitable to be built in above-mentioned illustrated various portable In multimedia device.
In general, the data of write-in to reproducible nonvolatile memorizer module all can be according to an error correcting code To encode, and read data will also pass through corresponding program to translate from reproducible nonvolatile memorizer module Code.However, the corrigendum ability of error correcting code has its upper limit.For example, if using turbine code algorithm or low-density parity inspection Correcting code algorithm implements error correcting code by iterative manner, after increasing to certain number with the number of iterative decoding, It will appear the phenomenon that error bit number is not reduced with the increase of the number of iterations in subsequent iterative decoding process.This phenomenon Referred to as mistake saturation (error floor).
Base this, how read data are successfully decoded, are art technology to obtain initial data The target that personnel are endeavoured.
Summary of the invention
The present invention provides a kind of method for reading data, memorizer control circuit unit and memory storage apparatus, can subtract The generation of few mistake saturation and the correctness for increasing reading data.
One embodiment of the invention provides one kind for method for reading data, is used for type nonvolatile mould Block, wherein the reproducible nonvolatile memorizer module includes multiple storage units；The method for reading data include from Host system, which receives, reads instruction, wherein multiple first storage units for reading instruction instruction from those storage units are read Access evidence；It sends first and reads instruction sequence to obtain the first serial data from those first storage units；And to described One serial data executes error correction translator and has decoded the first serial data to generate；If the method for reading data further includes institute State and decoded in the first serial data inerrancy position, using it is described decoded the first serial data as correction data and sent to it is described Host system is to respond the reading instruction；And if described decoded has error bit in the first serial data, sends second and read Instruction fetch sequence has decoded the first serial data and the second number to obtain the second serial data from those first storage units, to described Logical operation is carried out to obtain adjustment serial data according to string, has decoded the first serial data according to adjustment serial data adjustment to obtain It has adjusted the first serial data, and first serial data that adjusted is executed by the error correction translator again and will be translated Serial data conduct obtained is described after code has decoded the first serial data.
In one embodiment of this invention, wherein above-mentioned transmission it is described first read instruction sequence with from those first storage The step of first serial data is obtained in unit includes reading instruction sequence according to described first to read voltage reading using first Those first storage units are taken to obtain first serial data from those first storage units；In addition, described in above-mentioned transmission Second reading instruction sequence is to include according to described the step of obtaining second serial data from those first storage units Second reading instruction fetch sequence reads those first storage units using the second reading voltage to obtain from those first storage units Second serial data, wherein the voltage value that the described second voltage value for reading voltage reads voltage not equal to described first.
In one embodiment of this invention, above-mentioned transmission described first reads instruction sequence with from those the first storage units The step of middle acquisition first serial data includes: to read instruction sequence according to described first to read voltage reading using one first Those first storage units from those first storage units to obtain first serial data；Wherein above-mentioned transmission described second Instruction sequence is read to include: to read the step of obtaining second serial data from those first storage units according to described second Instruction fetch sequence reads those first storage units using one second reading voltage to obtain institute from those first storage units The second serial data is stated, wherein the voltage value that the described second voltage value for reading voltage reads voltage not equal to described first.
In one embodiment of this invention, wherein first serial data and second serial data are carried out the logic Operation includes carrying out mutual exclusion fortune to first serial data and second serial data to obtain the step of the adjustment serial data It calculates to generate the adjustment serial data.
In one embodiment of this invention, wherein above-mentioned decoded the first data according to described in adjustment serial data adjustment String includes that described decoded of identification multiple among the first serial data can not know to obtain described the step of having adjusted the first serial data Other data can not identify that the multiple of data can not identify data address with corresponding those, and using right in the adjustment serial data It is mutual can not should to identify that the data of data address can not identify that data carry out to those for having decoded in the first serial data a bit Reprimand operation described has decoded the first serial data to adjust to obtain and described adjust the first serial data.
In one embodiment of this invention, the method for reading data further includes that record has adjusted the first data to described String executes the number of the error correction translator；And if transmission error message is extremely when the number is greater than pre-determined number The host system.
In one embodiment of this invention, wherein executing the error correction translator to first serial data to produce Raw described the step of having decoded the first serial data includes that the error correction translator is executed using block turbine code algorithm.
In one embodiment of this invention, wherein executing the error correction decoding using the block turbine code algorithm The step of program includes odd using Bo Si-Qiao Heli-Huo Ke algorithm or low-density to first serial data by iterative manner The even final decoding result for checking correcting code algorithm and obtaining corresponding first serial data as additional interpretations algorithm；And The first serial data has been decoded using the final decoding result as described.
One embodiment of the invention provides a kind of memorizer control circuit unit, and for controlling, duplicative is non-volatile to be deposited Memory modules；The memorizer control circuit unit includes host interface, memory interface and memory management circuitry；The master Machine interface is electrically connected to host system；It is non-volatile that the memory interface is electrically connected to the duplicative Memory module, wherein the reproducible nonvolatile memorizer module has multiple storage units；The memory management Circuit is electrically connected to the host interface and the memory interface；The memory management circuitry is to from the host system System, which receives, reads instruction, wherein multiple first storage units for reading instruction instruction from those storage units read number According to；The memory management circuitry is also to send the first reading instruction sequence to obtain first from those first storage units Serial data, and error correction translator is executed to first serial data and has decoded the first serial data to generate；If described Inerrancy position is decoded in the first serial data, memory management circuitry is also to using first serial data that decoded as Correction data sends the host system to respond the reading instruction；If having decoded in the first serial data and having had error bit, The memory management circuitry is also to send the second reading instruction sequence to obtain the second number from those first storage units According to string, to first serial data and second serial data progress logical operation of having decoded to obtain adjustment serial data, foundation The adjustment serial data adjustment is described to have decoded the first serial data to obtain and adjust the first serial data, and has adjusted to described First serial data executes the error correction translator again and has decoded using serial data obtained after decoding as described First serial data.
In one embodiment of this invention, the memory management circuitry also to send the first reading instruction sequence with From the running for obtaining first serial data in these first storage units, the memory management circuitry is according to described first It reads instruction sequence and reads those first storage units using the first reading voltage to obtain institute from those first storage units State the first serial data；Wherein the memory management circuitry also to send it is described second read instruction sequence with from those first In the running for obtaining second serial data in storage unit, the memory management circuitry reads sequence of instructions according to described second Column read those first storage units using the second reading voltage to obtain second data from those first storage units String, wherein the voltage value that the described second voltage value for reading voltage reads voltage not equal to described first.
In one embodiment of this invention, the memory management circuitry by it is described decoded the first serial data with it is described Second serial data carries out the logical operation to obtain in the running of the adjustment serial data, and the memory management circuitry is to institute It states and has decoded the first serial data and the second serial data progress exclusion operation to generate the adjustment serial data.
In one embodiment of this invention, described according to adjustment serial data adjustment in the memory management circuitry Decode the first serial data with obtain it is described adjusted in the running of the first serial data, the memory management circuitry identification is described Decode among the first serial data multiple can not identify that data can not identify that the multiple of data can not identify data with corresponding those Address, and the has been decoded to described by using data that those can not identify data address are corresponded in the adjustment serial data Those in one serial data, which can not identify, data to carry out exclusion operation described to have decoded the first serial data described to obtain to adjust The first serial data is adjusted.
In one embodiment of this invention, the memory management circuitry record executes first serial data that adjusted The number of the error correction translator；And if the memory management circuitry passes when the number is greater than pre-determined number Send error message to the host system.
In one embodiment of this invention, in the memory management circuitry also to execute institute to first serial data State error correction translator with generate it is described decoded in the running of the first serial data, the memory management circuitry uses area Block turbine code algorithm executes the error correction translator.
In one embodiment of this invention, it is executed in the memory management circuitry using the block turbine code algorithm In the running of the error correction translator, the memory management circuitry makes first serial data by iterative manner Bo Si-Qiao Heli-Huo Ke algorithm or low-density parity is used to check correcting code algorithm as additional interpretations algorithm to obtain corresponding institute The final decoding of the first serial data is stated as a result, and having decoded the first serial data using the final decoding result as described.
One embodiment of the invention provides a kind of memory storage apparatus comprising connecting interface unit, duplicative are non- Volatile and memorizer control circuit unit, the connecting interface unit are electrically connected to host system； The reproducible nonvolatile memorizer module has multiple storage units；The memorizer control circuit unit is electrically connected To the connecting interface unit and the reproducible nonvolatile memorizer module；The memorizer control circuit unit to It is received from the host system and reads instruction, wherein multiple first storages for reading instruction instruction from those storage units Unit reads data；Wherein the memorizer control circuit unit also to send the first reading instruction sequence with from those first The first serial data is obtained in storage unit, and the error correction translator is executed to generate to first serial data Decode the first serial data；If having decoded in the first serial data inerrancy position, the memorizer control circuit unit will be also to will It is described to have decoded the first serial data as correction data and send the host system to respond readings and instruct；And If described decoded has error bit in the first serial data, the memorizer control circuit unit also refers to send the second reading It enables sequence to obtain the second serial data from those first storage units, has decoded the first serial data and second number to described According to string carry out logical operation to obtain adjustment serial data, according to the adjustment serial data adjustment described in decoded the first serial data with Acquisition has adjusted the first serial data, and to it is described adjusted the first serial data execute the error correction translator again and The first serial data has been decoded using serial data obtained after decoding as described.
In one embodiment of this invention, in the memorizer control circuit unit also to send the first reading sequence of instructions Column are with from the running for obtaining first serial data in those first storage units, the memorizer control circuit unit foundation The first reading instruction sequence reads voltage using first and reads those first storage units with from those the first storage units It is middle to obtain first serial data；In addition, in the memorizer control circuit unit also to send the second reading instruction sequence With from the running for obtaining the second serial data in those first storage units, the memorizer control circuit unit is according to described Second reading instruction fetch sequence reads those first storage units using the second reading voltage to obtain from those first storage units Second serial data, wherein the voltage value that the described second voltage value for reading voltage reads voltage not equal to described first.
In one embodiment of this invention, the memorizer control circuit unit by it is described decoded the first serial data with In running of the second serial data progress logical operation to obtain the adjustment serial data, the memorizer control circuit unit To first serial data and second serial data progress exclusion operation of having decoded to generate the adjustment serial data.
In one embodiment of this invention, institute is adjusted according to the adjustment serial data in the memorizer control circuit unit State decoded the first serial data with obtain it is described adjusted in the running of the first serial data, the memorizer control circuit unit is known Not it is described decoded among the first serial data it is multiple can not identify data with it is corresponding these can not identify that the multiple of data can not know Other data address, and by using corresponded in the adjustment serial data data that these can not identify data address to it is described Those for decoding in the first serial data can not identify that data carry out exclusion operation to adjust and described decode the first serial data to obtain The first serial data has been adjusted described in obtaining.
In one embodiment of this invention, the memorizer control circuit unit record has adjusted the first serial data to described Execute the number of the error correction translator；And if the number is greater than pre-determined number, the memorizer control circuit Unit transmits error message to the host system.
In one embodiment of this invention, in the memorizer control circuit unit also to be held to first serial data The row error correction translator with generate it is described decoded in the running of the first serial data, the memorizer control circuit list Member executes the error correction translator using block turbine code algorithm.
In one embodiment of this invention, come in the memorizer control circuit unit using the block turbine code algorithm In the running for executing the error correction translator, the memorizer control circuit unit is by iterative manner to described first Serial data uses Bo Si-Qiao Heli-Huo Ke algorithm or low-density parity to check correcting code algorithm as additional interpretations algorithm to obtain The final decoding of first serial data must be corresponded to as a result, and will finally decode result as described and decode the first data String.
Based on above-mentioned, method for reading data, memorizer control circuit unit and memory storage dress provided by the present invention Set, in addition to can use using block turbine code make error correction coding to protect data, can also during decoding, The decoding data that fails is decoded again successfully to decode and read data, Jin Erzeng by reading again data Into the correctness of reading data and for the protective capability of the data stored.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the host system of one embodiment of the invention and the schematic diagram of memory storage apparatus；
Fig. 2 is the schematic diagram of the computer of one embodiment of the invention, input/output device and memory storage apparatus；
Fig. 3 is the host system of one embodiment of the invention and the schematic diagram of memory storage apparatus；
Fig. 4 is the schematic block diagram of memory storage apparatus shown in FIG. 1；
Fig. 5 is the schematic block diagram of the reproducible nonvolatile memorizer module of one embodiment of the invention；
Fig. 6 is the error checking of one embodiment of the invention and the schematic diagram of correcting code frame；
Fig. 7 is the schematic diagram that error correction coded program is carried out using block turbine code of one embodiment of the invention；
Fig. 8~Figure 17 is the signal that error correction translator is carried out using block turbine code of one embodiment of the invention Figure；
Figure 18 is the flow chart of the method for reading data of one embodiment of the invention.
Description of symbols:
11: host system；
12: computer；
122: microprocessor；
124: random access memory；
13: input/output device；
126: system bus；
128: data transmission interface；
21: mouse；
22: keyboard；
23: display；
24: printer；
25: portable disk；
26: storage card；
27: solid state hard disk；
31: digital camera；
32:SD card；
33:MMC card；
34: memory stick；
35:CF card；
36: embedded storage device；
10: memory storage apparatus；
402: connecting interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory management circuitry；
504: host interface；
506: memory interface；
508: buffer storage；
510: electric power management circuit；
512: error checking and correcting circuit；
ECCF1: error checking and correcting code frame；
ECC1: error checking and correcting code；
UD: data；
DB1~DB32: data block；
RG1~RG4, CG1~CG8: data group；
BCH1~BCH12: error-correcting code；
700,710,711,712,713,714,720,730,740,741,742: data matrix；
1200: can not identify data；
1400: correspondence can not identify the data of data address；
S1801, S1803, S1805, S1807, S1809, S1811: the step of method for reading data.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) includes duplicative non-volatile memories Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is used together with host system, so that host System can write data into memory storage apparatus or read from memory storage apparatus data.
Fig. 1 is the host system of one embodiment of the invention and the schematic diagram of memory storage apparatus, and Fig. 2 is this hair The schematic diagram of the computer of a bright embodiment, input/output device and memory storage apparatus.
Fig. 1 is please referred to, host system 11 generally comprises computer 12 and input/output (input/output, abbreviation I/O) Device 13.Computer 12 includes microprocessor 122, random access memory (random access memory, abbreviation RAM) 124, system bus 126 and data transmission interface 128.Input/output device 13 includes the mouse 21 such as Fig. 2, keyboard 22, display Device 23 and printer 24.It will be appreciated that the unrestricted input/output device 13 of device shown in Fig. 2, input/output device 13 may also include other devices.
In one embodiment, memory storage apparatus 10 is by the other of data transmission interface 128 and host system 11 Component is electrically connected.It can be by data by the running of microprocessor 122, random access memory 124 and input/output device 13 Write-in reads data to memory storage apparatus 10 or from memory storage apparatus 10.For example, memory storage apparatus 10 can Be portable disk 25 as shown in Figure 2, storage card 26 or solid state hard disk (Solid State Drive, abbreviation SSD) 27 it is equal can Manifolding formula non-volatile memory storage device.
Fig. 3 is the host system of one embodiment of the invention and the schematic diagram of memory storage apparatus.
In general, host system 11 is substantially to cooperate with memory storage apparatus 10 with any system of storing data System.Although in the present embodiment, host system 11 is explained with computer system, however, in another embodiment, host system System 11 can be the systems such as digital camera, video camera, communication device, audio player or video player.For example, in host system System be digital camera (video camera) 31 when, type nonvolatile storage device be then its used SD card 32, Mmc card 33, memory stick (memory stick) 34, CF card 35 or embedded storage device 36 (as shown in Figure 3).Embedded storage Device 36 includes embedded multi-media card (Embedded MMC, abbreviation eMMC).It is noted that embedded multi-media card is Directly it is electrically connected on the substrate of host system.
Fig. 4 is the schematic block diagram of memory storage apparatus shown in FIG. 1.
Referring to figure 4., memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with Reproducible nonvolatile memorizer module 406, wherein reproducible nonvolatile memorizer module 406 is wiped with multiple entities Except unit 410 (0)~410 (N).
In the present embodiment, connecting interface unit 402 is compatible with serial advanced attachment (Serial Advanced Technology Attachment, abbreviation SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface Unit 402 is also possible to meet parallel advanced attachment (Parallel Advanced Technology Attachment, abbreviation PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, abbreviation IEEE) 1394 standards, high speed peripheral component connecting interface (Peripheral Component Interconnect Express, abbreviation PCI Express) standard, universal serial bus (Universal Serial Bus, Abbreviation USB) standard, secure digital (Secure Digital, abbreviation SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, abbreviation UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, abbreviation UHS-II) interface mark Quasi-, memory stick (Memory Stick, abbreviation MS) interface standard, multimedia storage card (Multi Media Card, abbreviation MMC) Interface standard, built-in multimedia storage card (Embedded Multimedia Card, abbreviation eMMC) interface standard, general sudden strain of a muscle Deposit (Universal Flash Storage, abbreviation UFS) interface standard, compact flash (Compact Flash, abbreviation CF) connects Mouth standard, integrated driving electrical interface (Integrated Device Electronics, abbreviation IDE) standard or other suitable Standard.Connecting interface unit 402 can be encapsulated in memorizer control circuit unit 404 in a chip or connecting interface Unit 402 is laid in outside a chip comprising memorizer control circuit unit 404.
Memorizer control circuit unit 404 is to execute in the form of hardware or multiple logic gates of software form implementation or control System instruction, and writing for data is carried out in reproducible nonvolatile memorizer module 406 according to the instruction of host system 11 Enter, read and the runnings such as erasing.
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and uses The data being written with host system 11.Reproducible nonvolatile memorizer module 406 can be single-order storage unit (Single Level Cell, abbreviation SLC) NAND-type flash memory module, multi-level cell memory (Multi Level Cell, abbreviation MLC) NAND-type flash memory module (that is, flash memory module that 2 bit datas can be stored in a storage unit), Complex Order storage unit (Triple Level Cell, abbreviation TLC) NAND-type flash memory module is (that is, can store 3 bit datas in a storage unit Flash memory module), other flash memory modules or other memory modules with the same characteristics.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit of one embodiment of the invention.
Referring to figure 5., memorizer control circuit unit 404 includes memory management circuitry 502, host interface 504, storage Device interface 506, buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.
Overall operation of the memory management circuitry 502 to control memorizer control circuit unit 404.Specifically, it deposits Reservoir, which manages circuit 502, has multiple control instructions, and when memory storage apparatus 100 operates, these control instruction meetings It is performed to carry out the running such as the write-in of data, reading and erasing.
In the present embodiment, the control instruction of memory management circuitry 502 is to exist in a software form.For example, memory Managing circuit 502 has microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions be by Burning is so far in read-only memory.When memory storage apparatus 100 operate when, these control instructions can by microprocessor unit Lai It executes and is operated with the write-in, reading and erasing etc. that carry out data.
In an alternative embodiment of the invention, the control instruction of memory management circuitry 502 can also be deposited with program code pattern The specific region of reproducible nonvolatile memorizer module 406 is stored in (for example, being exclusively used in storage system number in memory module According to system area) in.In addition, there is memory management circuitry 502 microprocessor unit (not shown), read-only memory (not to show Out) and random access memory (not shown).In particular, this read-only memory has driving code, and when memory control electricity When road unit 404 is enabled, microprocessor unit, which can first carry out this driving code section, will be stored in that duplicative is non-volatile to be deposited Control instruction in memory modules 406 is loaded onto the random access memory of memory management circuitry 502.Later, micro process The running such as write-in, reading and erasing that device unit can operate these control instructions to carry out data.
In addition, in an alternative embodiment of the invention, the control instruction of memory management circuitry 502 can also be with an example, in hardware Carry out implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write circuit, deposits Reservoir reading circuit, memory erasing circuit and data processing circuit.Storage Unit Management circuit, is deposited at memory write circuit Reservoir reading circuit, memory erasing circuit and data processing circuit are electrically connected to microcontroller.Wherein, storage unit tube Reason circuit wipes unit to manage the entity of reproducible nonvolatile memorizer module 406；Memory write circuit to Write instruction is assigned to reproducible nonvolatile memorizer module 406 to write data into duplicative non-volatile memories In device module 406；Memory reading circuitry to reproducible nonvolatile memorizer module 406 assign reading instruction with from Data are read in reproducible nonvolatile memorizer module 406；Memory erasing circuit is to non-volatile to duplicative Memory module 406 assigns erasing instruction to wipe data from reproducible nonvolatile memorizer module 406；And data Processing circuit to handle be intended to be written data to reproducible nonvolatile memorizer module 406 and from duplicative it is non-easily The data read in the property lost memory module 406.
Host interface 504 is electrically connected to memory management circuitry 502 and to receive and identification host system 1000 instructions and data transmitted.That is, the instruction that host system 1000 is transmitted can be connect with data by crossing host Mouthfuls 504 are sent to memory management circuitry 502.In the present embodiment, host interface 504 is compatible with SATA standard.However, It must be appreciated that the invention is not limited thereto, host interface 504 can also be compatible with PATA standard, 1394 standard of IEEE, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standard.
Memory interface 506 is electrically connected to memory management circuitry 502 and non-volatile to access duplicative Property memory module 406.It can be by depositing to the data of reproducible nonvolatile memorizer module 406 that is, being intended to be written Memory interface 506 is converted to the 406 receptible format of institute of reproducible nonvolatile memorizer module.Specifically, if storage When device management circuit 502 will access reproducible nonvolatile memorizer module 406, memory interface 506 can transmit corresponding Instruction sequence.These instruction sequences may include one or more signals, or the data in bus.For example, reading sequence of instructions In column, it will include the information such as identification code, the storage address of reading.
Buffer storage 508 is electrically connected to memory management circuitry 502 and is configured to temporarily store from host system 1000 data and instruction or the data from reproducible nonvolatile memorizer module 406.Memorizer control circuit list Member 404 is kept in non-volatile from the data of host system 1000 or from duplicative in advance in buffer storage 508 Property memory module 406 data and be written to so that data organization is at predetermined unit size or becomes transmission unit size Reproducible nonvolatile memorizer module 406 or pass back to host system.It is deposited in addition, buffer storage 508 can also be kept in Systems management data used in memory control circuit unit 404, for example, data configuration table or logic-unit mapping table etc..
Electric power management circuit 510 is electrically connected to memory management circuitry 502 and to control memory storage dress Set 100 power supply.
Error checking and correcting circuit 512 are electrically connected to memory management circuitry 502 and to execute wrong inspection It looks into and correction program is to ensure the correctness of data.Specifically, when memory management circuitry 502 connects from host system 1000 When receiving write instruction, error checking can execute error correction coding with correcting circuit 512 for the data of this corresponding write instruction Program is to generate corresponding error-correcting code (error correcting code, abbreviation ECC code) and/or error checking code (error detecting code, abbreviation EDC), and memory management circuitry 502 can be by the data of this corresponding write instruction It is written with corresponding error-correcting code or error checking code into reproducible nonvolatile memorizer module 406.Later, when depositing Reservoir management circuit 502 can read this data pair when reading data from reproducible nonvolatile memorizer module 406 simultaneously The error-correcting code and/or error checking code answered, and error checking and correcting circuit 512 can according to this error-correcting code and/ Or error checking code executes error correction translator to read data.
As described above, the error checking in memory storage apparatus 100 can be configured to verify and can answer with correcting circuit 512 Whether correct write the data stored in formula non-volatile memory module 406.However, when executing error-correcting routine, nothing By being coding or decoding procedure, error checking and correcting circuit 512 are all to need to be clear from claimed data length to be What, so can just calculate correct condition code, to check correct errors present, and then position of righting the wrong.In this implementation In example, when memorizer control circuit unit 404 (or memory management circuitry 502) receives data, memorizer control circuit Data first can be divided into multiple yards of frames (frame), later error checking and school by unit 404 (or memory management circuitry 502) Positive circuit 512 carries out error correction coded program to generate the corresponding error-correcting code of each code frame, by these yard of frame and its again Respectively corresponding error-correcting code, which is separately encoded, is formed as error checking and correcting code frame.Here, error checking and correcting code The size of frame is to be divided according to the size of unit of transfer, and the size of this unit of transfer is deposited according to duplicative is non-volatile The specifications of memory modules 406 determine.That is, each unit of transfer must protect (protect) how many a positions (bit). For example, unit of transfer is 512bytes, 12 positions, memorizer control circuit unit 404 (or memory management circuitry 502) are protected It is 512bytes that data can be cut into per unit.And error checking and correcting circuit 512 can then be directed to the number of every 512bytes According to progress error correction coded program, therefore the size of each error checking and correcting code frame is exactly 512bytes.But it have to be understood that , the invention is not limited thereto, in another embodiment, the size of error checking and correcting code frame can also be 1K bytes or 2K bytes etc..
In the present embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can with error checking with Correcting code frame be unit come to data decoding to read data.As an example it is assumed that memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) reading instruction is received from host system, it is deposited wherein reading instruction instruction from duplicative is non-volatile Data are read in multiple storage units (also referred to as, the first storage unit) in memory modules 406.In this example, it is assumed that this The data to be read are divided into 1 error checking and correcting code frame, and are stored in these first storage units.Memory control Circuit unit 404 (or memory management circuitry 502) processed, which can send, reads instruction sequence (also referred to as, first reading instruction sequence) extremely Reproducible nonvolatile memorizer module 406 is with from these of the error checking of the corresponding data to be read of storage and correcting code frame In first storage unit obtain serial data (also referred to as, the first serial data), to the first serial data execute error correction translator with The successfully decoded correction data of corresponding data to be read is generated, and sends correction data to host system to respond Read instruction.It should be noted that if the data to be read are divided into 2 or more error checking and correcting code frames, memory Control circuit unit 404 (or memory management circuitry 502) can read the serial data of corresponding each error checking and correcting code frame, Error correction translator, and the merging data after successfully correcting read serial data are carried out to read serial data It conspires to create as correction data and is sent to host system to respond reading instruction.
It in the present embodiment, is block turbine code (block turbo used in error checking and correcting circuit 512 Code, abbreviation BTC) Lai Jinhang error correction coding/decoding program.
Fig. 6 is the error checking of one embodiment of the invention and the schematic diagram of correcting code frame, and Fig. 7 is of the invention one The schematic diagram that error correction coded program is carried out using block turbine code of embodiment.It will be appreciated that being described herein mistake When checking with correcting circuit 512 to the runnings of data, the words such as " selection ", " segmentation ", " division ", " association ", " arrangement " are logics On concept.That is, error checking and the storage location of data handled by correcting circuit 512 itself are not changed, and It is that data are operated in logic.
Please refer to Fig. 6, it is assumed that error checking and correcting circuit 512 carry out error correction coded program, and number to data UD It is divided into 1 error checking and correcting code frame ECCF1 according to UD to carry out error correction coded program, wherein error checking and school Code frame ECCF1 is stored in multiple storage units (also referred to as, the first storage unit).In the present embodiment, error checking with Correcting circuit 512 will use block turbine code algorithm to execute error correction coded program to data UD, and data UD is divided into Multiple data groups, and these data groups are encoded respectively to obtain corresponding error checking and correcting code frame ECCF1 Error-correcting code ECC1.
Please refer to Fig. 6 and Fig. 7, for example, firstly, error checking and correcting circuit 512 data UD can be divided into it is more A data block (data bits), data block DB1~DB32 as illustrated in FIG. 6.It should be noted that in the present embodiment, For ease of description, each data block includes 1 bit data, however, the present invention is not limited thereto.For example, in other embodiments, Each data block also may include the position data of 2 or more than two.
Then, data block DB1~DB32 is arranged as one 8 multiplied by 4 two dimension with correcting circuit 512 by error checking (laterally and longitudinally) data matrix, and multiple longitudinal directions and lateral data group are divided into according to dimension.For example, laterally arranging Data block DB1~DB8 of column can be divided into data group RG1；Data block DB9~DB16 can be divided into data group RG2；Data block DB17~DB24 can be divided into data group RG3；Data block DB25~DB32 can be divided into data Group RG4.In addition, data block DB1, DB9, DB17, DB25 of longitudinal arrangement can be divided into data group CG1；Data field Block DB2, DB10, DB18, DB26 can be divided into data group CG2；Data block DB3, DB11, DB19, DB27 can be divided For data group CG3；Data block DB4, DB12, DB20, DB28 can be divided into data group CG4；Data block DB5, DB13, DB21, DB29 can be divided into data group CG5；Data block DB6, DB14, DB22, DB30 can be divided into data Group CG6；Data block DB7, DB15, DB23, DB31 can be divided into data group CG7；Data block DB8, DB16, DB24, DB32 can be divided into data group CG8.
In the present embodiment, data block DB1~DB32 is being divided into lateral data group RG1~RG4 and longitudinal direction Data group CG1~CG8 after, error checking and correcting circuit 512 will use-Huo Ke yards of Bo Si-Qiao Heli (hereinafter referred to as BCH) These data groups are encoded respectively as auxiliaring coding algorithm, to generate the error correction of these corresponding data groups Code.That is, for lateral data group RG1~RG4, error checking and correcting circuit 512 can be by BCH algorithms to drawing The data (that is, data block DB1~DB8) to data group RG1 are divided to be encoded to generate the data of corresponding data group RG1 Error-correcting code BCH1.The rest may be inferred, and error checking can generate the wrong school of corresponding data group RG2 with correcting circuit 512 Code BCH2；Generate the error-correcting code BCH3 of corresponding data group RG3；Generate the error-correcting code of corresponding data group RG4 BCH4.In addition, error checking and correcting circuit 512 can also generate corresponding data group for longitudinal data group CG1~CG8 The error-correcting code BCH5 of group CG1；Generate the error-correcting code BCH6 of corresponding data group CG2；Generate corresponding data group CG3 Error-correcting code BCH7；Generate the error-correcting code BCH8 of corresponding data group CG4；Generate the mistake of corresponding data group CG5 Accidentally correcting code BCH9；Generate the error-correcting code BCH10 of corresponding data group CG6；Generate the wrong school of corresponding data group CG7 Code BCH11；Generate the error-correcting code BCH12 of corresponding data group CG8.Therefore, data group RG1~RG4 and data group Data in group CG1~CG8 can be protected by corresponding error-correcting code BCH1~BCH4 and error-correcting code BCH5~BCH12 respectively Shield.It should be noted that the present invention is not limited to use-Huo Ke yards of Bo Si-Qiao Heli to come respectively as auxiliaring coding algorithm to this A little data groups encode.For example, in another embodiment, error checking and correcting circuit 512 will use low-density parity inspection Correcting code is looked into as auxiliaring coding algorithm to encode respectively to these data groups.
It is noted that in the present embodiment, data block can first be divided to more by error checking with correcting circuit 512 A data group and then each data group is encoded to generate the error-correcting code of corresponding each data group, but The invention is not limited thereto.For example, in another embodiment, error checking can not first divide data block with correcting circuit 512 For these data groups, and error correction coding is directly made to data block according to the arrangement mode of data block.Citing For, error checking and correcting circuit 512 directly can carry out error correction coded program to data block DB1~DB8, to produce The error-correcting code BCH1 of raw corresponding data block DB1~DB8.
Fig. 6 is please referred to, in the present embodiment, error checking and correcting circuit 512 can be by error-correcting code BCH1~BCH12 Merging becomes corresponding error checking and the error checking of correcting code frame ECCF1 and correcting code ECC1, and stores and mistake is completed The error checking of correction coding program and correcting code frame ECCF1 and error checking and correcting code ECC1.Then, memory control electricity Road unit 404 (or memory management circuitry 502) can be by error checking and correcting code ECC1 to error checking and correcting code frame ECCF1 carries out error correction translator to read data UD.
Fig. 8~Figure 17 is the signal that error correction translator is carried out using block turbine code of one embodiment of the invention Figure.
Referring to Fig. 6, Fig. 7 and Fig. 8, for example, assuming that memorizer control circuit unit 404 (or memory pipe Reason circuit 502) it is received from host system and reads instruction, wherein reading instruction instruction from type nonvolatile mould Data UD is read in multiple storage units (also referred to as, the first storage unit) of block 406.Memorizer control circuit unit 404 (or deposit Reservoir manages circuit 502) it can send and read instruction sequence to obtain serial data (also referred to as, first from these first storage units Serial data).Refer to it should be noted that memorizer control circuit unit 404 (or memory management circuitry 502) can be read according to first Sequence is enabled to read these first storage units using the first reading voltage to obtain the first data from these first storage units String.
As noted previously, as data UD becomes error checking and correcting code frame by above-mentioned error correction coded program ECCF1.Therefore, in the error correction translator to data UD, error checking and the meeting of correcting circuit 512 will be from storage mistakes Check with read first serial data of the first storage unit of correcting code frame ECCF1 be divided into 32 data block DB1~ DB32, and data block DB1~DB32 is arranged in two-dimensional data matrix 710.Wherein, corresponding data block DB1~DB32 The division methods of data group be identical to the example in Fig. 7, details are not described herein.Error checking and correcting circuit 512 can be from The mistake of corresponding error checking each data group corresponding with acquisition in the error checking of correcting code frame ECCF1 and correcting code ECC1 Correcting code BCH1~BCH12.In this example, it is assumed that the protective capability of error checking and correcting circuit 512 is 1 position.It changes Yan Zhi, if there are 2 or more mistakes for the data in the data group of one of corresponding error-correcting code BCH1~BCH12 Accidentally position, error checking and correcting circuit 512 just can not the error-correcting code according to corresponding to this data group successfully decode The data of this data group.
As an example it is assumed that there are multiple error bits (site block as shown in Figure 8) in the first serial data, these Error bit is data block DB4, DB10, DB11, DB12, DB13, DB17, DB18, DB23, DB24, DB31, DB32 respectively.Such as It is upper described, it is 1 position by the protective capability of error checking and correcting circuit 512 and is formed by data block DB9~DB16 Data group RG2 error bit number be 4.Therefore, error checking and correcting circuit 512 can not be according to error-correcting codes BCH2 carrys out the data of data group RG2 corresponding to decoding error correcting code BCH2.But error checking and correcting circuit 512 But the error-correcting code that can use corresponding other data groups iteratively carries out the correction of error bit.
Assuming that error checking and correcting circuit 512 first can be formed by multiple data groups to transversely arranged data block It is decoded with the error-correcting code of these corresponding data groups, then multiple data is formed by the data block of longitudinal arrangement Group is decoded with the error-correcting code of these corresponding data groups.Referring to Fig. 7, Fig. 8 and Fig. 9, for the first time to In the error correction translator that one serial data carries out, error checking and correcting circuit 512 have carried out the ordinate iteratuin of first time Decoding.That is, error checking and correcting circuit 512 can be by error-correcting code BCH1 come decoded data blocks DB1~DB8；Pass through Error-correcting code BCH2 carrys out decoded data blocks DB9~DB16；By error-correcting code BCH3 come decoded data blocks DB17~ DB24；By error-correcting code BCH4 come decoded data blocks DB25~DB32.It should be noted that above-mentioned laterally decode or indulge It is only purposes of discussion to the sequencing of decoding, the invention is not limited thereto.
Have 1 error bit (that is, figure since data block DB1~DB8 in fig. 8 is formed by data group RG1 only Data block DB4 shown in 8), error checking can successfully pass through the wrong school of corresponding data group RG1 with correcting circuit 512 Code BCH1 decodes out the data of data group RG1.But since data block DB9~DB16 in fig. 8 is formed by Data group RG2 has 4 error bits (that is, data block DB10, DB11, DB12, DB13 depicted in Fig. 8), error checking The number of data group RG2 cannot be decoded out by the error-correcting code BCH2 of corresponding data group RG2 with correcting circuit 512 According to.In other words, data block DB10~DB13 that mistake occurs is not corrected.The rest may be inferred, by wrong school for the first time After the first time ordinate iteratuin decoding of positive translator, as shown in figure 9, error checking and correcting circuit 512 successfully correct hair The data block DB4 (being indicated with runic baseline) of raw mistake, and obtain data matrix 711.
As described above, after completing lateral decoding and obtaining data matrix 712, error checking and 512 meeting of correcting circuit Longitudinal decoding is carried out to data matrix 712.That is, error checking can be translated with correcting circuit 512 by error-correcting code BCH5 Code data block DB1, DB9, DB17, DB25；By error-correcting code BCH6 come decoded data blocks DB2, DB10, DB18, DB26；By error-correcting code BCH7 come decoded data blocks DB3, DB11, DB19, DB27；By error-correcting code BCH8 come Decoded data blocks DB4, DB12, DB20, DB28；By error-correcting code BCH9 come decoded data blocks DB5, DB13, DB21, DB29；By error-correcting code BCH10 come decoded data blocks DB6, DB14, DB22, DB30；Pass through error-correcting code BCH11 Come decoded data blocks DB7, DB15, DB23, DB31；By error-correcting code BCH12 come decoded data blocks DB8, DB16, DB24、DB32。
It is similar to above-mentioned lateral decoding, since data block DB1, DB9, DB17, DB25 in Fig. 9 are formed by number Only have 1 error bit (that is, data block DB17 shown in Fig. 9) according to group CG1, error checking and correcting circuit 512 can be at The data of data group CG1 are decoded out to function by the error-correcting code BCH5 of corresponding data group CG1.But due to Data block DB2, DB10, DB18, DB26 in Fig. 8 are formed by data group CG2 with 2 error bits (that is, Fig. 8 is drawn Data block DB10, DB18 shown), error checking and correcting circuit 512 cannot pass through the error correction of corresponding data group CG2 Code BCH6 decodes out the data of data group CG2.In other words, data block DB10, DB18 that mistake occurs is not corrected. The rest may be inferred, and after the decoding of the first time abscissa iteration of first time error correction translator, as shown in Figure 10, mistake is examined It looks into and successfully corrects data block DB4, DB11, DB12, DB13 that mistake occurs with correcting circuit 512 (with runic baseline table Show), and obtain data matrix 712.
In the first time for completing first time error correction translator laterally and longitudinally after iterative decoding, error checking with Correcting circuit 512 will continue to iteratively carry out decoding data matrix 712.In the same manner, error checking and correcting circuit 512 can be first Data matrix 712 is started to carry out lateral decoding.Referring to Figure 10 and Figure 11, due to being translated by first time error correction After the first time abscissa iteration decoding of coded program, error checking is successfully corrected with correcting circuit 512 cannot be by wrong for the first time Accidentally data block DB11, DB12, DB13 of the mistake of the first time ordinate iteratuin decoding correction of correction translator, and for Data block DB9~DB16, which is formed by data group RG2 only, has 1 error bit (that is, data block DB10).Therefore, exist In second of ordinate iteratuin decoding of the first time error correction translator of connecting, error checking and correcting circuit 512 can be with Carry out decoding data group RG2 using the error-correcting code BCH2 of corresponding data group RG2.In other words, data block DB10 can be with Successfully corrected.Figure 11 is please referred to, after the decoding of second of ordinate iteratuin of first time error correction translator, data Block DB10 is successfully corrected, error bit only data left block DB18, DB23, DB24, DB31, DB32, and generates number According to matrix 713.
Similarly, after completing second of ordinate iteratuin decoding of first time error correction translator, error checking Second of abscissa iteration decoding that will continue to carry out first time error correction translator with correcting circuit 512 carrys out decoding data square Battle array 713.Figure 10, Figure 11 and Figure 12 are please referred to, originally in Figure 10, the first time of first time error correction translator longitudinally changes Generation decoding can not correct data block DB10, DB18 that mistake occurs.But due to the of first time error correction translator Secondary ordinate iteratuin successfully decoded ground correction data block DB10, and make longitudinal arrangement data block DB2, DB10, DB18, DB26, which are formed by data group CG2 only, has 1 error bit (the data block DB18 as depicted in Figure 11).Therefore, In second of abscissa iteration decoding of first time error correction translator in Figure 12, error checking and correcting circuit 512 The data block DB18 that mistake occurs can be corrected by the error-correcting code BCH6 of corresponding data group CG2.Please refer to figure 12, after completing second of abscissa iteration decoding of first time error correction translator, error bit only data left block DB23, DB24, DB31, DB32, and produce data matrix 714.
It should be noted that being similar to above-mentioned steps, error checking and correcting circuit 512 again carry out data matrix 714 Iterative decoding laterally and longitudinally, but data block DB23, DB24, DB31, DB32 that mistake occurs still cannot be by successes Ground correction.That is, data matrix 714 is the final decoding result of this mistake decoding correction program.Error checking and school Positive circuit 512 can export data matrix 714, and memorizer control circuit unit 404 (or memory management circuitry 502) meeting The first serial data of decoding by data matrix 714 as corresponding first serial data.
Since the first serial data of decoding of the final decoding result of this error correction translator has still remained not The data block that can be successfully corrected, in the present embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) it will continue to processing and decoded the first serial data.Firstly, memorizer control circuit unit 404 (or memory management circuitry 502) judge decoded in the first serial data can not identify data with it is corresponding can not identify data can not identify data Address.Specifically, is being decoded since memorizer control circuit unit 404 (or memory management circuitry 502) can determine that The data block successfully corrected in one serial data (that is, data matrix 714) is data block DB1~DB22, DB25 ~DB30, and memorizer control circuit unit 404 (or memory management circuitry 502) can not judge data block DB23, Whether DB24, DB31, DB32 occur mistake.Therefore, memorizer control circuit unit 404 (or memory management circuitry 502) It can identify that data block DB23, DB24, DB31, DB32 are that can not identify data, and can not identify data for these are corresponded to Address is as can not identify data address 1200 (the thick frame region 1200 of black as shown in figure 12).
In the present embodiment, if having decoded when having error bit in the first serial data, memorizer control circuit unit 404 (or memory management circuitry 502) can send another reading instruction sequence (also referred to as, second read instruction sequence) with from these the One storage unit obtains serial data (also referred to as, the second serial data) again.For example, in an exemplary embodiment, memory control electricity Road unit 404 (or memory management circuitry 502) can read instruction sequence according to second and read these using the second reading voltage First storage unit from these first storage units to obtain the second serial data, and the voltage value of the second reading voltage is equal to Above-mentioned first reads the voltage value of voltage.However, it is necessary to be appreciated that, the voltage value of the second reading voltage can also be not equal to above-mentioned First reads the voltage value of voltage.For example, in another embodiment, memorizer control circuit unit 404 (or memory management electricity Road 502) the critical electricity of the first storage unit can be first detected before reading these first storage units using the second reading voltage Pressure distribution carrys out the voltage for reading voltage using appropriate second further according to testing result (e.g., the offset of critical voltage distribution) Value is to read the first storage unit, wherein the second voltage value for reading voltage can be different from the first voltage value for reading voltage.Cause This, memorizer control circuit unit 404 (or memory management circuitry 502) can relatively correctly identify the storage of the first storage unit State.It should be noted that the present invention is not limited to adjust the method for adjustment of the voltage value of the second reading voltage.For example, memory Control circuit unit 404 (or memory management circuitry 502) can be not required to be detected, and adjust table according to predetermined read voltage To adjust the voltage value of the second reading voltage.
Figure 13 is please referred to, above-mentioned steps, memorizer control circuit unit 404 (or memory management circuitry 502) are similar to Second serial data can be arranged as data matrix 720.Assuming that having multiple mistakes in the second serial data (that is, data matrix 720) Accidentally position, these error bits are data block DB4, DB10~13, DB16, DB17~DB18, DB23~DB24, DB30~DB31.
Referring to Figure 12, Figure 13 and Figure 14, memorizer control circuit unit 404 (or memory management circuitry 502) It can be to having decoded the first serial data (that is, data matrix 714) and the second data last time error correction translator is obtained String (that is, data matrix 720) does exclusion operation to obtain adjustment serial data (data matrix 730 as depicted in Figure 14), to sentence At fixed second serial data and the difference for having decoded the first serial data (oblique line data block DB16, DB30 as shown in figure 14, DB32)。
In the present embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can be according to adjustment data String adjustment has decoded the first serial data and has adjusted the first serial data to obtain.
Specifically, firstly, memorizer control circuit unit 404 (or memory management circuitry 502) can be by from having translated What the first serial data of code was recognized can not identify data and can not identify data address, correspond to nothing in adjustment serial data to recognize The data 1400 (the thick frame region 1400 of black as shown in figure 14) of method identification data address.
Then, referring to Figure 12, Figure 14 and Figure 15, memorizer control circuit unit 404 (or memory management circuitry 502) it will use and correspond to data 1400 that these can not identify data address in adjustment serial data to having decoded in the first serial data These can not identify data 1200 carry out exclusion operation with adjust decoded the first serial data become adjusted the first serial data (that is, data matrix 740 in Figure 15).In other words, memorizer control circuit unit 404 (or memory management circuitry 502) is no Adjustment can be gone to have decoded in the first serial data the data block of successful correction, but can by using the second serial data with Decoding data string can not identify the data difference in data address adjust decoded the first serial data can not identify data. Whereby, memorizer control circuit unit 404 (or memory management circuitry 502) can continue to have decoded the first serial data to adjustment (that is, data matrix 714) adjusted the first serial data (that is, data matrix 740) obtained carries out error correction translator (that is, second of error correction translator).
It has decoded the first data due to the adjustment by above-mentioned adjustment serial data referring to Figure 15 and Figure 16 and has conspired to create To have adjusted the first serial data, and there are 2 error bits in having decoded the first serial data (that is, data matrix 714) originally Data block DB25~the DB32 of (that is, data block DB31, DB32) be formed by data group become adjusted the first data Only with the data group of 1 error bit (that is, data block DB31) in string (that is, data matrix 740).That is, scheming Only data block DB24~DB32 with 1 error bit can pass through in 15 the first serial data of adjustment (data matrix 740) It is corrected using error-correcting code BCH4.Above-mentioned steps are similar to, the first time ordinate iteratuin by second of error correction After decoding, the data block DB31 that mistake occurs originally is successfully corrected, and wrong data block only data left area occurs Block DB23, DB24, and generate data matrix 741.
Referring to Figure 16 and Figure 17, it is similar to above-mentioned steps, memorizer control circuit unit 404 (or memory pipe Reason circuit 502) it will continue to carry out longitudinal decoding.After the first time abscissa iteration decoding of second of error correction, hair Data block DB23, DB24 of raw mistake is also corrected, and is generated without the data matrix 742 of any error bit.Mistake inspection It looks into the data matrix 742 for being successfully completed correction can be converted to correcting circuit 512 and has decoded the output of the first serial data.Example Such as, having decoded the first serial data is arranged in proper order by data block DB1~DB32 of decoding success.Memorizer control circuit Unit 404 (or memory management circuitry 502), which judges, has decoded whether the first serial data has error bit.Due to having decoded There is no any error bit in one serial data (that is, data matrix 742), memorizer control circuit unit 404 (or memory Management circuit 502) can will decode the first serial data as correction data and transmit correction data to host system with Instruction is read in response.
It is noted that above-mentioned will be divided into 32 data fields by read serial data from these first storage units Block and these data blocks are arranged in 8 multiplied by the mode of 4 two-dimensional data matrix is only purposes of discussion, the present invention is not limited to This.For example, in other embodiments, can be divided into from these read serial datas of the first storage unit less than 32 or Extra 32 data blocks, and the data block after these segmentations can be arranged in two dimension or three-dimensional any length and width (height) The data matrix of ratio.Then, then to multiple data groups belonging to these data blocks make error correction coding or decoding journey To obtain error-correcting code or the correction of these corresponding data groups wrong data block occurs for sequence.
It should be noted that memorizer control circuit unit 404 (or memory management circuitry 502) also will record to having adjusted First serial data executes the number of the error correction translator.If the number is greater than pre-determined number, memory control electricity Road unit 404 (or memory management circuitry 502) transmission error message responds reading instruction to host system, wherein the mistake False information can not read the reading instruction data to be read to indicate.In other words, if it is multiple by from reading again One storage unit serial data obtained is obtained with by previous wrong translator first serial data obtained that decoded Modulated entire data string cannot all be decoded successfully, memorizer control circuit unit 404 (or memory management circuitry 502) is no It reattempts adjustment and has decoded the first serial data, and stop the error correction translator to serial data obtained, and pass Send error message to host system.It should be noted that manufacturer can set the numerical value of the pre-determined number according to self-demand.
Figure 18 is the flow chart of the method for reading data of one embodiment of the invention.
Firstly, in step S1801, memorizer control circuit unit 404 (or memory management circuitry 502) is from host system System, which receives, reads instruction, wherein reading multiple first storage units of the instruction instruction from these storage units reads data.? In step S1803, memorizer control circuit unit 404 (or memory management circuitry 502) send first read instruction sequence with The first serial data is obtained from these first storage units.
In step S1805, memorizer control circuit unit 404 (or memory management circuitry 502) is to the first serial data It executes error correction translator and has decoded the first serial data to generate.The memorizer control circuit unit 404 in step S1807 (or memory management circuitry 502) judgement has decoded the first serial data with the presence or absence of error bit.
If having decoded in the first serial data inerrancy position, in step S1809, memorizer control circuit unit 404 (or Memory management circuitry 502) it the first serial data will have been decoded sends host system to as correction data and referred to responding reading It enables, and terminates whole flow process.If having decoded in the first serial data and having had error bit, in step S1811, memorizer control circuit Unit 404 (or memory management circuitry 502) sends the second reading instruction sequence to obtain the from these first storage units Two serial datas, to the first serial data and the progress logical operation of the second serial data has been decoded to obtain adjustment serial data, foundation is adjusted Serial data adjustment has decoded the first serial data and has adjusted the first serial data to obtain, and will execute again to the first serial data has been adjusted Error correction translator serial data obtained, which is used as, has decoded the first serial data, and subsequent steps S1807.
In conclusion method for reading data provided by the present invention, memorizer control circuit unit and memory storage fill It sets, making error correction coding in addition to can use block turbine code to protect data, can more pass through during decoding Data are read again decoded again to the decoding data that fails successfully to decode and read data, and then promote number According to the correctness of reading and for the protective capability of the data stored.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (18)

1. a kind of method for reading data is used for a reproducible nonvolatile memorizer module, which is characterized in that described to make carbon copies Formula non-volatile memory module includes multiple storage units, and the method for reading data includes:
One is received from a host system and reads instruction, wherein described read instruct instruction from those storage units multiple first Storage unit reads a data；
One first reading instruction sequence is sent to obtain one first serial data from those first storage units；
One error correction translator is executed to first serial data and has decoded the first serial data to generate one；
If described decoded in the first serial data inerrancy position, using first serial data that decoded as a correction data The host system is sent to respond the reading instruction；And
If described decoded has error bit in the first serial data, send one second read instruction sequence with from those first storage One second serial data is obtained in unit, to it is described decoded the first serial data and second serial data carry out a logical operation with An adjustment serial data is obtained, has adjusted first according to the first serial data has been decoded described in adjustment serial data adjustment to obtain one Serial data, and first serial data that adjusted is executed by the error correction translator again and will be obtained after decoding Serial data decoded the first serial data as described,
It is wherein above-mentioned to have decoded the first serial data to obtain and described adjust the first number according to adjustment serial data adjustment is described Include: according to the step of string
Identification is described, which have been decoded, multiple among the first serial data can not identify that data can not identify the multiple of data with corresponding those It can not identify data address；And
The first serial data has been decoded to described using the data that those can not identify data address are corresponded in the adjustment serial data In those can not identify that data carry out an exclusion operation to adjust and described decode the first serial data to obtain described adjusted First serial data.
2. method for reading data according to claim 1, which is characterized in that described to send the first reading instruction sequence To include: the step of obtaining first serial data from those first storage units
According to the first reading instruction sequence using one first read voltage read those first storage units with from those the First serial data is obtained in one storage unit,
Wherein above-mentioned transmission described second reads instruction sequence to obtain second serial data from those first storage units The step of include:
According to the second reading instruction sequence using one second read voltage read those first storage units with from those the Second serial data is obtained in one storage unit, wherein the described second voltage value for reading voltage is read not equal to described first The voltage value of voltage.
3. method for reading data according to claim 1, which is characterized in that by it is described decoded the first serial data with it is described Second serial data carries out the logical operation to obtain
To first serial data and second serial data, one exclusion operation of progress of having decoded to generate the adjustment serial data.
4. method for reading data according to claim 1, which is characterized in that the method also includes:
Record is to a number for having adjusted the first serial data and having executed the error correction translator；And
If the number is greater than a pre-determined number, one error message of transmission to the host system.
5. method for reading data according to claim 1, feature are lain in, the mistake is executed to first serial data Translator is corrected to generate described the step of having decoded the first serial data and include:
The error correction translator is executed using a block turbine code algorithm.
6. method for reading data according to claim 5, which is characterized in that executed using the block turbine code algorithm The step of error correction translator includes:
- Huo Ke yards of algorithms of one Bo Si-Qiao Heli or a low-density parity are used to first serial data by an iterative manner Check that correcting code algorithm obtains a final decoding result of corresponding first serial data as an additional interpretations algorithm；And
The first serial data has been decoded using the final decoding result as described.
7. a kind of memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, which is characterized in that The memorizer control circuit unit includes:
One host interface is electrically connected to a host system；
One memory interface, be electrically connected to it is described can make carbon copies the non-volatile memory module, wherein described can answer Formula non-volatile memory module is write with multiple storage units；And
One memory management circuitry is electrically connected to the host interface and the memory interface,
Wherein the memory management circuitry reads instruction to receive one from the host system, wherein the reading refers to Show that multiple first storage units from those storage units read a data,
Wherein the memory management circuitry is also to send one first reading instruction sequence from those first storage units One first serial data is obtained,
Wherein the memory management circuitry is also to execute an error correction translator to first serial data to generate One has decoded the first serial data,
If wherein described decoded in the first serial data inerrancy position, the memory management circuitry by described also to have decoded First serial data as one correction data send the host system to respond reading instruction,
If wherein described decoded has error bit in the first serial data, the memory management circuitry is also to send one second Instruction sequence is read to obtain one second serial data from those first storage units, has decoded the first serial data and institute to described It states the second serial data and carries out a logical operation to obtain an adjustment serial data, decoded according to described in adjustment serial data adjustment First serial data has adjusted the first serial data to obtain one, and executes the mistake again to first serial data that adjusted It corrects translator and has decoded the first serial data using serial data obtained after decoding as described,
Wherein the first serial data has been decoded to obtain according to described in adjustment serial data adjustment in the memory management circuitry In the running for having adjusted the first serial data,
Memory management circuitry identification is described decoded among the first serial data it is multiple can not identify data with it is corresponding those It can not identify that the multiple of data can not identify data address；And
The memory management circuitry can not identify the data of data address by using corresponding to those in the adjustment serial data Data, which carry out an exclusion operation and adjust and described decoded first, to be identified to those for having decoded in the first serial data Serial data described has adjusted the first serial data to obtain.
8. memorizer control circuit unit according to claim 7, which is characterized in that the memory management circuitry also Read instruction sequence to send described first with from the running for obtaining first serial data in those first storage units,
The memory management circuitry according to it is described first reading instruction sequence using one first reading voltage read those first Storage unit to obtain first serial data from those first storage units,
Wherein in memory management circuitry described above also to send the second reading instruction sequence first to deposit from those In the running for obtaining second serial data in storage unit,
The memory management circuitry according to it is described second reading instruction sequence using one second reading voltage read those first Storage unit from those first storage units to obtain second serial data, wherein described second reads the voltage value of voltage The voltage value for reading voltage not equal to described first.
9. memorizer control circuit unit according to claim 7, which is characterized in that incited somebody to action in the memory management circuitry It is described to have decoded the first serial data and second serial data carries out the logical operation to obtain the fortune of the adjustment serial data In work,
The memory management circuitry to it is described decoded the first serial data and second serial data carry out an exclusion operation with Generate the adjustment serial data.
10. memorizer control circuit unit according to claim 7, which is characterized in that the memory management circuitry note It records to a number for having adjusted the first serial data and having executed the error correction translator,
If wherein the number is greater than a pre-determined number, the memory management circuitry transmits an error message to the host System.
11. memorizer control circuit unit according to claim 7, which is characterized in that in the memory management circuitry Also to execute the error correction translator to first serial data to generate the fortune for having decoded the first serial data In work,
The memory management circuitry executes the error correction translator using a block turbine code algorithm.
12. memorizer control circuit unit according to claim 11, which is characterized in that in the memory management circuitry In the running for executing the error correction translator using the block turbine code algorithm,
The memory management circuitry uses-Huo Ke yards of a Bo Si-Qiao Heli to first serial data by an iterative manner Algorithm or a low-density parity check that correcting code algorithm obtains corresponding first serial data as an additional interpretations algorithm One final decoding as a result,
Wherein the memory management circuitry has decoded the first serial data using the final decoding result as described.
13. a kind of memory storage apparatus characterized by comprising
One connecting interface unit, is electrically connected to a host system；
One reproducible nonvolatile memorizer module, wherein the reproducible nonvolatile memorizer module has multiple deposit Storage unit；And
One memorizer control circuit unit is electrically connected to the connecting interface unit and the duplicative non-volatile memories Device module,
Wherein the memorizer control circuit unit reads instruction to receive one from the host system, wherein the reading refers to Multiple first storage units of the instruction from those storage units are enabled to read a data,
Wherein the memorizer control circuit unit is also to send one first reading instruction sequence with single from those first storages One first serial data is obtained in member,
Wherein the memorizer control circuit unit also to first serial data execute an error correction translator with It generates one and has decoded the first serial data,
If wherein described decoded in the first serial data inerrancy position, the memorizer control circuit unit will be also to will be described Decoded the first serial data as one correction data send the host system to respond reading instruction,
If wherein described decoded has error bit in the first serial data, the memorizer control circuit unit is also to send one Second reads instruction sequence to obtain one second serial data from those first storage units, has decoded the first serial data to described A logical operation is carried out to obtain an adjustment serial data with second serial data, has been translated according to described in adjustment serial data adjustment The first serial data of code has adjusted the first serial data to obtain one, and executes the mistake again to first serial data that adjusted It accidentally corrects translator and has decoded the first serial data using serial data obtained after decoding as described,
Wherein the memorizer control circuit unit according to adjustment serial data adjustment it is described decoded the first serial data with It has been adjusted in the running of the first serial data described in obtaining,
Memorizer control circuit unit identification is described decoded among the first serial data it is multiple can not identify data with it is corresponding Those can not identify that the multiple of data can not identify data address；And
The memorizer control circuit unit can not identify data address by using corresponding to those in the adjustment serial data Data can not identify that data carry out an exclusion operation and adjust described decoded to those for having decoded in the first serial data First serial data described has adjusted the first serial data to obtain.
14. memory storage apparatus according to claim 13, which is characterized in that in the memorizer control circuit unit Also to send the first reading instruction sequence to obtain the running of first serial data from those first storage units In,
The memorizer control circuit unit reads those using one first reading voltage according to the first reading instruction sequence First storage unit to obtain first serial data from those first storage units,
Wherein in the memorizer control circuit unit also to send the second reading instruction sequence first to deposit from those In the running for obtaining second serial data in storage unit,
The memorizer control circuit unit reads those using one second reading voltage according to the second reading instruction sequence First storage unit from those first storage units to obtain second serial data, wherein described second reads the electricity of voltage The voltage value that pressure value reads voltage not equal to described first.
15. memory storage apparatus according to claim 13, which is characterized in that in the memorizer control circuit unit The first serial data has been decoded and second serial data carries out the logical operation to obtain the adjustment serial data for described In running,
The memorizer control circuit unit has decoded the first serial data and second serial data, one mutual exclusion fortune of progress to described It calculates to generate the adjustment serial data.
16. memory storage apparatus according to claim 13, which is characterized in that the memorizer control circuit unit note It records to a number for having adjusted the first serial data and having executed the error correction translator,
If wherein the number is greater than a pre-determined number, the memorizer control circuit unit transmits an error message to the master Machine system.
17. memory storage apparatus according to claim 13, which is characterized in that in the memorizer control circuit unit Also to execute the error correction translator to first serial data to generate the fortune for having decoded the first serial data In work,
The memorizer control circuit unit executes the error correction translator using a block turbine code algorithm.
18. memory storage apparatus according to claim 17, which is characterized in that in the memorizer control circuit unit In the running for executing the error correction translator using the block turbine code algorithm,
The memorizer control circuit unit uses a Bo Si-Qiao Heli-suddenly to first serial data by an iterative manner Gram code algorithm or a low-density parity check that correcting code algorithm obtains corresponding first data as an additional interpretations algorithm The final decoding of the one of string as a result,
Wherein the memorizer control circuit unit has decoded the first serial data using the final decoding result as described.
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