CN105988714A - Radiation-resistant fault-tolerant SRAM (static random access memory) storage array and making method thereof - Google Patents

Abstract

The invention belongs to the field of integrated circuits, and proposes a fault-tolerant SRAM array circuit design method capable of resisting radiation when writing data, reading data and suspending use (neither reading nor writing). The present invention adds a SRAM unit for data backup at the end of each row of SRAM units used for data reading and writing in the SRAM storage array. Each SRAM unit used for data reading and writing and backup can resist radiation. When radiation occurs in writing SRAM unit data, the SRAM unit used for data backup can protect other SRAM units not writing data in the same row as the SRAM unit that is writing data from being affected by radiation. The radiation-resistant design of the SRAM cells can also protect all SRAM cells from radiation when the SRAM memory array is reading data and suspending use (neither reading nor writing).

Description

A radiation-resistant fault-tolerant SRAM memory array and its preparation method

technical field

The invention belongs to the field of integrated circuits, and in particular relates to a radiation-resistant and fault-tolerant SRAM storage array and a preparation method thereof.

Background technique

According to research, with the reduction of process size, integrated circuits in chips are more and more susceptible to errors caused by heavy particle or proton radiation in high-level space or near-earth space. If the radiation occurs in the storage node of a storage unit such as SRAM (Static Random Access Memory), it may directly cause the storage unit to store wrong values and generate a single event upset event. If the radiation occurs at the combinational circuit node, it may cause a single event transient pulse, which changes the logic state of the circuit node, and the error value conduction memory caused by the single event transient pulse may or may be captured and stored, resulting in a single event reversal event. Therefore, the single event upset event will change the logic state stored in SRAM and other memories, which may cause the overall circuit function error. Therefore, the design method of the memory circuit against radiation has attracted the attention of those skilled in the art.

The design methods of radiation-hardened SRAM memory circuits in the prior art mainly include multi-mode redundancy, error correction codes, radiation-resistant hardening technology, etc. Among them, the multi-mode redundancy method is represented by triple-mode redundancy technology, using redundant circuit modules And the majority voting circuit shields the output of the wrong circuit module; the error correction code method is represented by the Hamming code, by calculating the check value of the code, locating the position of the error bit, and then correcting the error by inverting the error bit, but research shows that using Designing SRAM storage arrays with triple-mode redundancy and error-correcting codes will bring a large area overhead; the anti-radiation hardening technology is represented by SRAM-tct, which adds additional transistors and capacitors on the basis of the basic SRAM storage cell structure to enhance sensitive nodes Radiation resistance, but when radiation occurs when writing SRAM cell data, traditional SRAM-tct and other radiation-resistant hardening technologies cannot protect other non-writing SRAM cells in the same row as the SRAM cell that is writing data in the SRAM array SRAM cells are not affected by radiation, because traditional SRAM arrays allow SRAM cells in the same row to share access and read and write control signals in order to reduce area overhead, and when a radiation-resistant SRAM cell is allowed to access and write data, its radiation-resistant circuit The structure will temporarily lose its function so that data can be written quickly, so when writing data to a SRAM unit, the radiation resistance of other SRAM units that are not writing data in the same row of shared access and read/write control signals will temporarily disappear. Therefore, it is easily affected by radiation.

Based on the status of the prior art, the inventors of the present application intend to provide a radiation-resistant fault-tolerant SRAM storage array and a preparation method thereof.

References relevant to the present invention are:

[1] Baumann R.Soft Errors in Advanced Computer Systems[J],IEEE Transactions on Device and Materials Reliability,2005,22(3),pp.258-266

[2] Oliveira R., Jagirdar A., Chakraborty T.J.: A TMR Scheme for SEU Mitigation in ScanFlip-Flops [C], in International Symposium on Quality Electronic Design, 2007, pp.905–910

[3]Tausch H.J.Simplified Birthday Statistics and Hamming EDAC[J],IEEE Transactions on Nuclear Science,2009,56(2),pp.474–478

[4] Y.Shiyanovskii, F.Wolff, C.Papachristou, "SRAM Cell Design Protected from SEUUpsets", 14th International On-Line Testing Symposium, 7-9Jul.2008, pp.169–170.

Contents of the invention

The purpose of the present invention is to overcome the defective of prior art, for SRAM storage array, propose a kind of can resist radiation fault-tolerant SRAM storage array and preparation thereof when writing data, reading data and suspending use (neither read nor write) method.

Specifically, the present invention adds a SRAM unit for data backup at the end of each row of SRAM units used for data reading and writing in the SRAM storage array; each SRAM unit for data reading and writing and data backup can resist radiation; When radiation occurs in writing SRAM unit data, the SRAM unit used for data backup can protect other SRAM units not writing data in the same row as the SRAM unit that is writing data from being affected by radiation. The anti-radiation design of the SRAM cells can of course also protect all SRAM cells from radiation when the SRAM storage array reads data and is suspended (neither read nor write).

More specifically, a radiation-resistant, fault-tolerant SRAM storage array of the present invention is characterized in that it is a fault-tolerant SRAM array circuit that can resist radiation when writing data, reading data, and suspending use, and is designed by the following methods and steps:

Step 1: According to the circuit structures shown in Fig. 1, Fig. 2 and Fig. 3, an integrated circuit design method is used to design a radiation-resistant SRAM storage array;

Step 2: Operate the access control signal and read-write control signal of the SRAM unit used for data storage and data backup, so that the SRAM storage array is in the state of writing data, reading data and suspending use (neither reading nor writing) All are resistant to radiation.

In step 1) of the present invention, according to the circuit structure shown in Figure 1, a radiation-resistant SRAM storage array is designed; the SRAM array includes n rows and m columns of SRAM cells (C _n1 -C _nm , ..., C ₁₁ -C) for data storage _1m ) and m SRAM cells (S ₁ -S _m ) for data backup arranged at the end of each column; the SRAM cell circuit structure for data storage is shown in Figure 2; the SRAM cell circuit structure for data backup As shown in Figure 3;

Step 2 of the present invention) comprises:

If the SRAM storage array is in the data writing mode, proceed to steps 2.1 and 2.2 in sequence;

Step 2.1: It is the stage of preparing to write data; set the value of address A1A2...Ak in Figure 1, select the SRAM unit to write data, set the control signal EN to 1, WR and Set to 0 and 1 respectively; the access control signal CS of the SRAM unit used for data backup in the same column as the SRAM unit to be written is set to 0, the read and write control signal FS and Set to 0 and 1 respectively, but the access control signal CS of other SRAM cells used for data backup that is not in the same column as the SRAM cell to be written is set to 1, and the read and write control signals FS and Set to 1 and 0 respectively, then go to step 2.2;

Step 2.2: It is the stage of writing data; the control signal EN is set to 1, WR and Set to 1 and 0 respectively, and the access control signal CS of the SRAM unit used for data backup in the same column as the SRAM unit to write data continues to be 0, and the read and write control signal FS and Continue to keep 0 and 1 respectively, but the access control signal CS of other SRAM cells used for data backup that are not in the same column as the SRAM cell that writes data is set to 1, and the read and write control signals FS and Set to 0 and 1 respectively;

If the SRAM storage array is in the data read mode, proceed to step 2.3;

Step 2.3: Set the value of address A1A2...Ak in Figure 1, select the SRAM unit to read data; set the control signal EN to 1, WR and Set to 0 and 1 respectively, CS ₁ -CS _m is set to 0, FS ₁ -FS _m is set to 0, set 1;

If the SRAM storage array is in the suspend mode, proceed to step 2.4;

Step 2.4: Set control signal EN to 0, WR and Set to 0 and 1 respectively, CS ₁ -CS _m is set to 0, FS ₁ -FS _m is set to 0, set 1;

In the present invention, the multi-bit SRAM unit is simultaneously written and read, wherein at first a plurality of SRAM storage array structures as shown in Figure 1 are adopted, and the control signals EN of these SRAM storage array structures are connected together, The control signal WR is connected together, the control signal connected together, the control signals CS ₁ are connected together, the control signals CS ₂ are connected together, ..., the control signals CS _m are connected together, the control signals FS ₁ are connected together, the control signals FS ₂ are connected together in Together, ..., the control signal FS _m are interconnected together, the control signal interconnected together, the control signal interconnected together, ..., control signals Connect together; then according to the steps 2.1-2.3, realize writing and reading operations to the multi-bit SRAM unit simultaneously, and suspend all SRAM storage arrays according to the step 2.4 (neither read nor write).

The present invention has the following advantages:

(1) The present invention proposes a fault-tolerant SRAM array circuit design method that can resist radiation when writing data, reading data, and suspending use (neither reading nor writing), especially when writing data, it can protect and The SRAM cells in which data is written and other SRAM cells in which data is not written in the same row are not affected by radiation.

(2) The area overhead of the present invention is mainly an SRAM unit for backing up data added at the end of each column. The proportion of the additional area overhead brought by the SRAM unit for backing up data is approximately inversely related to the number of rows in the SRAM array, so the proportion of the area overhead will continue to decrease as the number of rows increases. For example, in a common 64K byte SRAM array, the ratio of the extra area overhead brought by the SRAM unit for backing up data can be approximately estimated to be 1/64000, so the ratio of the extra area overhead of the present invention is in large capacity SRAM arrays are still fairly small.

For ease of understanding, the present invention will be described in detail below through specific drawings and embodiments. It should be pointed out that the specific examples and accompanying drawings are only for illustration. Obviously, those skilled in the art can make various amendments and changes within the scope of the present invention according to the description herein. These amendments and Modifications are also included within the scope of the present invention. In addition, the present invention refers to published documents, which are for the purpose of more clearly describing the present invention, the entire contents of which are incorporated herein by reference as if they had been recited herein in their entirety.

Description of drawings:

FIG. 1 is a schematic diagram of a radiation-resistant fault-tolerant SRAM memory array of the present invention.

FIG. 2 is a schematic diagram of the circuit structure of the SRAM cell used for data storage in FIG. 1 .

FIG. 3 is a schematic diagram of the circuit structure of the SRAM unit used for data backup in FIG. 1 .

detailed description

Embodiment 1 uses the following methods and steps to set up a fault-tolerant SRAM array circuit that can resist radiation when writing data, reading data, and suspending use.

Step 1: According to the circuit structures shown in Fig. 1, Fig. 2 and Fig. 3, a radiation-hardened SRAM memory array is designed using a traditional integrated circuit design method.

According to the circuit structure shown in Fig. 1, design the anti-radiation SRAM memory array. Fig. 1 shows an SRAM cell (C _n1 -C _nm ,..., C ₁₁ -C _1m ) comprising n rows and m columns of the present invention for data storage and m SRAMs arranged at the end of each column for data backup Rad-hard SRAM memory array of cells (S ₁ -Sm).

The SRAM unit circuit structure used for data storage in Figure 1 is shown in Figure 2. In Figure 2, when the read-write control signal WR is 1, When it is 0, the NMOS transistors M2 and M4 are turned on, and the PMOS transistors M1 and M3 are turned on, so the inverters INV1 and INV2 whose drive voltage is Vdd constitute a traditional storage unit, and nodes X and Y are storage nodes. For example, when the X value is 1, the Y value becomes 0 after being inverted by the inverter INV2; after the Y value is inverted by the inverter INV1, the X value is 1 again, which further strengthens the previous value 1 of X, thus Make the storage nodes X and Y store values 1 and 0 stably, respectively. When the access control signal EN is 1, the NMOS transistors M5 and M6 are turned on, so the data line and BL are respectively connected to storage nodes X and Y. So when EN is 1 and WR is 1, is 0, the data line A value opposite to that on the BL can be written to the memory cell (e.g. The value of BL is 1, and the value of BL is 0, so that the storage nodes X and Y of the storage unit can store 1 and 0 stably, respectively). When data is written into the storage unit, even if the value of the storage node X or Y changes due to the transient radiation pulse, after the radiation pulse disappears, the data being written will drive the storage node X or Y affected by the radiation to recover correctly Value, so the memory cell has anti-radiation characteristics when writing data. But note that when WR is 1, When it is 0, if no data is written, the change of the value of one storage node due to the transient radiation pulse will immediately cause the change of another storage node through the inverter and be latched. For example, suppose the value of storage node X is 1, and the corresponding value of storage node Y is 0. When WR is 1, When it is 0, if the value stored in Y changes from 0 to 1 due to the influence of the transient radiation pulse, because the NMOS transistors M2 and M4 are turned on, and the PMOS transistors M1 and M3 are turned on, the change in the value stored in Y will pass through the inverter immediately INV1 causes the value stored in X to change from 1 to 0, and after the X value is inverted by the inverter INV2, the Y value is 1 again, which further strengthens the wrong value of Y to 1, so that the storage nodes X and Y can store stably respectively. Error values 0 and 1. So, when WR is 1, When it is 0, if the data is not being written, the memory cell has no anti-radiation characteristics, but if data is written, the data being written will drive the storage nodes affected by radiation to restore the correct value, thus having anti-radiation characteristics. When WR is 0, When it is 1, the NMOS transistors M2 and M4 are turned off, and the PMOS transistors M1 and M3 are turned off. The change of the value of one storage node due to the transient radiation pulse will not cause the change of the other storage node through the inverter in a short time. After the radiation pulse disappears, the storage node holding the correct value will drive the storage node holding the wrong value back to the correct value. For example, suppose the value of storage node X is 1, and the corresponding value of storage node Y is 0. If the value stored by Y changes from 0 to 1 due to the influence of the transient radiation pulse, because the NMOS transistors M2 and M4 are turned off, and the PMOS transistors M1 and M3 are turned off, the change in the value stored by Y will not pass through the inverter INV1 in a short time The value stored in X changes from 1 to 0, so X still maintains the correct value of 1. After the radiation pulse on the storage node Y disappears, the storage node X that maintains the correct value of 1 drives the storage node Y to restore the correct value through the inverter INV2 0. So when WR is 0, When it is 1, the storage unit has anti-radiation characteristics. When the access control signal EN is 1, the NMOS transistors M5 and M6 are turned on, and the data line and BL are respectively connected to storage nodes X and Y. So when EN is 1 and WR is 0, When 1, the memory cell is resistant to radiation and the values on memory nodes X and Y can be read separately to the data lines and BL on. When the access control signal EN is 0, the NMOS transistors M5 and M6 are turned off, and the data line and BL are not connected to storage nodes X and Y. So when EN is 0 and WR is 0, When it is 1, the memory cell is resistant to radiation but is in a suspended state (neither read nor write). The above functions are summarized as follows: When the access control signal EN is 1, the read and write control signal WR and 1 and 0 respectively, the data line The value opposite to that on BL is written into the storage unit, and the storage unit is resistant to radiation; when the access control signal EN is 1, the read-write control signal WR and When they are 0 and 1 respectively, the values with opposite phases stored in the storage unit are read out to the data lines respectively and BL, and the storage unit is resistant to radiation; when the access control signal EN is 0, the read and write control signal WR and When they are 0 and 1 respectively, the storage unit is in a suspended state (neither read nor write), and the storage unit can resist radiation; when the read-write control signal WR and Don't be 1 and 0, if the data line If no data is applied to the memory cell and BL, then the memory cell has no anti-radiation characteristics. It should be noted that the circuit structure of the SRAM unit used for data storage in FIG. 1 may also adopt other radiation-hardened SRAM unit structures, as long as its function is the same as that of the radiation-hardened SRAM unit shown in FIG. 2 .

The circuit structure of the SRAM cell used for data backup in Fig. 1 is shown in Fig. 3 . The SRAM unit circuit structure for data backup shown in Figure 3 is exactly the same as the SRAM unit circuit structure for data storage shown in Figure 2, except that the control signals in Figure 2 are EN, WR and The corresponding control signals in Figure 3 are CS, FS and According to the functional description of Figure 2 in the previous paragraph, the structure and function of the SRAM unit circuit used for data backup shown in Figure 3 can be summarized as follows: when the access control signal CS is 1, the read and write control signal FS and 1 and 0 respectively, the data line The value opposite to that on BL is written into the storage unit, and the storage unit is resistant to radiation; when the access node CS is 1, the read-write control signal FS and When they are 0 and 1 respectively, the values with opposite phases stored in the storage unit are read out to the data lines respectively and BL, and the storage unit is resistant to radiation; when the access node CS is 0, the read and write control signal FS and When they are 0 and 1 respectively, the storage unit is in a suspended state (neither read nor write), and the storage unit can resist radiation; when the read-write control signal FS and are 1 and 0 respectively, if the data line If no data is applied to the memory cell and BL, then the memory cell has no anti-radiation characteristics. It should be noted that the circuit structure of the SRAM unit used for data backup in FIG. 1 may also adopt other radiation-hardened SRAM unit structures, as long as its function is the same as that of the radiation-hardened SRAM unit shown in FIG. 3 .

Now return to FIG. 1 and continue to introduce the radiation-hardened SRAM memory array structure of the present invention. A1A2...Ak in Fig. 1 is the SRAM unit address to be accessed, and the decoder decodes the address. The decoder can be realized by a traditional decoder circuit. The output of the decoder controls the row multiplexer and the column multiplexer in Figure 1 (the row multiplexer and the column multiplexer can be implemented using traditional multiplexer circuits) to determine which The SRAM unit of the row and column is accessed, and then the access control signal EN and the read and write signal WR and Apply the corresponding value to read and write to the selected SRAM unit. For example, assuming that Figure 1 is a 16-row and 16-column SRAM storage array, the first 4 bits A1A2A3A4 of the 8-bit addresses A1A2...A8 can be used to represent the row address, and the last 4 bits A5A6A7A8 to represent the column address. If the address A1A2...A8 is 00000001, two outputs 0000 and 0001 can be generated through the decoder, the first output 0000 selects the first row of SRAM cells C ₁₁ -C ₁ m through the row multiplexer, and the second output 0001 further selects the second column of SRAM cells C ₁₂ among the SRAM cells C ₁₁ -C _1m through the column multiplexer. In Figure 1, it is assumed that the control signal EN is 1, and the read and write control signal WR is 1. is 0, since the row multiplexer selects row 1, EN ₁ is connected to EN, so EN ₁ 1, WR ₁ vs. WR So WR ₁ outputs 1, WR ₁ with connected, so output 0, again due to the column The selector selects column 2, so BL ₂ is connected to BL, and connected. Therefore, according to the introduction to the function of the SRAM unit storing data shown in Figure 2, the data line A value opposite to that of BL can be written into the selected SRAM cell C ₁₂ in row 1 and column 2 . It is worth noting that if EN, WR and Operate as a traditional SRAM array, and set it to 1, 1 and 0 respectively at the same time, then other SRAM cells in the first row that have no data written in the same row as the SRAM cell C ₁₂ that is writing data have no anti-radiation characteristics temporarily. If these unwritten SRAM cells are irradiated, the data they store is likely to be erroneous. The present invention adds SRAM units (S ₁ -S _m ) for data backup at the end of each column of the SRAM storage array, and controls access control signals CS ₁ -CS _m , read and write control signals FS of the SRAM units for data backup ₁ -FS _m with And the access control signal EN of the SRAM unit used for data storage, the read and write control signal WR and Special operations are performed to protect other SRAM cells without data written in the same row as the SRAM cells being written into from radiation, and these special operations will be described in detail in step 2.

Step 2: Operate the access control signal and read-write control signal of the SRAM unit used for data storage and data backup, so that the SRAM storage array is in the state of writing data, reading data and suspending use (neither reading nor writing) can resist radiation,

The SRAM storage array has three modes: write data, read data, and suspend use (neither read nor write);

If the SRAM storage array is in the data writing mode, proceed to steps 2.1 and 2.2 in sequence;

Step 2.1 is the stage of preparing to write data. In step 2.1, set the value of address A1A2...Ak in Figure 1, output the row address and column address through the decoder, and select the SRAM unit to write data through the row multiplexer and column multiplexer. The access control signal EN of the SRAM cell used for data storage is set to 1, but the read and write control signals WR and Set to 0 and 1 respectively, so that the SRAM unit used for data storage still has radiation resistance (note that data has not been written to the SRAM unit used for data storage at this time). At the same time, the access control signal CS of the SRAM unit used for data backup in the same column as the SRAM unit to be written is set to 0, and the read and write control signal FS and Set to 0 and 1 respectively, but the access control signal CS of other SRAM cells used for data backup that is not in the same column as the SRAM cell to be written is set to 1, and the read and write control signals FS and Set to 1 and 0 respectively, so that in addition to the SRAM unit to be written in data, other SRAM units that do not write data in the same row as the SRAM unit to be written in (note that they are in a radiation-resistant state at this time) store The correct data is written into the corresponding SRAM unit for data backup for backup. For example, assuming that the SRAM cell C _n1 in Figure 1 is selected to write data, then EN is set to 1, WR and Set to 0 and 1 respectively, CS ₁ is set to 0, FS ₁ and are set to 0 and 1 respectively, while CS ₂ -CS _m is set to 1, FS ₂ -FS _m is set to 1, set to 0. In this way, except for the SRAM cell C _n1 to write data, the SRAM cells C _n2 -C _nm in the anti-radiation state write their correct data stored in the SRAM cells S ₂ -S _m for backup; then enter step 2.2;

Step 2.2 is the phase of writing data. In step 2.2, the access control signal EN of the SRAM unit used for data storage is set to 1, and the read and write control signals WR and Set to 1 and 0 respectively, and write data to the SRAM cell selected in step 2.1. At this time, the SRAM cell that is writing data is in a radiation-resistant state, but other SRAM cells that are not written in data in the same row as the SRAM cell that is writing data are not in a radiation-resistant state, and are easily affected by radiation and store erroneous data. Therefore, the access control signal CS of the SRAM unit used for data backup in the same column as the SRAM unit to be written in data continues to be 0, and the read and write control signal FS and Continue to keep 0 and 1 respectively, but the access control signal CS of other SRAM cells used for data backup that are not in the same column as the SRAM cell that writes data is set to 1, and the read and write control signals FS and Set to 0 and 1 respectively; like this, other SRAM cells used for data backup that are not in the same column as the SRAM cells that write data are in a radiation-resistant state, and their backup stored data in step 2.1 can drive those affected by radiation, and The SRAM unit with data written in other SRAM units without data written in the same row recovers correct data after the radiation pulse disappears; refer to the example in step 2.1, assuming that the SRAM unit C _nm without written data is affected by radiation, then The SRAM unit S _m backing up its correct data in step 2.1 can drive the SRAM unit C _nm to restore the correct data after the radiation pulse disappears;

If the SRAM storage array is in the data read mode, proceed to step 2.3;

In step 2.3, set the value of address A1A2...Ak in Figure 1, output the row address and column address through the decoder, and select the SRAM unit to read data through the row multiplexer and column multiplexer. The access control signal EN of the SRAM unit used for data storage is set to 1, and the read and write control signals WR and Set to 0 and 1 respectively, so that the SRAM cells used for data storage have radiation resistance characteristics, and the data stored in the selected SRAM cells can be read out to the data lines BL and superior. At the same time, the access control signals CS ₁ -CS _m of the SRAM unit used for data backup are set to 0, FS ₁ -FS _m are set to 0, Set 1; in this way, the SRAM cell used for data backup remains in a radiation-resistant state, and is not connected to the data lines BL and connected to avoid interference with reading data from SRAM cells used for data storage;

If the SRAM storage array is in the suspend mode, proceed to step 2.4;

In step 2.4, the access control signal EN of the SRAM cell used for data storage in Figure 1 is set to 0, and the read and write control signals WR and Set to 0 and 1 respectively; the access control signal CS ₁ -CS _m of the SRAM unit used for data backup is set to 0, FS ₁ -FS _m is set to 0, set1. In this way, all SRAM cells used for data storage and data backup remain in a radiation-hardened state and are not connected to the data lines BL and The connection is in a suspended state (neither read nor write);

The present invention has described the writing and reading operation to 1-bit SRAM unit in above-mentioned steps 2.1-2.3, but the present invention is easy to extend to multi-bit SRAM unit and writes and reads simultaneously, and a kind of method is Multiple SRAM memory array structures as shown in Figure 1 are adopted, the control signals EN of these SRAM memory array structures are connected together, the control signals WR are connected together, and the control signals connected together, the control signals CS ₁ are connected together, the control signals CS ₂ are connected together, ..., the control signals CS _m are connected together, the control signals FS ₁ are connected together, the control signals FS ₂ are connected together in Together, ..., the control signal FS _m are interconnected together, the control signal interconnected together, the control signal interconnected together, ..., control signals Connect each other together, and then follow the above steps 2.1-2.3 to realize simultaneous writing and reading operations on multi-bit SRAM cells, and follow step 2.4 to suspend all SRAM storage arrays (neither read nor write) . For example, to write and read one byte (8 bits) of SRAM data, 8 SRAM storage array structures as shown in Figure 1 can be used, and the corresponding control signals are connected together, according to the above steps 2.1-2.3 operation can be realized.

Embodiment 2 test experiment result

In the experiment, a standard SRAM unit without radiation resistance is used to construct a 64-row and 64-column SRAM array for storing data, and the present invention is used to construct a 64-row and 64-column radiation-resistant SRAM array for storing data, and a SRAM-tct unit is used to construct a 64-row The radiation-hardened SRAM storage array with 64 columns storing data randomly irradiates the three SRAM arrays 1000 times respectively, and the test results are shown in Table 1. The area and power consumption in table 1 have been through normalization process, and its numerical value is the multiple with respect to the actual area of SRAM array of the present invention and power consumption; As can be seen from table 1, the number of times of error occurrence of the present invention is minimum (error occurs The number of times is 0), so the anti-radiation ability is the strongest; as can be seen from Table 1, compared with the SRAM-tct scheme which also has anti-radiation ability, the area and power consumption of the present invention are all smaller.

Table 1 Comparison of area, power consumption and radiation resistance

Program Error Occurrences area power consumption Non-Radiation Hardened SRAM Arrays 654 0.59 0.51 Anti-radiation SRAM array of the present invention 0 1 1 Radiation Hardened SRAM Array Using SRAM-tct Cells 18 1.29 1.17

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Claims (4)

1. a kind of anti-radiation fault-tolerant SRAM memory array, it is characterized in that, for the fault-tolerant SRAM array circuit that can resist radiation when writing data, reading data and suspending not in use, design system by following method and step: Step 1: According to the circuit structures shown in Fig. 1, Fig. 2 and Fig. 3, an integrated circuit design method is used to design a radiation-resistant SRAM storage array; Step 2: Operate the access control signal and read-write control signal of the SRAM unit used for data storage and data backup, so that the SRAM storage array can resist radiation when writing data, reading data and suspending the state. 2. the anti-radiation and fault-tolerant SRAM storage array according to claim 1, wherein in said step 1), the anti-radiation SRAM storage array comprises n rows and m columns of SRAM cells (C _n1- for data storage) C _nm ,..., C ₁₁ -C _1m ) and m SRAM cells (S ₁ -S _m ) for data backup arranged at the end of each column; the circuit structure of the SRAM cell for data storage is shown in Figure 2; The SRAM unit circuit structure used for data backup is shown in Figure 3. 3. by the anti-radiation fault-tolerant SRAM memory array of claim 1, it is characterized in that, wherein said step 2) comprises: If the SRAM storage array is in the data writing mode, proceed to steps 2.1 and 2.2 in sequence; Step 2.1: It is the stage of preparing to write data; set the value of address A1A2...Ak in Figure 1, select the SRAM unit to write data; set the control signal EN to 1, WR and Set to 0 and 1 respectively; the access control signal CS of the SRAM unit used for data backup in the same column as the SRAM unit to be written is set to 0, the read and write control signal FS and Set to 0 and 1 respectively, but the access control signal CS of other SRAM cells used for data backup that is not in the same column as the SRAM cell to be written is set to 1, and the read and write control signals FS and Set to 1 and 0 respectively; then go to step 2.2; Step 2.2: It is the stage of writing data; the control signal EN is set to 1, WR and Set to 1 and 0 respectively, and the access control signal CS of the SRAM unit used for data backup in the same column as the SRAM unit to write data continues to be 0, and the read and write control signal FS and Continue to keep 0 and 1 respectively, but the access control signal CS of other SRAM cells used for data backup that are not in the same column as the SRAM cell that writes data is set to 1, and the read and write control signals FS and Set to 0 and 1 respectively; If the SRAM storage array is in the data read mode, proceed to step 2.3; Step 2.3: Set the value of address A1A2...Ak in Figure 1, select the SRAM unit to read data; set the control signal EN to 1, WR and Set to 0 and 1 respectively, CS ₁ -CS _m is set to 0, FS ₁ -FS _m is set to 0, set 1; If the SRAM storage array is in the suspend mode, proceed to step 2.4; Step 2.4: Set control signal EN to 0, WR and Set to 0 and 1 respectively, CS ₁ -CS _m is set to 0, FS ₁ -FS _m is set to 0, set1. 4. The anti-radiation and fault-tolerant SRAM storage array according to claim 1, wherein said method and steps are used to simultaneously write and read the multi-bit SRAM unit, which comprises: first adopting a plurality of In the SRAM memory array structure shown in Figure 1, the control signals EN are connected to each other, the control signals WR are connected to each other, and the control signals connected together, the control signals CS ₁ are connected together, the control signals CS ₂ are connected together, ..., the control signals CS _m are connected together, the control signals FS ₁ are connected together, the control signals FS ₂ are connected together in Together, ..., the control signal FS _m are interconnected together, the control signal interconnected together, the control signal interconnected together, ..., control signals Connect together; Then according to the steps 2.1-2.3 described in claim 3, realize writing and reading operation simultaneously to the multi-bit SRAM unit, and suspend all SRAM storage arrays according to the step 2.4.