CN105988255B - Display panel - Google Patents
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- CN105988255B CN105988255B CN201510074172.8A CN201510074172A CN105988255B CN 105988255 B CN105988255 B CN 105988255B CN 201510074172 A CN201510074172 A CN 201510074172A CN 105988255 B CN105988255 B CN 105988255B
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Abstract
The present invention relates to a kind of display panels comprising first substrate, first substrate include: substrate；Semiconductor layer is located at substrate；First insulating layer is located on semiconductor layer；First scan line and the second scan line are located on the first insulating layer, and extend in a first direction respectively, and first and second partial scan line is Chong Die with semiconductor layer；Second insulating layer is located on the first scan line, second scan line and the first insulating layer；Data line is located in the second insulating layer, and extends in a second direction, which is electrically connected by the first contact hole and the semiconductor layer, wherein second direction difference and first direction；And first metal gasket and the second metal gasket, it is located in second insulating layer, first and second metal gasket passes through two second contact holes respectively and semiconductor layer is electrically connected；Wherein, the first contact hole and two second contact holes are located between first and second scan line.
Description
Technical field
The present invention relates to a kind of display panel, it is espespecially a kind of by adjusting array substrate with line position and its structure with
Improve the display panel of aperture opening ratio.
Background technique
In general, liquid crystal display panel is by the array substrate comprising active members such as thin film transistor (TFT)s, comprising colour
The colored filter substrate of the elements such as optical filter and sandwiched liquid crystal therein are formed, wherein in data line and scan line etc.
Distribution area and transistor area, the display panel generally include a black matrix" to prevent colour mixture, raising contrast degree and prevent
Transistor causes alignment film orientation uneven.As the demand of high-resolution liquid crystal display increases therewith, black matrix" is reduced
To promote the important topic that the aperture opening ratio of liquid crystal display becomes technical field development.
However, the design based on known transistor and wiring subtracts under the premise of maintaining to avoid colour mixture and keep contrast
The effect of lacking aperture opening ratio of the black matrix" to improve display is to be limited.Therefore developing matching by adjusting array substrate
Line position and its structure have the function of high aperture and have both the liquid crystal display of above-mentioned black matrix" to provide one, to have
Needed for it.
Summary of the invention
The main object of the present invention is to provide a kind of display panel, to match line position by adjusting array substrate
And its structure is to improve the aperture opening ratio of display panel.
To reach above-mentioned purpose, the present invention is to provide a kind of display panel comprising a first substrate, a display layer and one
The second substrate, wherein the display layer is located between the first substrate and the second substrate, which includes: a substrate；
Semi-conductor layer is located on the substrate；One first insulating layer is located on the semiconductor layer；One first scan line and one second
Scan line is located on first insulating layer, and extends respectively along a first direction, and first and second scan line of a part
It is Chong Die with the semiconductor layer；One second insulating layer is located on first scan line, second scan line and first insulating layer；
One data line is located in the second insulating layer, and extends along a second direction, which passes through one first contact hole and be somebody's turn to do half
Conductor layer is electrically connected, wherein the second direction difference and the first direction；And one first metal gasket and one second metal
Pad is located in the second insulating layer, which passes through two second contact holes with second metal gasket respectively partly leads with this
Body layer is electrically connected；Wherein, first contact hole and two second contact hole are located at first scan line and second scan line
Between.
In a state sample implementation, which can further include: a third insulating layer, be located at first metal gasket, this
On two metal gaskets and the second insulating layer；One first pixel electrode layer is located on the third insulating layer, first pixel electrode layer
It is electrically connected by a third contact hole and first metal gasket；And one second pixel electrode layer, it is located at the third insulating layer
On, which is electrically connected by another third contact hole and second metal gasket.
In a state sample implementation, which can be adjacent to the same of the data line with second pixel electrode layer
Side.
In a state sample implementation, first pixel electrode layer and second pixel electrode layer can be adjacent to the data line not
It is ipsilateral, and first scan line includes one first inside edge and one first outer ledge, which includes one
Second inside edge and one second outer ledge, wherein adjacent second inside edge in first inside edge.
In a state sample implementation, first pixel electrode layer can be overlapped in first inside edge of first scan line with
First outer ledge, and second pixel electrode layer can be overlapped in second scan line second inside edge and this second
Outer ledge.
In a state sample implementation, first pixel electrode layer and second pixel electrode layer can be located at first scan line
Between first outer ledge and the second outer ledge of second scan line.
In a state sample implementation, which can further include multiple light shield layers, be located at the substrate and the semiconductor layer
Between, the position of the light shield layer correspond respectively to first scan line region Chong Die with the semiconductor layer and this second
The scan line region Chong Die with the semiconductor layer.
In a state sample implementation, which can further include a buffer layer, be located at the substrate and the semiconductor layer it
Between, and the light shield layer is located between the substrate and the buffer layer.
In a state sample implementation, which can further include one first black-matrix layer and one second black-matrix layer,
Between the first substrate and the second substrate, which at least covers first scan line or this second is swept
Line is retouched, and second black-matrix layer at least covers the data line.
In a state sample implementation, the width of first black-matrix layer is between 5 μm to 50 μm.
In a state sample implementation, which can be a colored filter substrate, which includes at least four
The pixel group of different colours, wherein each pixel group includes four adjacent to each other and the first pixel units of same color, second
Pixel unit, third pixel unit and the 4th pixel unit, wherein first black-matrix layer or second black-matrix layer
Between the pixel group of different colours.
In a state sample implementation, which can be a colored filter substrate, which includes at least three
The pixel group of row different colours, each pixel group include it is multiple along the second direction arrangement and same color pixel unit,
In, in the pixel group, first black-matrix layer is between two adjacent pixel units and another two adjacent pixel unit.
In a state sample implementation, which can further include one first black-matrix layer and one second black-matrix layer,
Between the first substrate and the second substrate, which at least covers first scan line or this second is swept
Line is retouched, and second black-matrix layer at least covers the data line of a part.
In a state sample implementation, which can be a colored filter substrate, which includes at least three
The pixel group of a different colours, each pixel group include two adjacent and same color pixel units in the first direction,
Wherein, first black-matrix layer or second black-matrix layer are located between the pixel group of different colours.
Detailed description of the invention
To further illustrate technology contents of the invention, with reference to embodiments and attached drawing detailed description is as follows, in which:
Fig. 1 is the schematic diagram of the display panel of the embodiment of the present invention 1.
Fig. 2 is the line configuring schematic diagram of the first substrate of the embodiment of the present invention 1.
Fig. 3 is the line construction schematic diagram of the first substrate of the embodiment of the present invention 1.
Fig. 4 is the schematic top plan view of the first substrate of the embodiment of the present invention 1.
Fig. 5 is the schematic cross-sectional view for the first substrate being unfolded along the A-A ' cutting line of Fig. 4.
Fig. 6 A is the schematic diagram of the second substrate of the embodiment of the present invention 1.
Fig. 6 B is the schematic diagram of the second substrate of the embodiment of the present invention 2.
Fig. 7 is the line configuring schematic diagram of the first substrate of the embodiment of the present invention 3.
Fig. 8 is the line construction schematic diagram of the first substrate of the embodiment of the present invention 3.
Fig. 9 is the schematic top plan view of the first substrate of the embodiment of the present invention 3.
Figure 10 is the schematic diagram of the second substrate of the embodiment of the present invention 3.
Figure 11 is the line construction schematic diagram of the first substrate of the embodiment of the present invention 4.
Figure 12 is the schematic top plan view of the first substrate of the embodiment of the present invention 4.
Figure 13 A is known pixel polarity schematic diagram.
Figure 13 B is the pixel polarity schematic diagram of the first substrate of the embodiment of the present invention 4.
Figure 14 is the first substrate of the embodiment of the present invention 4 and the schematic diagram that the second substrate is stacked.
Specific embodiment
With high-resolution liquid crystal display demand with increase, reduce black matrix" to promote liquid crystal display
Aperture opening ratio becomes an important topic of technical field development.Therefore for improve the above problem, the present invention be by adjusting
Array substrate matches line position and its structure to achieve the purpose that improve display panel aperture opening ratio.
In the present invention, as long as can reach the purpose of aforementioned present invention, the present invention is also not particularly limited the array substrate
Material used in each element, any material known in the art all can be used.For example, in an implementation of the invention
In aspect, which can be a transparent substrate, such as transparent plastic substrate or glass substrate；The buffer layer can by silicon nitride,
Silica or combinations thereof is formed；The semiconductor layer can be made of uncrystalline silicon, low temperature polycrystalline silicon or metal oxide；It should
Second insulating layer (or can be described as passivation layer) can be by silicon nitride, silica or combinations thereof；First insulating layer material can be by aoxidizing
Silicon, silicon nitride, silicon oxynitride or hafnium oxy-nitride are formed；First scan line, second scan line (or can be described as grid
Layer), first metal gasket and second metal gasket (or can be described as source layer) can be by conduction materials such as molybdenums, aluminium, copper, titanium or combinations thereof
Material is formed；The third insulating layer can by perfluoroalkoxy resin (perfluoroalkoxy polymer resin,
PFA), the materials such as fluorubber (fluoroe lastomers) are formed；And first pixel electrode and the second pixel electrode can be by
Transparent conductive oxide is formed, such as indium tin oxide, indium-zinc oxide, aluminium zinc oxide etc..
It is that embodiments of the present invention are illustrated by specific embodiment below, the personage for being familiar with this technology can be by this specification
Other advantages and efficacy of the present invention can be easily understood for revealed content.In addition, the present invention also can be different specific by other
Embodiment is implemented or is applied, and carries out various modifications and change without departing from the spirit of the present invention.
Embodiment 1
Referring to FIG. 1, being the schematic diagram of the display panel 100 of the present embodiment 1, wherein the display panel 100 includes one the
One substrate 10, a display layer 5 and a second substrate 20, wherein the display layer 5 is located at the first substrate 10 and the second substrate 20
Between, and the first substrate 10 and the second substrate 20 are respectively array basal plate and a colored filter substrate, the display layer 5
It can be a liquid crystal layer.
Referring to FIG. 2, the line configuring schematic diagram of the first substrate 10 for the present embodiment 1.As shown in Fig. 2, the present embodiment 1
It is by adjusting the line configuring mode on first substrate 10 and by lighttight element (such as the first scan line of adjacent pixel
105, the second scan line 105 ' and thin-film transistor element T) concentrated setting.Further, referring to FIG. 3, being for the present embodiment
The line construction schematic diagram of 1 first substrate 10, wherein Fig. 3 is only presented semiconductor layer 103, the first scan line 105, second sweeps
Retouch line 105 ', data line 107 (or can be described as drain electrode layer) and the first contact hole 108 being electrically connected, the second contact hole 111, the
The relative positional relationship of the elements such as one pixel electrode layer 113 and the second pixel electrode layer 115, this hair is more clearly presented
Bright technical characteristic.In Fig. 3, data line 107 is to be electrically connected by one first contact hole 108 with the semiconductor layer 103.Half
Conductor layer 103 is by two second contact holes 111 and two third contact holes 114,114 ' (being shown in Fig. 5) and first pixel electrode
Layer 113 is electrically connected with second pixel electrode layer 115.
First contact hole 108 and two second contact hole 111 are located at one first scan line 105 and one second scan line
Between 105 '.First pixel electrode layer 113 is located at the not ipsilateral of the data line 107 with second pixel electrode layer 115, and should
First scan line 105 includes one first inside edge 1051 and one first outer ledge 1052, second scan line 105 ' packet
Contain one second inside edge 1051 ' and one second outer ledge 1052 ', wherein first inside edge 1051 it is adjacent this
Two inside edges 1051 ', first pixel electrode layer 113 be overlapped in the first inside edge 1051 of first scan line 105 with
First outer ledge 1052, and second pixel electrode layer 115 is overlapped in the second inside edge of second scan line 105 '
1051 ' with second outer ledge 1052 '.
It is the schematic top plan view (corresponding diagram 3 of the first substrate 10 of respectively the present embodiment 1 please also refer to Fig. 4 and Fig. 5
The position of dotted line frame) and along Fig. 4 the schematic cross-sectional view of first substrate 10 be unfolded of A-A ' cutting line, wherein to become apparent from
Technical characteristic of the invention is presented, Fig. 4 clipped is found in the element (such as pixel electrode and third insulating layer) of Fig. 5.It is
With as shown in Figures 4 and 5, the first substrate 10 of the present embodiment 1 includes: a substrate 101；One buffer layer 102 is located at the bottom
On substrate 101；Semi-conductor layer 103 is located on the buffer layer 102；One first insulating layer 104 is located at the buffer layer 102 and is somebody's turn to do
On semiconductor layer 103；One first scan line 105 and one second scan line 105 ' are located on first insulating layer 104, and respectively
Extend (X-direction of such as Fig. 4) along a first direction, and first scan line 105 of a part and the second scan line 105 ' and this
Semiconductor layer 103 is overlapped；One second insulating layer 106, be located at first scan line 105, second scan line 105 ' and this first
On insulating layer 104；One data line 107 is located in the second insulating layer 106, and prolongs along a second direction (Y-direction of such as Fig. 4)
It stretches, which is electrically connected by one first contact hole 108 with the semiconductor layer 103, wherein the second direction is different
With the first direction；And one first metal gasket 109 and one second metal gasket 110, it is located in the second insulating layer 106, this
One metal gasket 109 is electrically connected by two second contact holes 111 with the semiconductor layer 103 respectively with second metal gasket 110；Its
In, it second is swept as shown in figure 4, first contact hole 108 and two second contact hole 111 are located at first scan line 105 with this
It retouches between line 105 '.
Please continue to refer to Fig. 4 and Fig. 5, the first substrate 10 further include: a third insulating layer 112 is located at first metal
In pad 109, second metal gasket 110 and the second insulating layer 106；One first pixel electrode layer 113 is located at the third insulating layer
On 112, which is electrically connected by a third contact hole 114 with first metal gasket 109；One second
Pixel electrode layer 115 is located on the third insulating layer 112, which passes through another third contact hole 114 '
It is electrically connected with second metal gasket 110；And multiple light shield layers 116, be located at the substrate 101 and the semiconductor layer 103 it
Between, the position of the light shield layer 116 corresponds respectively to first scan line 105 region Chong Die with the semiconductor layer 103, and
The second scan line 105 ' region Chong Die with the semiconductor layer 103.
In addition, the semiconductor layer 103 can be made of a low-temperature polysilicon silicon materials, and it includes mixing in the present embodiment 1
It is miscellaneous to have appropriate admixture (such as: nitrogen or phosphorus) or source/drain region 103A and a line areas using the metal-doped formation of aluminium
The undoped channel region 103C of 103B and setting therebetween.
It will since the present embodiment 1 matches line position and its structure by adjusting the first substrate 10 please continue to refer to Fig. 6 A
The active member concentrated setting as sub-pixel switch, the second substrate 20 as colored filter substrate can suitably increase
There is the width of the black-matrix layer at the opaque active member such as this and reduce in the corresponding first substrate 10 and be somebody's turn to do corresponding
First substrate 10 does not have the width of the black-matrix layer at the opaque active member such as this, reaches and reduces integral black matrix
Ratio shared by layer and the effect of improve the aperture opening ratio of display panel.Therefore please also refer to Fig. 1 and Fig. 6 A, the display panel 100
Further include one first black-matrix layer I-I ' and one second black-matrix layer II-II ', is located in the second substrate 20, this first
The position of black-matrix layer I-I ' at least correspond to Fig. 4 first scan line 105 and second scan line 105 ' and this first
Black-matrix layer I-I ' is the strip veil extended in X direction for one, and width is enough to cover first scan line 105 simultaneously
With second scan line 105 ', and the position of second black-matrix layer II-II ' at least corresponds to the data line 107 of Fig. 4.
In the present embodiment 1, the width of first black-matrix layer I-I ' is about 5-50 μm, and second black-matrix layer II-II '
Width is about 2-20 μm.In addition, as shown in Figure 6A, which further includes the third black matrix" that a width is about 2-20 μm
Layer III-III ', it is parallel with first black-matrix layer, to avoid the adjacent pixel unit of different colours in the second substrate
Between generate colour mixture.
Therefore as shown in Figure 1, Figure 2 to shown in 5 and Fig. 6 A, by adjusting the wiring position of the first substrate 10 as array substrate
It sets and its structure, the display base plate 100 of the present embodiment 1 can reduce black-matrix layer proportion, improve opening for display panel
Mouth rate.
Embodiment 2
Embodiment 2 and embodiment 1 are substantially similar, do not exist together be only that embodiment 2 as colored filter substrate
The pixel unit configuration mode for the colored filter that the second substrate 20 ' is included is different.Fig. 6 B is please referred to, in the present embodiment
In 2, which includes the pixel group 201 of at least four different colours, wherein each pixel group 201 include four that
This adjacent and same color first pixel unit 201A, the second pixel unit 201B, third pixel unit 201C and the 4th picture
Plain unit 201D, wherein the first black-matrix layer I-I ' or the second black-matrix layer II-II ' is located at the picture of different colours
Between plain group.As adjacent pixel unit (as shown in 201A, 201B, 201C or 201D) be same color, be not required to avoid mixing
Color, therefore setting black-matrix layer (position shown in dotted line) can be not required between adjacent and homochromy pixel unit, further subtract
Few black-matrix layer proportion, to more improve the aperture opening ratio of display panel.Included by the second substrate 40 of the present embodiment 2
For pixel group in addition to the pixel group that can be red, green, blue and white four kinds of colors, fields have usually intellectual also can be according to demand
It is adjusted to the pixel group of other four kinds of colors, the present invention is not specifically limited thereto.
Other structures same as Example 1 and configuration mode the present embodiment 2 will not be described in great detail.
Embodiment 3
The line configuring mode for being different in the first substrate as array substrate of embodiment 3 and embodiment 1, and
The configuration mode of the pixel unit of the second substrate as colored filter substrate is different.
Referring to FIG. 7, being the line configuring schematic diagram of the first substrate 30 of the present embodiment 3.As shown in fig. 7, the present embodiment 3
Also through the line configuring mode on adjustment first substrate 30 by lighttight element (such as the first scan line of adjacent pixel
305, the second scan line 305 ' and thin-film transistor element T) concentrated setting.Further, referring to FIG. 8, being for the present embodiment 3
First substrate 30 line construction schematic diagram.Similar to Example 1, semiconductor layer 303, the first scan line is only presented in Fig. 8
305, the second scan line 305 ', data line 307, the first contact hole 308, the second contact hole 311, the first pixel electrode layer 313 with
The relative positional relationship of the elements such as the second pixel electrode layer 315, technical characteristic of the invention is more clearly presented.This implementation
Example 3 is similar to Example 1, and a data line 307 is to be electrically connected by one first contact hole 308 with the semiconductor layer 303, different
Being in the first pixel electrode layer 313 and the second pixel electrode layer 315 is positioned at the same side of the data line 307.This first connects
Contact hole 308 and two second contact hole 311 are also between one first scan line 305 and one second scan line 305 '.As for
Embodiment 1 substantially similar other elements structure and configuration, will not be described in great detail herein.
It is the schematic top plan view (position of 8 dotted line frame of corresponding diagram of the first substrate 30 of the present embodiment 3 please also refer to Fig. 9
Set), wherein Fig. 9 also clipped element (such as pixel electrode and third insulating layer) skill of the invention is presented to become apparent from
Art feature.As shown in figure 9, the first metal gasket 309 and the second metal gasket 310 are electrically connected by two second contact holes 311
The semiconductor layer 303, and first contact hole 308 and two second contact hole 311 be located at first scan line 305 and this second
Between scan line 305 '.The other elements structure of the present embodiment 3 and configuration are substantially similar with embodiment 1, cut along the B-B ' of Fig. 9
The schematic cross-sectional view of the first substrate 30 of secant expansion is the same as Fig. 5, will not be described in great detail herein.
With continued reference to FIG. 10, due to the present embodiment 3 by adjusting the first substrate 30 match line position and its structure, will
As the active member concentrated setting of sub-pixel switch, therefore as shown in Figure 10, the second substrate as colored filter substrate
40 can suitably increase the width for having the black-matrix layer at the opaque active member such as this in the corresponding first substrate 30 simultaneously
The width for reducing the black-matrix layer that the corresponding first substrate 30 does not have at the opaque active member such as this, it is whole to reach reduction
Ratio shared by body black-matrix layer and the effect of improve the aperture opening ratio of display panel.Therefore as shown in Figure 10, in embodiment 3,
The second substrate 40 as colored filter substrate includes the pixel group of four row different colours (such as red, green, blue and white)
401, each pixel group 401 include it is multiple along the second direction (Y-direction of such as Fig. 9) arrangement and same color pixel unit
(401A, 401B, 401C), wherein in the pixel group 401, which is located at two adjacent pixel units
Between another two adjacent pixel unit (between such as 401A and 401B or between 401B and 401C).In embodiment 3, this second
Substrate 40 also includes one second black-matrix layer II-II ', is located between the pixel group of different colours.In the present embodiment 3,
The width of first black-matrix layer I-I ' is about 5-50 μm, and the width of second black-matrix layer II-II ' is about 2-20 μ
m.Further, since adjacent pixel unit (as shown in 401A, 401B, 401C) is same color, it is not required to avoid colour mixture, therefore remove
Setting black-matrix layer can be not required at lighttight active member, between adjacent and homochromy pixel unit (such as dotted line institute
Show position), reach and reduce ratio shared by integral black matrix layer, improves the aperture opening ratio of display panel.Furthermore the present embodiment 3
In addition to the pixel group that can be red, green, blue and white four kinds of colors, fields have usual pixel group included by the second substrate 40
Skill can also be adjusted to the pixel group of red three kinds of colors of green and blue according to demand, and the present invention is not specifically limited thereto.
Therefore as shown in Figure 7 to 10, matching line position and its knot by adjusting the first substrate 30 as array substrate
Structure can also reduce black-matrix layer proportion, improve the aperture opening ratio of display panel.
Embodiment 4
The line configuring mode for being different in the first substrate as array substrate of embodiment 4 and embodiment 1, and
The configuration mode of the pixel unit of the second substrate as colored filter substrate is different.
Figure 11 is please referred to, is the line construction schematic diagram of the first substrate 50 for the present embodiment 4.It is similar to Example 1, figure
11 are only presented semiconductor layer 503, the first scan line 505, the second scan line 505 ', data line 507, the first contact hole 508, second
The relative positional relationship of the elements such as contact hole 511, the first pixel electrode layer 513 and the second pixel electrode layer 515, with apparent
Technical characteristic of the invention is presented in ground.The present embodiment 4 and embodiment 1 are different in the first pixel electrode layer 513 and one the
What two pixel electrode layers 515 were seen by top view direction, not only in the not ipsilateral of the data line 507, also it is located at first scan line
Between 505 and second scan line 505 '.More specifically, which includes one first inside edge 5051
With one first outer ledge 5052, which includes one second inside edge 5051 ' and one second outer side edges
Edge 5052 ', wherein adjacent second inside edge 5051 ' in first inside edge 5051.First pixel electrode layer 513 with
Second pixel electrode layer 515 is located at the first outer ledge 5052 and second scan line 505 ' of first scan line 505
Between second outer ledge 5052 '.As for the other elements structure and configuration substantially similar with embodiment 1, will no longer go to live in the household of one's in-laws on getting married herein
It states.
It is the schematic top plan view (position of 11 dotted line frame of corresponding diagram of the first substrate 50 of the present embodiment 4 please also refer to Figure 12
Set), wherein Figure 12 also clipped element (such as pixel electrode and third insulating layer) skill of the invention is presented to become apparent from
Art feature.As shown in figure 12, embodiment 4 is similar to Example 1, and the first metal gasket 509 and the second metal gasket 510 pass through two second
The semiconductor layer 503 is electrically connected in contact hole 511, and first contact hole 508 and two second contact hole 511 are located at this
Between first scan line 505 and second scan line 505 '.The other elements structure of the present embodiment 4 and configuration and embodiment 1 are big
The schematic cross-sectional view of similar, to be unfolded along the C-C ' cutting line of Figure 12 first substrate 50 is caused to be the same as Fig. 5, it herein will no longer
It repeats.
Figure 13 A is please referred to, is the pixel polarity schematic diagram using the first substrate 50 ' of known line structure design.Such as figure
Shown in 13A, since same data line 507 ' is to input electric signal with fixed positive-negative polarity to each pixel, therefore every row pixel
It is polarity having the same, and the pixel between not going together has different polarity.Due to adjacent same column pixel polarity that
This is on the contrary, each pixel is easy to produce crosstalk (cross-talk) to each other.It is the embodiment of the present invention conversely, please referring to Figure 13 B
The pixel polarity schematic diagram of 4 first substrate 50.Though the data line 507 of the present embodiment 4 still inputs news with fixed positive-negative polarity
Number to each pixel, so because being designed using the line configuring of the present embodiment 4, driven in a manner of row reversion (column inversion)
Dynamic pixel, the pixel polarity of adjacent same column is mutually the same, is not likely to produce crosstalk.Therefore, the first substrate 50 of the present embodiment 4 has
The advantages of low-power consumption, low crosstalk.
It is the second substrate 60 of the first substrate 50 of corresponding diagram 11 please continue to refer to Figure 14, wherein Figure 14 is to be overlapped
The second substrate 60 is presented in the mode of 50 local line of first substrate of Figure 11, with the black square to become apparent from display the second substrate
Relative positional relationship between battle array layer and pixel group and the route of first substrate.Since the present embodiment 4 is by adjusting first base
Plate 50 matches line position and its structure, reduces the active member of sub-pixel switch, therefore as shown in figure 14, as colorized optical filtering
The second substrate 60 of plate base can appropriate adjustment have in the corresponding first substrate 50 it is black at the opaque active member such as this
The position of color matrix layer, and the corresponding pixel unit of the sub-pixel of adjacent and unshared same first contact hole switch is configured
For homochromy pixel group, ratio shared by integral black matrix layer is reduced and the function of the aperture opening ratio that improves display panel to reach
Effect.Therefore as shown in figure 14, in embodiment 4, the second substrate 60 as colored filter substrate does not include at least three not
The pixel group 601 of same color (such as red, green, blue), each pixel group 601 include two adjacent to each other and same colors and along this
The pixel unit (601A, 601B and 601C) of one direction arrangement, wherein in Yu Suoshu pixel group 601, first black matrix"
Layer I-I ' is positioned at the pixel group 601 between and along a first direction (X-direction in such as figure) extension, and second black matrix"
Layer II-II ' is between two sets of adjacent pixels 601.Further, since adjacent pixel unit (601A, 601B or 601C) is phase
Same color is not required to avoid colour mixture, therefore can be not required to be arranged between adjacent and homochromy pixel unit (601A, 601B or 601C)
Second black-matrix layer II-II ' (such as between pixel unit 601A) reaches and reduces ratio shared by integral black matrix layer, mentions
The aperture opening ratio of high display panel.Furthermore though the present embodiment 4 is to be painted pixel unit 601A with rectangle, as long as can so reach known
The demand and the present invention of black-matrix layer improve the effect of aperture opening ratio, and the black-matrix layer of any shape all can be used, therefore this hair
The bright shape for being not specially limited pixel unit.Furthermore pixel group included by the second substrate 60 of the present embodiment 4 is removed
Outside red, green and blue three-color pixel group, fields tool usually intellectual also can be adjusted to red, green, blue according to demand
And the pixel group of white four kinds of colors, the present invention are not specifically limited thereto.
It is only for the sake of illustration for above-described embodiment, and the interest field that the present invention is advocated certainly should be with right
Subject to described in claimed range, not just the above examples.
Claims (13)
1. a kind of display panel comprising a first substrate, a display layer and a second substrate, wherein the display layer is located at should
Between first substrate and the second substrate, which includes:
One substrate；
Semi-conductor layer is located on the substrate；
One first insulating layer is located on the semiconductor layer；
One first scan line and one second scan line are located on first insulating layer, and extend respectively along a first direction, and one
Partial first and second scan line is Chong Die with the semiconductor layer；
One second insulating layer is located on first scan line, second scan line and first insulating layer；
One data line, be located at the second insulating layer on, and along a second direction extend, the data line by one first contact hole with
The semiconductor layer is electrically connected, wherein the second direction difference and the first direction；
One first metal gasket and one second metal gasket are located in the second insulating layer, first metal gasket and second metal gasket
It is electrically connected respectively by two second contact holes and the semiconductor layer；
One third insulating layer is located in first metal gasket, second metal gasket and the second insulating layer；
One first pixel electrode layer is located on the third insulating layer, and first pixel electrode layer is by a third contact hole and is somebody's turn to do
First metal gasket is electrically connected；And
One second pixel electrode layer is located on the third insulating layer, second pixel electrode layer by another third contact hole and
Second metal gasket is electrically connected；
Wherein, first contact hole and two second contact hole are located between first scan line and second scan line.
2. display panel as described in claim 1, wherein first pixel electrode layer is adjacent to second pixel electrode layer
The same side of the data line.
3. display panel as described in claim 1, wherein first pixel electrode layer is adjacent to second pixel electrode layer
The data line it is not ipsilateral, and first scan line includes one first inside edge and one first outer ledge, this second is swept
Retouching line includes one second inside edge and one second outer ledge, wherein adjacent second inner side edge in first inside edge
Edge.
4. display panel as claimed in claim 3, wherein first pixel electrode layer be overlapped in first scan line this
One inside edge and first outer ledge, and second pixel electrode layer is overlapped in second inner side edge of second scan line
Edge and second outer ledge.
5. display panel as claimed in claim 3, wherein first pixel electrode layer is located at second pixel electrode layer should
Between first outer ledge of the first scan line and the second outer ledge of second scan line.
6. display panel as described in claim 1 further includes multiple light shield layers, be located at the substrate and the semiconductor layer it
Between, the position of the light shield layer corresponds respectively to first scan line region Chong Die with the semiconductor layer and this second is swept
Retouch the line region Chong Die with the semiconductor layer.
7. display panel as claimed in claim 6 further includes a buffer layer, between the substrate and the semiconductor layer,
And the light shield layer is located between the substrate and the buffer layer.
8. display panel as described in claim 1 further includes one first black-matrix layer and one second black-matrix layer, is located at
Between the first substrate and the second substrate, which at least covers first scan line or second scanning
Line, and second black-matrix layer at least covers the data line.
9. display panel as claimed in claim 8, wherein the width of first black-matrix layer is between 5 μm to 50 μm.
10. display panel as claimed in claim 8, wherein the second substrate is a colored filter substrate, the second substrate
Pixel group including at least four different colours, wherein each pixel group includes four adjacent to each other and same color first
Pixel unit, the second pixel unit, third pixel unit, with the 4th pixel unit, wherein first black-matrix layer or this
Two black-matrix layers are located between the pixel group of different colours.
11. display panel as claimed in claim 8, wherein the second substrate is a colored filter substrate, the second substrate
It include the pixel group of at least three row different colours, each pixel group includes multiple along second direction arrangement and same color
Pixel unit, wherein in the pixel group, which is located at two adjacent pixel units and another two adjacent pixel
Between unit.
12. display panel as described in claim 1 further includes one first black-matrix layer and one second black-matrix layer, position
Between the first substrate and the second substrate, which at least covers first scan line or second scanning
Line, and second black-matrix layer at least covers the data line of a part.
13. display panel as claimed in claim 12, wherein the second substrate is a colored filter substrate, second base
Plate includes the pixel group of at least three different colours, and each pixel group includes two adjacent in the first direction and identical face
The pixel unit of color, wherein first black-matrix layer or second black-matrix layer are located between the pixel group of different colours.
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| CN201410718861 | 2014-12-02 | ||
| CN2014107188613 | 2014-12-02 |
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| CN105988255B true CN105988255B (en) | 2019-07-09 |
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| CN201510074172.8A Active CN105988255B (en) | 2014-12-02 | 2015-02-12 | Display panel |
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| CN111754934A (en) * | 2020-06-22 | 2020-10-09 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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|---|---|---|---|---|
| US6323918B1 (en) * | 1996-12-10 | 2001-11-27 | Fujitsu Limited | Liquid crystal display device and process for production thereof |
| CN1379276A (en) * | 2001-03-30 | 2002-11-13 | 三洋电机株式会社 | Dynamic matrix type display device having complementary capacitance on each pixel |
| US6630971B1 (en) * | 1999-04-02 | 2003-10-07 | Lg.Philips Lcd Co., Ltd. | Multi-domain liquid crystal display device |
| CN103309076A (en) * | 2012-03-14 | 2013-09-18 | 株式会社东芝 | Liquid crystal display apparatus including interference filters |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120147314A1 (en) * | 2009-08-24 | 2012-06-14 | Sharp Kabushiki Kaisha | Display device and color filter substrate |
-
2015
- 2015-02-12 CN CN201510074172.8A patent/CN105988255B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6323918B1 (en) * | 1996-12-10 | 2001-11-27 | Fujitsu Limited | Liquid crystal display device and process for production thereof |
| US6630971B1 (en) * | 1999-04-02 | 2003-10-07 | Lg.Philips Lcd Co., Ltd. | Multi-domain liquid crystal display device |
| CN1379276A (en) * | 2001-03-30 | 2002-11-13 | 三洋电机株式会社 | Dynamic matrix type display device having complementary capacitance on each pixel |
| CN103309076A (en) * | 2012-03-14 | 2013-09-18 | 株式会社东芝 | Liquid crystal display apparatus including interference filters |
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| CN105988255A (en) | 2016-10-05 |
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