CN105981001B

CN105981001B - System and method for abstracting storage media device through full-duplex queued command interface

Info

Publication number: CN105981001B
Application number: CN201480075072.0A
Authority: CN
Inventors: J·D·比森; J·B·耶茨
Original assignee: Concurrent Ventures LLC
Current assignee: Concurrent Ventures LLC
Priority date: 2013-12-06
Filing date: 2014-12-08
Publication date: 2020-06-02
Anticipated expiration: 2034-12-08
Also published as: EP3077915A1; CN105981001A; EP3077915A4; WO2015085315A1

Abstract

The simplified host accesses SATA and SAS storage media devices by abstracting the SATA and SAS protocols with one full duplex protocol that supports full command queuing for each storage media device, whether SATA or SAS, where the abstraction protocol is performance-centric and supports common high-level read and write access to a pool of storage media devices, where each storage media device may have a SATA or SAS interface. The abstract protocol is link independent and may be carried over a number of direct-attached or network interfaces including, but not limited to, a PCIe interface, an ethernet (e.g., 1GbE, 10GbE, 40GbE, or 100GbE) interface, an infiniband interface, a thunderbolt interface, a firewall interface, a USB interface, and/or a custom interface.

Description

System and method for abstracting storage media device through full-duplex queued command interface

Technical Field

The present invention generally relates to the field of memory devices. More particularly, the present invention relates to systems and methods for abstracting SATA and/or SAS storage media devices through a full duplex queued command interface to increase performance, reduce host overhead, and simplify scaling storage media devices and systems.

Background

Current state of the art for directly interacting with storage media devices (rotating hard disks, solid state disks, RAM drives, etc.) is for using interface protocols such as SATA (serial ATA, where ATA is advanced technology attachment) or SAS (serial attached SCSI). Both of these interfaces have originated from the older parallel interfaces (PATA and SCSI). The common protocols remain unchanged from the original parallel specification and they are now transported only over a serial interface rather than over a shared access bi-directional parallel bus. In the case of SATA, this limits the high speed full duplex serial link to be half duplex efficiently because full command queuing and out of order responses are not supported by themselves. While Native Command Queuing (NCQ) is supported by a subset of SATA storage media devices, it only addresses some data transfers and not all commands, and typically does not support interleaved read and write commands. SAS supports Tagged Command Queuing (TCQ) to overcome some of these limitations with SATA. When accessing a mixture of devices (some SATA, some SAS), the host must support and manage both protocols. The host software layer interacting with SATA or SAS must support their high protocol overhead.

SATA may have a port multiplier and SAS may have a port expander. Each of these devices splits the egress SATA or SAS link to another port, respectively. Either of the SATA or SAS protocols are paths from the host into these devices, and thus, the host must process SATA or SAS. In addition, this link bandwidth between the multiplier/expander and the host is shared between downstream storage media devices. SATA port multipliers are commonly used to increase storage capacity, thereby subdividing the bandwidth between the controller and the port multiplier. SATA port multipliers cannot be cascaded, limiting the increase in storage capacity. Furthermore, not all SATA controllers support port multipliers. SAS port expanders may also be used to increase storage capacity, but also allow several SAS links to hosts to be combined (joined) together into one port to increase bandwidth between the controller and the port multiplier. It is possible that the SAS interface carries SATA through SAS-STP (SASSATA transport protocol).

In the prior art, as shown in FIG. 1, host computer or processing unit 100 supports SATA and/or SAS as devices that communicate with SATA storage media devices (SATA SMD)106&110 and SAS storage media device (SAS SMD)108, respectively. The physical interface to the SMD is through SATA controller 102 or

SAS controllers

104 and 105, each communicating with the SMD through a serial interface. The SAS controller is capable of interacting with both SAS SMDs (e.g., SAS controller 104 interacting with SAS SMD 108) and SATA SMDs (e.g., SAS controller 105 interacting with SATA SMD 110), where SATA SMD is supported through SAS-STP (SAS SATA transport protocol). SATA controller is only able to interact with SATA SMDs (i.e., SATA controller 102 is only able to interact with SATA SMD devices like SATA SMD 106).

Alternatively, as shown in fig. 2, SATA controller 202 can interact with port multiplier 204 to connect to one or more SATA SMDs. Likewise, SAS controller 206 may interact with port expander 208 to connect to one or more SAS SMD or SATA SMD.

However, prior art systems such as those described above do not provide systems and methods for abstracting SATA and/or SAS storage media devices through a full duplex queued command interface to increase performance, reduce host overhead, and simplify scaling storage media devices and systems. Embodiments of the present invention are an improvement over prior systems and methods.

Disclosure of Invention

In one embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, comprising: at least one host; a host controller including a host processing unit, an optional host memory, a host controller interface in communication with the host computer, and at least one host controller control link interface; and at least one edge controller comprising an edge processing unit, an optional edge memory, an edge controller control link interface in communication with the host controller through the host controller control link interface, and at least one storage media device interface in communication with the at least one storage media device, wherein the host controller and the edge controller communicate through an abstraction protocol comprising a full duplex protocol supporting full command queuing of the at least one storage media device.

In another embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, comprising: at least one host; a first host controller including a first host processing unit, an optional first host memory, a first host controller interface in communication with the host, and at least one first host controller control link interface; and at least one first edge controller, the first edge controller comprising: a first edge processing unit, an optional first edge memory, a first edge controller control link interface in communication with a first host controller through a first host controller control link interface, an optional forwarding link interface in communication with a second edge controller to forward abstracted protocol packets from the first host controller to the second edge controller, the second edge controller comprising a second edge processing unit, an optional second edge memory, a second edge controller control link interface allowing the second edge processing unit to communicate with the forwarding link interface, and at least one second host controller control link interface in communication with the second edge controller; an optional second master controller comprising a second master processing unit, an optional second master memory, a second master controller interface in communication with the first edge processing unit, and at least one second master controller control link interface in communication with the second edge controller; and at least one storage media device interface in communication with the at least one storage media device, wherein the first and second host controllers, the first edge controller, and the second edge controller communicate via an abstraction protocol that includes a full duplex protocol that supports full command queuing for the at least one storage media device.

In one embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, comprising: at least one host; a host controller including a host processing unit, an optional host memory, a host controller interface in communication with the host computer, and at least one host controller control link interface; and at least one edge controller comprising an edge processing unit, an optional edge storage, an edge controller control link interface in communication with the host controller through the host controller control link interface, a SATA port multiplier in communication with the plurality of first storage media devices through a SATA protocol, and a SAS port expander in communication with the plurality of second storage media devices through a SAS protocol, wherein the host controller and the edge controller communicate through an abstraction protocol that supports both serial ata (SATA) and Serial Attached Scsi (SAS) storage media devices simultaneously, the abstraction protocol comprising a full duplex protocol that supports full command queuing of the first and second storage media devices.

In another embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, comprising: at least one host; a host controller including a host processing unit, a host controller interface in communication with the host, and at least one host controller control link interface; and at least one edge controller comprising an edge processing unit, an optional edge memory, an edge controller control link interface in communication with the host controller through the host controller control link interface, a port multiplier in communication with the plurality of storage media devices, wherein the host controller and the edge controller communicate through an abstraction protocol comprising a full duplex protocol supporting full command queuing of the storage media devices.

In another embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, comprising: at least one host; a host controller including a host processing unit, a host controller interface in communication with the host, and at least one host controller control link interface; and at least one edge controller comprising an edge processing unit, an optional edge memory, an edge controller control link interface in communication with the host controller through the host controller control link interface, and a port extender in communication with the plurality of storage media devices, wherein the host controller and the edge controller communicate through an abstraction protocol comprising a full duplex protocol supporting full command queuing of the storage media devices.

Drawings

The present disclosure is described in detail with reference to the accompanying drawings in accordance with one or more different examples. The drawings are provided for illustrative purposes only and depict only examples of the disclosure. These drawings are provided to facilitate the reader's understanding of the disclosure and should not be construed to limit the breadth, scope, or applicability of the disclosure. It should be noted that for clarity and ease of illustration, the drawings are not necessarily drawn to scale.

FIG. 1 illustrates a prior art host communicating with SATA and SAS controllers via SATA, SAS, or SAS-STP protocols.

FIG. 2 shows a prior art SATA controller in communication with a SATA port multiplier and a SAS controller in communication with a SAS expander.

FIG. 3 illustrates one example of a master controller of the present invention communicating with a host and an edge controller.

Fig. 4A through 4C illustrate various non-limiting examples of edge controllers of the present invention.

FIGS. 5A and 5B illustrate a system level overview of a non-limiting example of a master controller of the present invention interacting with one edge controller in communication with a storage media device and another edge controller in communication with other edge controllers and other storage media devices.

FIG. 6 illustrates an edge controller of the present invention capable of communicating with one or both of a SATA port multiplier, a SAS port expander.

Detailed Description

While the invention is shown and described in its preferred embodiments, the invention may be embodied in many different configurations. With the understanding of the present disclosure, preferred embodiments of the present invention, depicted in the drawings and described in detail herein, are to be considered as exemplifications of the principles of the invention and the relevant functional specifications for its construction and are not intended to limit the invention to the embodiments illustrated. Those skilled in the art will envision many other variations that are within the scope of the invention.

It should be noted that in this description, references to "one embodiment" or "an embodiment" mean that the referenced feature is included in at least one embodiment of the present invention. Additionally, separate references to "one embodiment" in this description do not necessarily refer to the same embodiment; however, as will be apparent to one of ordinary skill in the art, such embodiments are neither mutually exclusive nor distinct unless otherwise specified. Thus, the invention may encompass any kind of combination and/or integration of the embodiments described herein.

The present invention simplifies hosts accessing SATA and SAS storage media devices by abstracting the SATA and SAS protocols with a full duplex protocol that supports full command queuing for each storage media device, whether SATA or SAS. The present invention includes both hardware (system-architecture) and software (method-abstraction protocol). The simplified abstraction protocol provides high-level access commands to the storage media device. The high-level commands may eventually resolve several commands at the SATA or SAS interface, allowing the host to issue and track fewer commands. An example of this is moving large amounts of data using commands that are not supported by the SATA or SAS protocols themselves. The SATA or SAS interface of a storage media device is pushed to the edge, away from the host and towards the storage media device supported by the SATA or SAS interface. Pushing the SAS/SATA protocol to the edge simplifies the host/controller because it does not implement the traditional SAS/SATA protocol, it can do things that best suit its application. Since SAS/SATA is pushed to the edge and abstracted to the host, SATA and SAS can be mixed without affecting the host (the host is SAS/SATA unrelated). Even when the SATA tunnel passes through SAS (STP), the host is using the SATA/STP protocol. The host typically does not need to be aware of the interface protocol of the storage media device during operation. In addition, recoverable storage media device errors (e.g., retries) can be handled at the edge local to the storage media device, thereby offloading the task from the host. Where data replication is desired, processing can also be done at the edge, offloading the task from the host. This offloading may be important for SATA if NCQ is to be used, because any remaining queued read or write commands will be flushed if an error occurs, requiring the commands to be reissued. The abstract protocol supports flow control between the host and the edge. Since SATA and SAS handle flow control differently, such storage media device flow control is handled at the edge without burdening the host.

This abstraction protocol is performance-centric and supports common high-level read and write access to a pool of storage media devices, each of which may have a SATA or SAS interface. The abstract protocol is link independent and may be carried over a number of direct-attached or networked interfaces including, but not limited to, a PCIe interface, an ethernet (e.g., 1GbE, 10GbE, 40GbE, or 100GbE) interface, an Infiniband interface, a USB interface, a ThunderBolt interface, a firewall (Firewire) interface, and/or a custom interface. The abstract protocol link bandwidth need not be related to the SATA or SAS interface of the individual storage media device. Data written to and read from the storage media device may be pushed by the source or may be pulled by the destination. For example, when the link is ethernet, it is usually optimal to send block data with a command packet in the case of writing, and to send block data with a response packet in the case of reading (pushing). When the link is PCIe, it is usually best to retrieve the block data separately from the issued command or response when the command is ready to be executed or a response is received (injected).

The abstract protocol supports packet-switched routing fabric and error recovery. The routing may be based on a logical address, WWN (world wide web number-unique global ID number) or physical address. The logical address or WWN may be mapped to a physical address (e.g., via a lookup table). Such a mapping may be updated statically or dynamically based on a recovery process when the storage media device is (i) inserted into or removed from the system and/or (ii) powered on or off.

As shown in FIG. 3, the host controller 304 includes (i) one or more host processing units 306 that perform processing on a primary side of the abstract protocol and communicate with at least one host 302 via a host controller interface 308, which is connected to the host 302 via a host link 320, and (ii) one or more control link interfaces 310-312, which one or more control link interfaces 310-312 communicate with one or more edge controllers 316-318 via

control links

320 and 322. The host controller 304 may optionally have its own main memory 314, with the main memory 314 being used by functions contained for processing, buffering, queuing, and the like. Main memory 314 may be internal or external to main controller 304, main memory 314 comprising SRAM, DRAM, RLDRAM, FLASH, or a combination thereof. Host 302, host controller 304, and

edge controller

316 and 318 together form a routable packet-switched network supported by the abstraction protocol. It is possible that one or more hosts, master controllers, and/or edge controllers reside on the same physical device (e.g., a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), or any combination of different devices). Host link 320 may be implemented with a directly addressable memory interface, Universal Serial Bus (USB), ethernet, peripheral component interconnect express (PCIe), Infiniband, thunderbolt, firewall, and/or other common or custom interconnect technologies. The control links 320 and (&)322 may also be implemented with a directly addressable memory interface, USB, Ethernet, PCIe, infiniband, thunderbolt, firewall, and/or other public or custom interconnect technologies. Each of host link 320 and control links 320&322 may be implemented with different interconnect technologies, which need not be the same. For example, host link 320 may be implemented with PCIe and

control links

320 and 322 may be implemented with 10Gb Ethernet.

FIG. 4A depicts a non-limiting example of an edge controller. The edge controller 402 contains (i) one or more edge processing units 404 that perform edge-side processing of the abstract protocol and communicate with one or more master controllers 406 and 408 through control link interfaces 410 and 412, the control link interfaces 410 and 412 communicating with the master controllers 406 and 408 through

control links

414 and 416; (ii) one or

more SMD interfaces

418 and 420 in communication with one or more SMDs 422 and 424 via SATA and/or

SAS links

426 and 428; (iii) optionally, one or more forwarding link interfaces 430 communicate with other edge controllers 432 over control links 448, the control links 448 being used to forward these abstract protocol packets from the master controller 406 or 408 (received over control link interfaces 410 and 412 (control link interfaces 410 and 412 are not designated to the edge controller 402 that receives these abstract protocol packets) to the other edge controller 432; and (iv) optionally, one or

more master controllers

434 and 436 that communicate with

other edge controllers

438 and 440 when the edge processing unit 404 wishes to initiate an abstraction protocol message to the

other edge controllers

438 and 440. The forwarding link interface 430 may be functionally equivalent to the control link interfaces 410 and 412 in some embodiments. Edge controller 402 may optionally have its own edge memory 446 used by functions contained in the data for processing, buffering, queuing, etc. The edge memory 446 may be internal or external to the edge controller 402, the edge memory 446 comprising SRAM, DRAM, RLDRAM, FLASH memory (FLASH), or a combination thereof. It is possible that the plurality of edge controllers share the same edge memory while physically located close edge controllers allow sharing of the same edge memory. It is also possible that the edge memory and the main memory associated with the main controller are combined into one memory, while the physically close main controller and edge controller allow the combination.

Fig. 4B depicts another non-limiting example of an edge controller acting as a forwarding/routing device. The edge controller 474 contains (i) one or more edge processing units 460 that perform edge-side processing of the abstract protocol and communicate with one or

more master controllers

448 and 450 via control link interfaces 456 and 458, which control link interfaces 456 and 458 communicate with the

master controllers

448 and 450 via

control links

452 and 454; and (ii) one or more master controllers 462 and 468 that communicate with

other edge controllers

466 and 472 over

control links

464 and 472 when the edge processing unit 460 wishes to initiate an abstract protocol message to the

other edge controllers

466 and 472. Note that in this embodiment, the edge controller 474 acts as a forwarding/routing device because there is no storage media device connected to it. The edge controller 474 may optionally have its own edge memory 476, which edge memory 476 is used by functions included for processing, buffering, queuing, and the like. The edge memory 476 may be internal or external to the edge controller 474, the edge memory 476 comprising SRAM, DRAM, RLDRAM, flash memory, or combinations thereof. It is possible that multiple edge controllers share the same edge memory, while physically close edge controllers allow sharing of the same edge memory. It is also possible that the edge memory and the main memory associated with the main controller are combined into one memory, while the physically close main controller and edge controller allow the combination.

FIG. 4C depicts another non-limiting example of an edge controller that is a variation of the edge controller shown in FIG. 4A. The edge controller 402 'contains (i) one or more edge processing units 404' that perform edge-side processing of the abstract protocol and communicate with one or more master controllers 406 'and 408' through control link interfaces 410 'and 412', the control link interfaces 410 'and 412' communicating with the master controllers 406 'and 408' through control links 414 'and 416'; (ii) one or more SMD interfaces 418 'and 420' in communication with one or more SMDs 422 'and 424' via SATA and/or SAS links 426 'and 428'; (iii) optionally, one or more forwarding link interfaces 430 'that communicate with the other edge controller 432' over a control link 448', the control link 448' being used to forward these abstract protocol packets from the master controller 406 'or 408' to the other edge controller 432 'received over control link interfaces 410' and 412 '(control link interfaces 410' and 412 'are not designated to edge controller 402' that receives these abstract protocol packets); and (iv) optionally, one or more master controllers 434' and 436 ', master controller 434' communicating with edge controller 432' over control link 442' and master controller 436 ' communicating with edge controller 440' over control link 444' when edge processing unit 404' wishes to initiate an abstract protocol message to edge controllers 432' and/or 440 '. The forward link interface 430' may be functionally equivalent to the control link interfaces 410' and 412' in some embodiments. The edge controller 402' may optionally have its own edge memory 446', which edge memory 446' is used by functions contained in the data for processing, buffering, queuing, etc. The edge memory 446' may be internal or external to the edge controller 402', the edge memory 446' comprising SRAM, DRAM, RLDRAM, flash memory, or a combination thereof. It is possible that multiple edge controllers share the same edge memory, while physically close edge controllers allow sharing of the same edge memory. It is possible that the edge memory and the main memory associated with the main controller are combined into one memory while the physically close main controller and edge controller allow such combination. For simplicity, control links 448 'and 442' are shown as each connected to the edge controller 432', however, the control links 448' and control links 442 'may be combined into a single connection (e.g., mixed or multiplexed together) to the edge controller 432'.

In one embodiment as shown in FIG. 5A, master controller 502 communicates with one or

more edge controllers

504 and 506 via

control links

508 and 510, respectively. The edge controller 504 communicates with a plurality of SMDs 512 to 514 via SATA and/or

SAS links

516 and 518 depending on the type of SMD (i.e., SATA or SAS). Edge controller 506 communicates with two

other edge controllers

528 and 530 and with multiple SMDs 520-522 via SATA and/or

SAS links

524 and 526 depending on the type of SMD (i.e., SATA or SAS). Edge controller 528 communicates with edge controller 506 via a forwarding link interface 532 and a control link 534. In this case, the abstract protocol packet from the master controller 502 may be forwarded or proxied to another edge controller 528 based on certain criteria, including but not limited to being forwarded or proxied to a broadcast or destination that is not local to the edge controller 506. Another edge controller 530 communicates with edge controller 506 through master controller 536 and control link 538. In this case, edge controller 506 may be providing an abstract protocol command in which some action is required at edge controller 506 and some action is required at a different edge controller 530, which involves splitting the abstract protocol command into multiple abstract protocol commands, each of which is designated for one or more other edge controllers 530. The edge controller 528 communicates with the plurality of

SMDs

540 and 542 over SATA and/or SAS links 544 and 546 depending on the type of SMD (i.e., SATA or SAS). Edge controller 530 communicates with a plurality of

SMDs

548 and 549 via SATA and/or

SAS links

550 and 552 depending on the type of SMD (i.e., SATA or SAS). The

multiple control links

508, 510, 534, and 538 can be implemented with the same or different interconnect technologies including, but not limited to, directly addressable memory interfaces, USB, Ethernet, PCIe, Infiniband, thunderbolt, and/or firewalls. In some cases, such as in the case of ethernet, each

control link

508, 510, 534, and/or 538 may be the same network.

In another embodiment as shown in FIG. 5B, master controller 502 communicates with one or more edge controllers 504 'and 506' via control links 508 'and 510', respectively. The edge controller 504' communicates with the plurality of SMDs 512 ' to 514' via SATA and/or SAS links 516 ' and 518' depending on the type of SMD (i.e., SATA or SAS). The edge controller 506' communicates with two other edge controllers 528' and 530' and with multiple SMDs 520' through 522 ' over SATA and/or SAS links 524' and 526' depending on the type of SMD (i.e., SATA or SAS). Edge controller 528 'communicates with edge controller 506' via forwarding link interface 532 'and control link 534'. In this case, the abstract protocol packet from the master controller 502 ' may be forwarded or proxied to another edge controller 528' based on certain criteria, including but not limited to, a broadcast or destination that is not local to the edge controller 506 '. Edge controller 506 'communicates with edge controller 528' via master controller 536 'and control link 538'. The edge controller 506 'may be providing an abstract protocol command in which some action is required at the edge controller 506' and some action is required at a different edge controller 528', including splitting the abstract protocol command into a plurality of abstract protocol commands, each of which is designated for at least one other edge controller 528'. The edge controller 528' communicates with a plurality of SMDs 540 ', 542 ', 548' and 549' via SATA and/or SAS links 544', 546 ', 550' or 552 ' depending on the type of SMD (i.e., SATA or SAS). The multiple control links 508 ', 510', 534', and 538' may be implemented using the same or different interconnect technologies including, but not limited to, a directly addressable memory interface, USB, ethernet, PCIe, infiniband, lightning, and/or firewall. In some cases, such as ethernet, each control link 508 ', 510', 534', and/or 538' may be the same network. For simplicity, control links 534 'and 538' are shown as each connected to edge controller 528', however, control link 534' and control link 538 'may be combined into a single connection (e.g., mixed or multiplexed together) to edge controller 528'.

In another embodiment as shown in FIG. 6, edge controller 602 communicates with SAS port expander 606, which in turn communicates with one or more SAS ports and or

SATA SMD

616 and 620. Edge controller 602 may also communicate with SATA port multiplier 604 over SATA link 608, which in turn communicates with one or

more SATA SMDs

612 and 614.

Although FIG. 6 depicts both port multiplier 604 and port expander 606, it should be recognized that port multiplier only and port expander only embodiments are within the scope of the present invention.

For example, in one embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, the routable packet-switched network comprising: at least one host; a host controller including a host processing unit, an optional host memory, a host controller interface in communication with the host computer, and at least one host controller control link interface; and at least one edge controller comprising an edge processing unit, an optional edge memory, an edge controller control link interface in communication with the host controller through the host controller control link interface, a port multiplier in communication with the plurality of storage media devices, wherein the host controller and the edge controller communicate through an abstraction protocol comprising a full duplex protocol supporting full command queuing of the storage media devices.

In another embodiment, the present invention provides a routable packet-switched network supported by an abstraction protocol, the routable packet-switched network comprising: at least one host; a host controller including a host processing unit, an optional host memory, a host controller interface in communication with the host computer, and at least one host controller control link interface; and at least one edge controller comprising an edge processing unit, an optional edge memory, an edge controller control link interface in communication with the host controller through the host controller control link interface, and a port extender in communication with the plurality of storage media devices, wherein the host controller and the edge controller communicate through an abstraction protocol comprising a full duplex protocol supporting full command queuing of the storage media devices.

For simplicity, the system is described as being within a chassis, but it should be recognized that the entire system need not be co-located within one chassis or at one physical location, as one or more individual units may be located as part of different chassis/locations.

The above-described features and applications may be implemented as a software process specifically specified as a set of instructions recorded on a computer-readable storage medium (also referred to as computer-readable medium). When executed by one or more processing units (e.g., one or more processors, processor cores, or other processing units), the instructions cause the processing unit(s) to perform the actions indicated in the instructions. Embodiments within the scope of the present disclosure may also include tangible and/or non-transitory computer-readable storage media for carrying or having computer-executable instructions or data structures stored therein. Such non-transitory machine-readable storage media can be any available media that can be accessed by a general purpose or special purpose computer, including the functional design of any special purpose processor. By way of example, such non-transitory computer-readable media can include, but is not limited to, flash memory, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to carry or store desired program code means in the form of computer-executable instructions, data structures, or processor chip design. The computer readable medium does not contain carrier waves or electronic signals that are transmitted wirelessly or through a wired connection.

Computer-executable instructions comprise, for example, instructions and data which cause a general purpose computer, special purpose computer, or special purpose processing device to perform a certain function or group of functions. Computer-executable instructions also include program modules that are executed by computers in stand-alone or network environments. Generally, program modules include routines, programs, components, data structures, objects, and functions inherent in the design of special-purpose processors, etc. that perform particular tasks or implement particular abstract data types. Computer-executable instructions, associated data structures, and program modules represent examples of the program code means for executing steps of the methods disclosed herein. The particular sequence of such executable instructions or associated data structures represents examples of corresponding acts for implementing the functions described in such steps.

A computer program (also known as a program, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. The computer programs may correspond to files in a file system but do not necessarily correspond. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

These aforementioned functions may be implemented in digital electronic circuitry, computer software, firmware, or hardware. The techniques may be implemented using one or more computer program products. The processes and logic flows can be performed by one or more programmable processors and by one or more programmable logic circuits. General purpose and special purpose computing devices and storage devices may be interconnected by a communication network.

Some embodiments include electronic components such as microprocessors, storage and memory storing computer program instructions in a machine-readable or computer-readable medium (alternatively referred to as a computer-readable storage medium, machine-readable medium, or machine-readable storage medium). Some examples of such computer-readable media include RAM, ROM, compact disk read-only (CD-ROM), compact disk recordable (CD-R), compact disk rewritable (CD-RW), digital versatile disk read-only (e.g., DVD-ROM, dual-layer DVD-ROM), various DVD recordable/rewritable (e.g., DVD-RAM, DVD-RW, DVD + RW, etc.), flash memory (e.g., SD card, mini-SD card, etc.), magnetic or solid state hard drives, Blu-ray CD recordable only, ultra-dense optical disks, any other optical or magnetic media, and floppy disks. The computer-readable medium may store a computer program that is executable by at least one processing unit and that includes a set of instructions for performing various operations. Examples of computer programs or computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer, electronic component, or microprocessor using a compiler.

Although the above discussion has primarily referred to microprocessor or multi-core processors executing software, some embodiments are performed by one or more integrated circuits, such as Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs). In some embodiments, such integrated circuits execute instructions stored on/within the circuit itself. In some embodiments, software, such as with an FPGA, an example of which is an FPGA programming file, may be used to describe the hardware circuitry. Such FPGA programming files may also include computer programs, machine code, microcode, firmware, and other software. The FPGA programming file may be stored within an FPGA, an ASIC, a computer readable storage medium, a machine readable medium, or a machine readable storage medium.

As used in this specification and any claims of this application, the terms "computer," "server," "processor," and "memory" all refer to electronic or other technical devices. These terms do not include humans or groups of humans. For the purposes of this specification, the term display or display means displaying on an electronic device. As used in this specification and any claims of this application, the terms "computer-readable medium" and "computer-readable medium" are entirely limited to tangible objects that store information in a form readable by a computer. These terms do not include any wireless signals, wire-line downloaded signals, and any other transitory signals.

Those skilled in the art will appreciate that other embodiments of the disclosure may be practiced in network computing environments with many types of computer system configurations, including personal computers, hand-held devices, multi-processor systems, ASIC-based systems, FPGA-based systems, microprocessor-based or programmable consumer electronics, network PCs, minicomputers, mainframe computers, and the like. Embodiments may also be practiced in distributed computing environments where tasks are performed by local and remote processing devices that are linked (either by hardwired links, wireless links, or by a combination of hardwired or wireless links) through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

It should be understood that any specific order or hierarchy of steps in the processes discussed is an illustration of example methods. It should be understood that the specific order or hierarchy of steps in the process may be rearranged or performed in the order shown, based on design preferences. Some of this step may be performed simultaneously. For example, in some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components shown above should not be understood as requiring such separation, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Various modifications to these aspects will be readily apparent, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the claims, wherein reference to an element in the singular is not intended to mean "one and only one" but rather "one or more" unless specifically so stated. The terms "a", "an", and "the" mean "one or more", unless expressly specified otherwise. Pronouns in the male (e.g., his) include female and neutral (e.g., her and its), and vice versa. Headings and sub-headings, if any, are used for convenience only and do not limit the subject matter.

A phrase such as an "aspect" does not imply that such aspect is essential to the subject matter, or that such aspect applies to all configurations of the subject matter. The disclosure relating to aspects is applicable to all configurations or one or more configurations. A phrase, for example, an aspect may refer to one or more aspects and vice versa. A phrase such as "configured" does not imply that such configuration is essential to the subject technology or that such configuration applies to all configurations of the subject technology. The disclosure relating to configurations is applicable to all configurations or one or more configurations. A phrase, for example, a configuration may refer to one or more configurations and vice versa.

The various embodiments described above are provided by way of illustration only and should not limit the scope of the disclosure. Those skilled in the art will readily recognize various modifications and changes that may be made to the principles described herein without following the example embodiments and applications illustrated and described herein and without departing from the spirit and scope of the present disclosure.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments provided separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Also, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the various system components described above as being separate in various embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

As described above, particular embodiments of the present subject matter have been described, but other embodiments are within the scope of the following claims. For example, the acts recited in the appended claims may be performed in a different order and still achieve desirable results. For example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.

Conclusion

Systems and methods have been shown in the above embodiments for efficiently implementing systems and methods for abstracting SATA and/or SAS storage media devices through a full duplex queued command interface to increase performance, reduce host overhead, and simplify scaling storage media devices and systems. While various preferred embodiments have been shown and described, it will be understood that there is no intent to limit the invention by such disclosure, but rather, is intended to cover all modifications falling within the spirit and scope of the invention, as defined in the appended claims. For example, the invention should not be limited by software/programming, computing environment, or specific computing hardware.

Claims

1. A routable packet-switched network supported by an abstraction protocol, comprising:

at least one host (302);

a master controller (304), the master controller (304) comprising a master processing unit (306), a master controller interface (308) in communication with the host (302), and at least one master controller control link interface (310, 312); and

at least one edge controller (316, 318), the edge controller (316, 318) comprising an edge processing unit (404), an edge controller control link interface (410, 412) in communication with the master controller (304) through the master controller control link interface (310, 312), and at least one storage media device interface (418, 420) in communication with at least one storage media device (422, 424),

wherein the master controller (304) and the edge controller (316, 318) communicate over the abstraction protocol, the abstraction protocol comprising a full-duplex protocol that supports full-duplex command queuing for the at least one storage media device (422, 424); and

wherein the edge controllers (316, 318) further comprise at least one other master controller (434), the at least one other master controller (434) further communicating with at least one other edge controller (438) when the edge processing unit (404) associated with the edge controllers (316, 318) initiates an abstraction protocol message intended for the other edge controller (438).

2. The routable packet-switched network of claim 1, wherein the abstract protocol supports both serial ATA (SATA) and Serial Attached SCSI (SAS) storage media devices simultaneously.

3. The routable packet-switched network of claim 2, wherein a single high-level command issued by said master controller (304) resolves to one or more SATA commands and one or more SAS commands.

4. The routable packet-switched network of claim 1, wherein the abstract protocol supports serial ATA (SATA).

5. The routable packet-switched network of claim 4, wherein a single high-level command issued by said master controller (304) resolves to one or more SATA commands.

6. The routable packet-switched network of claim 1, wherein the abstract protocol supports Serial Attached SCSI (SAS).

7. The routable packet-switched network of claim 6, wherein a single high-level command issued by the master controller (304) resolves to one or more SAS commands.

8. The routable packet-switched network of claim 1, wherein routing between the master controller (304) and the edge controllers (316, 318) is based on any one of: logical address, world wide number, WWN, or physical address.

9. The routable packet-switched network of claim 8, wherein routing between the master controller (304) and the edge controllers (316, 318) is based on the logical address mapped to the physical address.

10. The routable packet-switched network of claim 9, wherein the storage medium device is (a) inserted; (b) removing; (c) electrifying; or (d) upon power down, the mapping between the logical address and the physical address is dynamically updated based on a recovery process.

11. The routable packet-switched network of claim 8, wherein routing between the master controller (304) and the edge controllers (316, 318) is based on the WWN mapped to the physical address.

12. The routable packet-switched network of claim 11, wherein the storage medium device is (a) inserted; (b) removing; (c) electrifying; or (d) upon power down, the mapping between said WWN and said physical address is dynamically updated based on a recovery process.

13. The routable packet-switched network of claim 1, wherein at least one of a), b) or c):

a) the edge controllers (316, 318) further comprise at least one forwarding link interface that communicates with at least one other edge controller (438) and forwards abstract protocol packets from the master controller (304) to the other edge controller (438);

b) the master controller (304) and the at least one edge controller (316, 318) are implemented in one physical device, the physical device being any one of the following: a field programmable gate array, i.e., an FPGA, or an application specific integrated circuit, i.e., an ASIC;

c) the host controller interface (308) communicates with the host through any one of the following interfaces: a directly addressable memory interface, USB, PCIe, Ethernet, infiniband, thunderbolt, or firewall.

14. The routable packet-switched network of claim 1, wherein one of said at least one other master controller (434) is a second master controller and one of said at least one other edge controller (438) is a second edge controller, said second master controller comprising a second master processing unit, a second master controller interface in communication with said edge processing unit, and at least one second master controller control link interface in communication with a second edge controller; and

the second edge controller includes a second edge processing unit, a second edge controller control link interface that allows the second edge processing unit to communicate with the second host controller.

15. The routable packet-switched network of claim 14, wherein at least one of a), b), or c):

a) the edge controller (316, 318) further comprises a forwarding link interface in communication with the second edge controller to forward abstract protocol packets from the master controller to the second edge controller, and at least one second master controller control link interface in communication with the second edge controller;

b) a single high-level command issued by the host controller (304) is parsed into one or more SATA commands;

c) a single high-level command issued by the master controller (304) is parsed into one or more SAS commands.