CN105959089B - Network device having frequency hopping sequence for performing channel hopping using blacklist for all channel numbers - Google Patents

Abstract

The application relates to a network device with a frequency hopping sequence for channel hopping with a blacklist for all channel numbers. Disclosed examples include a method and a network device (100) for communicating in a wireless network, wherein the device (100) generates a frequency hopping sequence y (j) (114) having a prime sequence length p using a secant class in a p field or using a step and step algorithm, wherein y (0) p-1 and a residual sequence value y (j) log_α(j) modulo (p-1). In some examples, α ═ 2 and without solving the logarithm, the sequences are generated using one or more algorithms to conserve memory and reduce processing complexity of low power wireless sensors or other IEEE 802.15.4e based networks using Time Slot Channel Hopping (TSCH) communications.

Description

Network device having frequency hopping sequence for performing channel hopping using blacklist for all channel numbers

Reference to related applications

According to 35 u.s.c. § 119, the present application claims priority and benefit of us provisional patent application 62/130,194 entitled "FHS algorithm WITH blacklist in wireless NETWORKS" (FHS ALGORITHMS WITH blackkey IN WIRELESS net works), filed 3, 9, 2015, the entire content of which is incorporated herein by reference.

Reference is made to co-pending U.S. patent application No. 14/813,093 filed on 29/7/2015, entitled "technique for generating Frequency Hopping sequences" (attorney docket No. TI-75449), which claims priority to U.S. provisional application No. 62/048,692 filed on 10/9/2014, which is incorporated herein by reference in its entirety.

Technical Field

The present invention relates generally to wireless sensors and more particularly to low power wireless devices using channel hopping sequences.

Background

IEEE 802.15.4e is an IEEE 802.15.4 enhanced Medium Access Control (MAC) layer protocol designed for low power and low rate networks and adapted for sensor devices with resource constraints, such as low power consumption, low computational capacity, and/or low memory. The IEEE 802.15.4 protocol supports Time Slotted Channel Hopping (TSCH), in which a network node or device is time synchronized with a root node in the network, and individual devices communicate and synchronize in the network using time slots. During a time slot, a device hops between all channels according to a Frequency Hopping Sequence (FHS). TSCH enables higher capacity and can provide finer granularity in IEEE 802.15.4e networks to save power. Network device power consumption increases with increasing channel interference due to more frequent data packet retransmissions than if there were no interference. TSCH utilizing channel blacklisting for IEEE 802.15.4e based networks is proposed to reduce power consumption due to interference by temporarily avoiding the use of channels that are observed to be severely interfering. Since some channels are "blacklisted," blacklisting changes the number of channels (referred to as channel numbers) used in a particular time slot. IEEE 802.15.4e defines a default FHS for each channel number. The default FHS is designed to provide a small probability of interference between interfering links. In the default setting of IEEE 802.15.4e, the device regenerates a new FHS when updating the channel black list. However, the processing resources of the network device required to generate a new FHS are typically proportional to the FHS length L, and therefore, generating a long FHS is costly in terms of device processing bandwidth, power consumption, and device memory utilization. At the same time, a large FHS length L pair ensures better randomness (e.g., L511 in the default FHS) and thus reduces the probability of collisions and corresponding data packet retransmissions.

Disclosure of Invention

Disclosed examples include a network apparatus and a wireless communication method, wherein the apparatus generates a FH using a cyclotomic class (cyclotomic class) in a p-fieldS, a sequence y (j) of sequence length p, wherein p is odd prime, y (0) p-1 and the remaining sequence value y (j) log_α(j) mod (p-1), where 1 > j > p-1. In some examples, α ═ 2 and the sequence is generated using an algorithm without using logarithmic, multiplication, or modulo arithmetic to reduce processing complexity. Further disclosed network apparatus and methods generate the sequence using a baby-step algorithm (baby-step coarse-step algorithm) to further facilitate reductions in computational complexity and memory requirements.

Drawings

Fig. 1 is an illustration of an example wireless network with network equipment that includes a transceiver, memory, and one or more processors to implement wireless time-slot channel hopping communications with channel blacklisting and generate FHSs.

Figure 2 is a diagram of a first algorithm with which one example of the apparatus of figure 1 generates a sequence that is used to generate an FHS.

Fig. 3 is a diagram showing a bitwise representation of the algorithm in fig. 4, with an example sequence of length 421.

Fig. 4 is a diagram of a second algorithm with which another example of the apparatus of fig. 1 generates the sequence.

Fig. 5 is a graph of interference probability in a wireless network.

Figure 6 is a diagram of further details of the initial sequence generation and sequence lookup operations used to generate the FHS in the apparatus of figure 1.

Fig. 7 is a diagram of a third algorithm with which another example of the apparatus of fig. 1 generates the sequence.

Fig. 8 is a diagram of a fourth algorithm for selecting parameters of the third algorithm of fig. 7.

Detailed Description

In the drawings, like numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and claims, the terms "including," comprising, "" having, "" containing, "or variants thereof, are intended to be inclusive in a manner similar to the term" comprising, "and thus should be interpreted to mean" including, but not limited to. Frequency hopping sequence generation techniques and wireless network devices are described to facilitate TSCH communication between devices using blacklisting in a wireless network, although the described examples can be used in a variety of different communication applications. In particular, battery powered wireless sensor devices have limited processing power and memory, and power consumption is an issue. At the same time, energy savings are facilitated by mitigating interference between devices and associated retransmission of data packets. Frequency hopping in conjunction with a blacklist of frequency channels known or susceptible to interference facilitates reducing power consumption of network devices. However, the FHS in the individual network devices are thus updated when the good channel list is updated, and the large and/or complex FHS generation processing may exceed the processing and/or memory storage capabilities of the low power wireless sensor and will increase the device power consumption.

Fig. 1 illustrates an example TSCH network device 100 that includes a transceiver 107 operatively coupled to a wireless network via an antenna 109 to transmit data to or receive data from one or more other network devices 100 via a plurality of frequency channels. The apparatus 100 includes electronic memory 103 and one or more processors 101, 105 to implement wireless communication functions in the network and to implement frequency hopping and sequence generation 120 and to implement sequence lookup function 121 to generate an FHS. In particular, electronic memory 103 stores a sequence list 114 representing the generated sequence, and memory 103 stores a good channel list (e.g., list 602 in fig. 6 below) including entries indicating currently available frequency channels (e.g., "good channels") of the wireless network. The illustrated device 100 includes a battery 116 that provides power to the processors 101, 105 and other components in the device 100. Further, in certain examples, the device 100 can be a low power sensor that includes one or more sensors 106 and/or one or more actuators 108, although such sensors and actuators are not required for all embodiments of the presently disclosed concepts. The disclosed examples include an apparatus 100 and method for FHS generation at initial apparatus start-up and/or in response to updating a good channel list for blacklist implementation to achieve sufficient frequency hopping sequence randomness to achieve a low interference probability in network operation while mitigating or reducing processing resources and memory utilization in the network apparatus, thereby reducing power consumption.

Any suitable processor(s) can be used to implement sequence generation 120 and sequence lookup function 121 as described herein. In particular, the processor may comprise programmed or programmable circuitry and/or fixed logic circuitry or a combination thereof. In this regard, FIG. 1 shows the various functions as blocks, including items 110, 111, 120, and 121 in FIG. 1, which can be implemented by a programmed or programmable processor 101, logic circuitry, or combination thereof, alone or in combination. Further, in certain examples, memory 103 constitutes a computer-readable storage medium that stores computer-executable instructions that, when executed by processor 101, perform the various features and functions detailed herein.

The apparatus 100 in fig. 1 includes a system processor (CPU)101, which system processor 101 may include internal electronic memory to store processor-executable instructions and data. In some examples, a separate electronic memory 103 is provided. Processor 101 and electronic memory 103 are operatively coupled to each other to allow processor 101 to obtain and execute instructions stored in memory 103 and to store data to memory 103. In one example, electronic memory 103 is a non-volatile memory that stores software program instructions that may be executed by CPU 101 and/or radio processor (CPU)105 to perform some or all of the network functions described herein. In one example, the functions 110, 112, and 120, 121 are implemented by program instructions stored in the memory 103 and executed by the CPU 101 of the device 100. In the illustrated example, a radio CPU 105 is operatively coupled to the system processor 101, and the CPU 105 is configured to control the transceiver 107 to send and receive data over a network using the wireless TSCH protocol. In one example, CC26xx SimpleLink purchased from Texas instruments was used^TMThe multi-standard wireless MCU Integrated Circuit (IC) implements the apparatus 100. In this example, the apparatus 100 further includes a Real Time Clock (RTC)104, the Real Time Clock (RTC)104 generating the periodic interrupt anda periodic interrupt is provided to the processor 101. In one example, the RTC interrupt initiator wakes up, and the processor 101 implements the RTC interrupt handler and transfers control to a Power Management (PM) wake up handler 110. In one example, PM wake up handler 110 performs state transition step 111 (such as clock rotation, radio setting, etc.), after which processor 101 executes Media Access Control (MAC) software 112 to issue commands (e.g., transmit, receive, idle) and otherwise control radio CUP 105. These features facilitate low power operation of the device 100, in particular, for a low power battery powered sensor device 100, the device 100 can enter a low power "sleep" mode to conserve battery power and then can wake up as needed to perform sensing and to perform transmit or receive functions via a wireless network.

The processor 101 implements sequence generation logic 120 to begin generating the sequence list 114 in memory 103 (such as when the device 100 joins a network), and the stored sequence list 114 is thereafter used by a sequence lookup function 121 (implemented by the processor 101) to determine a channel or frequency for data transmission or reception in a given time slot via the wireless network. In some examples, the initial sequence 114 is installed in the memory 203 during production of the apparatus 100. The processor 101 also implements a sequence lookup function 121 when transmitting or receiving. For example, certain channels of the wireless network may be determined to be unsuitable for use, and the wireless communication can notify the device 100 to update its internal good channel list (e.g., good channel list 602 in fig. 6 below). In another example, a previously assumed bad channel can be determined to be now suitable for wireless communication between the devices 100, and in response the device 100 can be notified to update the good channel list 602. In some examples, the update of the good channel list will not cause the processor 101 to again implement the sequence generation function 120, and the function implemented in the sequence lookup 121 will directly change the frequency selection result by utilizing the new good channel list. In some embodiments, if, for example, memory 103 of apparatus 100 does not include sufficient capacity memory to store the entire sequence 114, only a portion of sequence 114 is stored in memory 103. In this case, the remaining sequence 114 may be dynamically (on the fly) computed to perform a sequence lookup, if desired. As used herein, storing a sequence in electronic memory 103 means storing all or at least a portion of the sequence in memory 103.

As mentioned before, the length L of a particular FHS affects the random amount in the frequency hopping operation and thus the interference probability of the final operation of the wireless network. In operation, a supervising or host node in the network can assign and Offset an value of "Offset" to each device 100 joining the wireless network, and each device 100 uses this Offset, along with other parameters, to perform a sequence lookup function 121 in a given time slot using the device processor 101 to determine or select the particular frequency channel used by the transceiver 107 in that time slot. Further, the sequence lookup function 121 uses the sequence list 114 stored in the memory 103. If the entire sequence 114 is saved, the required memory is O (L) and the initial computational complexity of the sequence generation 120 is O (L), indicating that the memory and computational resource requirements are proportional to the length of the sequence 114. In one example, processor 101 implements sequence lookup logic 121 each time device 100 needs to transmit or receive to select a channel for use by radio CPU 105 in a frequency hopping or channel hopping fashion.

Referring also to fig. 2-6, fig. 6 illustrates further details of initial or subsequent sequence generation and sequence lookup operations in the apparatus 100 of fig. 1. Fig. 2 and 4 illustrate a first algorithm 200 and a second algorithm 400, respectively, used by some examples of the processor 101 to generate a sequence using a cutcircle class in field gf (P) of FHS sequence length "P", where P is an odd prime number. Fig. 3 shows an example bitwise representation 300 of a sequence generation 400 having a sequence length of prime 421(p 421). Figure 5 provides a graph 500 of FHS sequences 114502 and 504, as well as default IEEE 802.15.4e sequences 506 and optimal FHS 508, generated for two example cutcircle classes, illustrating simulated interference probabilities in a wireless network.

As shown in fig. 6, the processor 101 implements an initial generation component 600 (including the sequence generation function 120) to provide the FHS 114 stored in the electronic memory 103 (fig. 1). Processor 101 performs a sequence lookup in a given time slot based on stored sequence 114Functions and generates an index 604 of the good channel list 602 (which is stored in memory 103 in one example). The index of the good channel list 602 provides the selected channel frequency "f" that is used by the radio CPU 105 to transmit data to and/or receive data from the wireless network via the transceiver 107 and antenna in fig. 1. At unknown Channel number Channel_N(i.e., a good or operating channel number in the wireless network), an initial sequence 114 is initially generated. Once generated, when the apparatus 100 needs to send or receive data via the network, the processor 101 implements a sequence finding function 121 to find a Channel number according to the value in the sequence 114, the current Channel number_NIndicating the current Absolute Slot Number (ASN) of the time-slotted channel hopping (TSCH) communication protocol and generating a channel index 604 based on the channel Offset (Offset) assigned to a particular device 100. In one example, processor 101 calculates channel index 604 using the following equation (1):

Index＝(Sequence[(ASN+Offset)％p])％Channel_N (1)

where "%" represents a modulo operation, and p is the sequence length of sequence 114.

In some examples, the ASN value is an integer representing the current slot number that is used for synchronization, and the Offset value is assigned to device 100(s) by a root node (not shown) of the wireless network. Indeed, in one example, the root node uses the value Offset to mitigate collisions between interfering links by assigning different Offset values to such links. Sequence finding feature 121 advantageously allows operation of low power sensor device 100 in a series of time slots by using Channel or frequency hopping in conjunction with blacklisting via good Channel list 602 without having to perform Channel number every time_NA new FHS is regenerated when changed.

A disclosed example includes an apparatus 100 that generates a sequence 114 that is capable of generating an FHS with a low interference probability according to the Lempel-Greenberger bound when a channel number satisfies a certain condition and is capable of achieving a lower interference probability performance than if there were a default FHS for all channel numbers. Furthermore, the apparatus 100 is reduced with low computational complexityThe storage requirements and reduced power consumption generate the sequence 114. Apparatus 100 generates channels having different Channel numbers using only one initially generated sequence 114_NFHS of (1). Generating each Channel separately using different sequences_NIs possible (i.e., the FHS has the best interference probability), it is difficult to generate the best FHS for different channel numbers using only 1 sequence 114. Generating each Channel using multiple sequences_NThe optimal FHS of (a) results in large overhead in both storage and computation, which is not suitable for 802.15.4 networks.

In one example of the apparatus 100, the processor 101 is configured by program instructions stored in the memory 103 to generate a sequence 114 of sequence length P (Y ═ { Y (j) }) using the cutcircle class in the field (gf (P)), where P is an odd prime number, and where 0 ≦ j < P. The processor 101 stores the sequence 114 in the memory 103 and uses the sequence 114 and one or more time slots for transmitting or receiving data via the wireless network. As described above, processor 101 channels based on the current Channel number_NThe current absolute position number (ASN), and the channel Offset value Offset assigned to the device 100, an index value 604 (fig. 6) is generated within a given time slot. Using the channel index value 604, the processor 101 determines or selects one of the currently available frequency channels indicated by the index value 604 using the good channel list 602 and the index 604. With the selected channel from the good channel list 602, the processor 101 causes the transceiver 107 to transmit data to or receive data from the wireless network in a given time slot using the selected channel. In some implementations, as shown in fig. 1, the selected channel may be provided to a radio processor (CPU)105 to interact with a transceiver 107, although a single processor may be capable of performing all of the above functions and other implementations.

In one example, processor 101 generates sequence 114Y ═ { Y (j) }, where 0 ≦ j < p, where sequence length p is an odd prime number, using the cyclotomic class in gf (p). For p ═ ef +1, indicating the secant class in e | p-1(p field GF (p), 0 ≦ i ≦ e-1) is c_i＝{α^i+teL 0 ≦ t ≦ f-1}, where α is the primitive element (primary element) of the field GF (p). In some examples, the processor 101 is configured to generate the tool using equation (2) belowSequence 114Y with sequence length p ═ { Y (j) }:

supp_Y(i)＝C_iU{0}，i＝(p-1)mod e

supp_Y(i)＝C_i，0≤i≤e-1，i≠(p-1)mod e (2)

wherein, supp_Y(i)＝{t|y(t)-i，0≤t≤p-1。

The sequence Y can be defined equally according to the following equation (3):

y(0)＝(p-1)mod e

y(j)＝log_α(j)mod e，0＜j＜p (3)

wherein y (j) -log_α(j)<- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->α^y(j)-j mod p。

For e-p-1, processor 101 generates sequence 114Y ═ { Y (j) } according to the relationship set forth in the following equation (4):

y(0)＝p-1

y(j)＝log_α(j)mod(p-1)，0＜j＜p (4)

in some examples, the above relationship of equation (4) can be at the Channel number Channel_NAn optimal/near optimal FHS can be generated when p-1 is removed. For example, using a sequence length p of 421, for a typical case of a maximum number of 16 channels, the obtained sequence 114 is for the Channel number Channel_NEqual to 2, 3, 4, 5, 6, 7, 10, 12, 14 and 15 are optimal or nearly optimal. Thus, for the vast majority of possible Channel numbers, Channel_NThe processor 101 has very good immunity to interference (e.g., low probability of interference). In addition, for the Channel in which the Channel number is_NP-1 cannot be eliminated (e.g., Channel)_N8, 9, 11, 13, or 16), the interference probability is smaller than that of the default FHS. Thus, by using the sequence 114 to generate an FHS according to the relationship in equation (4), the processor 101 advantageously provides very good interference avoidance.

In one example, processor 101 generates sequence 114Y using equation (4), using p 421 and α 2, as shown in the following equation:

y(0)＝420

y(j)＝log₂(j)mod(420)，0＜j＜421

wherein y (j) -log₂(j)<- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ->2^y(j)-j mod 421。

Fig. 2 shows one example of the apparatus of fig. 1 using a first algorithm 200 to generate a sequence, where "%" indicates a modulo operation. In this example, the processor 101 is configured to generate the sequence 114Y ═ yj using the algorithm 200 without solving for any logarithms. As indicated above, direct evaluation of the relationship in equation (4) would require instructions executed by a complex processor to evaluate the logarithm where 0 ≦ j < p. By using the algorithm 200 of fig. 2 instead, the processor 101 is not required to evaluate logarithmic operations, thus saving processing resources in the apparatus 100. Note that because the algorithm 200 of fig. 2 uses multiplication to avoid the heavy computational burden of solving logarithms, the generated numbers are not in the order of the channel indices 604, and the numbers are recorded in a particular order (as indicated in the algorithm 200) in one example.

Referring also to fig. 3 and 4, the algorithm 200 of fig. 2 requires the processor 101 to perform a multiplication operation of p to multiply α by p modulo, where p-L is the length of the sequence 114. The algorithm 400 in fig. 4 further avoids the processor 101 performing both multiplications and modulo calculations, which are generally expensive in terms of processing resources and apparatus 100. Thus, in another example, processor 101 generates sequence 114 using algorithm 400 of fig. 4. This example is similar to the algorithm 200 of fig. 2, and also avoids logarithmic operations. Further, performing algorithm 400 for α ═ 2 generates FHS 114 without any multiplicative solution and without any subtraction for specific values of p. In this regard, executing the algorithm 400 for α ═ 2 generates the sequence 114 without any solution to multiplication, where the processor 101 can instead perform a shift operation as shown in line 7 of the algorithm 400. In one example, processor 101 avoids these expensive calculations by using α ═ 2. Furthermore, since α is 2, modulo arithmetic can be avoided and the processor 101 can instead perform subtraction, which is less costly in terms of processing resources and the apparatus 100. Thus, in this example, processor 101 further facilitates power conservation in low power sensor device 100 and network device 100 while facilitating computation of an optimal/near-optimal frequency hopping sequence from sequence 114.

Fig. 3 shows a bitwise representation 300 of one example of a sequence length of 421. Because the processor 101 performs a binary or boolean operation, the multiplication of α -2 is equivalent to a simple left shift operation. Furthermore, since we only multiply by 2 and the original number in algorithm 400 is less than p, the modulo operation of p in the relationship of equation (4) above is equivalent to subtracting p if the result is greater than p, as shown in line 8 of algorithm 400 of FIG. 4. Therefore, when we choose α ═ 2, the generation of the proposed sequence 114Y is computationally efficient. Fig. 3 shows a bitwise representation of 421 and algorithm 2 shows a precise algorithm with low complexity (i.e., replacing the heavy operations with shifts and subtractions).

Figure 5 shows Channel numbers for channels from 2 to 16 in a wireless network_NThe apparatus 100 uses a graph 500 of interference probability (derived by hamming autocorrelation) of channel index values 604 generated by using equation (1) operating in a wireless network with other similar apparatuses 100. Graph 500 illustrates example cases 502 and 504 generated using algorithm 200 or algorithm 400 in fig. 2 and 4. In this example, the processor 101 generates the sequence 114 where α ═ 2 and p ═ 421 (interference probability curve 502) and where p ═ 419 (probability curve 504). For comparison, FIG. 5 further illustrates an optimal probability curve 508 and a default curve 506. As shown in the graph 500 of fig. 5, when a Channel number can be divided by p-1 (e.g., when p is 421 and Channel)_N2, 3, 4, 5, 6, 7, 10, 12, 14, or 15), the FHS generated using the sequence 114 generated by the processor 101 ensures that all good channels are evenly distributed (as indicated by the good channel list 602 (fig. 6), and the probability curves 502 and 504 obtain the best/near-best hamming autocorrelation (i.e., the best/near-best (low) interference probability). As shown in fig. 5, when Channel_NThe processor-generated FHS generated using sequence 114 has a lower probability of interference than the default FHS when p-1 can be eliminated, and when the Channel_NThe processor-generated FHS generated using sequence 114 has the best/near-best interference probability when p-1 can be eliminated. Thus, the disclosed examples provide efficient systems and methodsThe method is to generate an optimal/near optimal FHS using the sequence 114. Thus, device 100 provides the advantages of communicating using the blacklisted TSCH protocol for IEEE 802.15.4e and other similar wireless networks for device 100, where low energy consumption, and low processor resource utilization and memory requirements are important aspects.

Referring now to fig. 7 and 8, fig. 7 shows a third algorithm 700, which third algorithm 700 can be used to generate the FHS 114 in another example of the apparatus 100 of fig. 1, and fig. 8 shows a fourth algorithm 800, which fourth algorithm 800 can be used to select parameters to implement the algorithm 700 of fig. 7. In the above examples, in some examples, processor 101 is able to use algorithm 200 of fig. 2 or algorithm 400 of fig. 4 to generate an optimal/near optimal FHS using sequence 114 with an initial generation complexity of o (L) and a required memory of o (L), where L is the length of sequence 114 (L ═ p). The computational complexity is due to the loops in 200 and 400 of the algorithm, so the memory 103 in these examples needs sufficient capacity to store the entire sequence 114.

For applications with memory limitations in the device 100, the algorithm 700 provides improved memory efficiency compared to the algorithms 200 and 400 described above. In this example, processor 101 generates sequence 114 using an example step-and-step algorithm 700 with a complexity of O (√ p) and a memory requirement of O (√ p). In these respects, the step-and-step algorithm provides an improvement in computational resource utilization and memory requirements over the examples in fig. 2 and 4 described above.

In this regard, the step-and-step algorithm 700 is used to solve the discrete logarithm problem as part of the sequence generation by the processor 101. As shown in equation (4) above, the operands j and y (j) are discrete values, and thus the solution to the logarithm and the relationship of equation (4) involve a discrete logarithm problem: given a β representation sequence index 604, the processor 101 finds x (representing sequence element y (j)) such that: alpha is alpha^xβ (mod p), where p is a prime number and α field gf (p) is the primitive element. In the above example, p is 421 and α is 2, and the processor 101 implements the algorithm 700 using a hash table in the memory 103. Further, in one example, the variable "m" is a positive integer less than or equal to the square root of p. In some examples, m is approximately equal to the square root of p. In this case, the memory complexity of algorithm 700 is O (m) and the computational complexity is O (n). Algorithm 700 also sets an upper limit (ceiling) on the value of m, for example to √ p using the variable "n" in row 4 of algorithm 700. In this implementation, memory and computational complexity is typically of the order O (√ p), and therefore represents a significant improvement over algorithms 200 and 400 described above.

However, as shown in fig. 7, the algorithm 700 involves both multiplication and modulo operations, which are generally expensive in terms of processing resource utilization by the apparatus 100. Specifically, the calculation of line 14 in algorithm 700 (t ═ t · α)^-m(mod p)) includes both multiplication and modulo operation. In some examples, using α -2, the processor 101 is configured to generate the sequence 114 using an algorithm 700 that uses a shift operation to calculate t α^-m. Further, in some examples, using an upper limit value "n" similar to the value of the square root of p (e.g., where m is less than or equal to the square root of p), processor 101 is configured to generate sequence 114 using a subtraction operation via algorithm 700 to compute m mod p. For example, using p 421, α 2, m has an upper limit of vp 21, α^-m329 and the calculation of row 14 becomes t 329(mod 421). Multiplication 329 creates a large number, which makes the modulo 421 calculation expensive in terms of processing resource utilization, and this calculation is repeated n times.

The disclosed example avoids such expensive calculations by selecting appropriate values for α and m. For example, α is selected to be 2²³261(mod 421), m 23, α ^-m2, which causes line 14 of algorithm 700 to: t ═ α^-mThe calculation of (mod p) is very simple. The new calculation of line 14 becomes t ═ t × 2(mod 421), which can be implemented by processor 101 using shift and subtraction operations without requiring multiplication or modulo calculation.

When 2 is the primitive element of field gf (p), the algorithm 800 of fig. 8 can be used to generate or calculate suitable values for α and m. In certain implementations, α is the primitive element of gf (p) and m is preferably approximately equal to vp. Since (p-1, m) is 1(p and m are prime numbers to each other), there is an integer pair (i, k) such that (p-1) × i-kM-1 and (k, p-1) -1 (k and (p-1) are reciprocal prime numbers). Since (k, p-1) ═ 1 and α ═ 2 are the primitive elements of gf (p), α ═ 2^k(mod p) is the primitive element of GF (p). Thus, the algorithm 800 can be used, for example, to determine the values of m and α to store in the electronic memory 103 and later used by the processor 101 to solve the algorithm 700. In some examples, the algorithm 800 can be implemented by the device processor 101. In other examples, the algorithm 800 can be implemented during production of the device 100, where the final values of m and α can be saved in the electronic memory 103.

It is further noted that the hash function of the hash table used in algorithm 700 may need to perform a modulo calculation or calculus. In some examples, the hash function is designed to avoid complex computations such as division or modulo arithmetic, for example, by implementing "divide by 2 power" and "modulo 2 power" using shifts and bitwise additions instead. In one possible example, a hash table of size m-23 can be used. The minimum number is 2⁵The minimum number is a power of 2 and is greater than m 23. In this example, the algorithm 700 performs a "divide by 32" which can be implemented by a 5-bit shift operation. Further, the computation of "modulo 32" can be implemented using a bitwise addition operation with hexadecimal 0x001f to create a hash function and generate a hash table of 28 size.

The disclosed example step-and-step algorithm 700 is for a Channel number Channel_NUsing the overall value of sequence 114, facilitates generation of an optimal/near-optimal FHS with a complexity of O (√ p) and a memory requirement of O (√ p), algorithm 700 has significant advantages over algorithms 200, 400 having a memory requirement of O (p). The disclosed examples provide an efficient method implemented by the processor 101 in the network device 100 to generate an optimal/near optimal FHS using the sequence 114 and provide an attractive low power consumption solution for battery powered sensors or other network devices 100 to enable IEEE 802.15.4e networks and the like operating in an environment where interference is present to communicate via the TSCH protocol utilizing blacklisting.

The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. Modifications of the described embodiments, as well as other embodiments, are possible within the scope of the claimed invention.

Claims (19)

1. A network device, the network device comprising:

a transceiver operatively coupled with a wireless network to transmit data to or receive data from another network device via a plurality of frequency channels of the wireless network;

an electronic memory storing a good channel list comprising entries indicating currently available frequency channels of the wireless network; and

a processor to:

generating a sequence Y ═ { Y (j) }, using cyclotomic classes in the domain, the sequence having a sequence length p, where p is an odd prime number, and where 0 ≦ j < p,

storing said sequence in said electronic memory,

the index value is generated from:

the number of the current channel is set to,

a current absolute position number indicating a current time slot of a time slot channel hopping communication protocol, TSCH, communication protocol, and

a channel offset value assigned to the network device, an

Determining a selected one of the currently available frequency channels indicated by the index value using the index value and the good channel list, and

causing the transceiver to transmit data to or receive data from the wireless network using the selected one of the currently available frequency channels in a given time slot;

wherein the processor is configured to generate the sequence Y ═ { Y (j) } according to the following relationship:

y (0) ═ p-1, and

y(j)＝log_α(j)mod(p-1)；

wherein 0< j < p; and is

Where α is the primitive element of the domain of length p of the sequence.

2. The network device of claim 1, wherein the processor is configured to generate the sequence Y ═ { Y (j) }usingan algorithm without solving for any logarithms.

3. The network device of claim 2, wherein α ═ 2; and wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the algorithm without any multiplicative solution.

4. A network apparatus according to claim 3, wherein the processor is configured to generate the sequence Y ═ { Y (j) }, using the algorithm, without performing any modulo operation.

5. The network device according to claim 4, wherein,

wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the following algorithm:

6. the network device of claim 1, wherein the processor is configured to generate the sequence Y ═ { Y (j) } using an algorithm without performing any modulo operation.

7. The network device of claim 1, wherein the processor is configured to generate the sequence Y ═ { Y (j) }usingan algorithm without solving for any logarithms.

8. The network device of claim 7, wherein α ═ 2; and wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the algorithm without any multiplicative solution.

9. The network device of claim 7, wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the algorithm without performing any modulo operation.

10. The network device according to claim 1, wherein,

wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the following algorithm:

11. the network device of claim 1, wherein the processor is configured to generate the Index value Index according to the following formula:

Index＝(Sequence[(ASN+Offset)％p])％Channel_N(ii) a And is

Wherein Sequence [ 2 ]]Representing the corresponding values in said sequence, ASN being said current absolute position number, Offset being said Channel Offset value, Channel_NIs the current channel number and% is the modulo operation.

12. A method of communicating in a wireless network, the method comprising:

in a network device, generating a sequence Y ═ { Y (j) }, using a cyclotomic class in the domain, the sequence having a sequence length p, wherein p is an odd prime number, and wherein 0 ≦ j < p;

in the network device, an index value is generated according to:

the number of the current channel is set to,

a current absolute position number indicating a current time slot of a time slot channel hopping communication protocol, TSCH, communication protocol, and

a channel offset value assigned to the network device;

determining, in the network device, a selected one of a plurality of currently available frequency channels indicated by the index value using the index value and a good channel list; and

transmitting data between the network device and a wireless network using the selected available frequency channel within a given time slot;

wherein the sequence Y ═ { Y (j) } is generated according to the following relationship:

y (0) ═ p-1, and

y(j)＝log_α(j)mod(p-1)；

wherein 0< j < p; and is

Where α is the primitive element of the domain of length p of the sequence.

13. A network device, the network device comprising:

a transceiver operatively coupled with a wireless network to transmit data to or receive data from another network device via a plurality of frequency channels of the wireless network;

an electronic memory storing a good channel list comprising entries indicating currently available frequency channels of the wireless network; and

a processor to:

generating a sequence Y ═ Y (j) with a sequence length p using a step-and-step algorithm according to the following relationship:

y (0) ═ p-1, and

y(j)＝log_α(j)mod(p-1)，

wherein the sequence length p is a prime number, wherein 0< j < p, and wherein a is a primitive element of a domain of the sequence length p,

storing said sequence in said electronic memory,

the index value is generated from:

the number of the current channel is set to,

a current absolute position number indicating a current time slot of a time slot channel hopping communication protocol, TSCH, communication protocol, and

a channel offset value assigned to the network device, an

Determining a selected one of the currently available frequency channels indicated by the index value using the index value and the good channel list, and

causing the transceiver to transmit data to or receive data from the wireless network using the selected one of the currently available frequency channels in a given time slot.

14. The network device according to claim 13,

wherein the processor is configured to generate the sequence Y ═ { Y (j) } using a hash table stored in the electronic memory and using the following algorithm:

wherein m is a positive integer.

15. The network device of claim 14, wherein α ═ 2; and wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the algorithm, wherein t ═ α is calculated using a shift operation^-m。

16. The network device of claim 15, wherein n is less than or equal to the square root of p; wherein m is less than or equal to the square root of p; and wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the algorithm, wherein m (mod p) is calculated using a subtraction operation.

17. The network device of claim 14, wherein n is less than or equal to the square root of p; wherein m is less than or equal to the square root of p; and wherein the processor is configured to generate the sequence Y ═ { Y (j) } using the algorithm, wherein m (mod p) is calculated using a subtraction operation.

18. The network device of claim 14, wherein m is approximately equal to the square root of p.

19. A method of communicating in a wireless network, the method comprising:

in the network apparatus, a sequence Y having a sequence length p is generated using a small-step and large-step algorithm according to the following relationship { Y (j) }:

y (0) ═ p-1, and

y(j)＝log_α(j)mod(p-1)，

wherein the sequence length p is a prime number, wherein 0< j < p, and wherein α is a primitive element of the domain of the sequence length p;

in the network device, an index value is generated according to:

the number of the current channel is set to,

a current absolute position number indicating a current time slot of a time slot channel hopping communication protocol, TSCH, communication protocol, and

a channel offset value assigned to the network device;

determining, in the network device, a selected one of a plurality of currently available frequency channels indicated by the index value using the index value and a good channel list; and

data is transmitted between the network device and a wireless network using the selected available frequency channel in a given time slot.

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