CN105957870A - Array substrate, display apparatus and preparation method for array substrate - Google Patents
Array substrate, display apparatus and preparation method for array substrate Download PDFInfo
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- CN105957870A CN105957870A CN201610497367.8A CN201610497367A CN105957870A CN 105957870 A CN105957870 A CN 105957870A CN 201610497367 A CN201610497367 A CN 201610497367A CN 105957870 A CN105957870 A CN 105957870A
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- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000011241 protective layer Substances 0.000 claims description 100
- 230000000994 depressogenic effect Effects 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 25
- 238000000059 patterning Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 9
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 9
- 230000002159 abnormal effect Effects 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 description 8
- 230000006872 improvement Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate, a display apparatus and a preparation method for the array substrate. The array substrate comprises a substrate, a first signal line formed on the substrate, a first protection layer formed on the substrate and the first signal line, a second signal line which is formed in the position, corresponding to the first signal line, of the first protection layer, and a second protection layer formed on the first protection layer and the second signal line. By enabling the thickness of a signal line region which is arranged, corresponding to the first signal line, on the first protection layer to be less than that of a non-signal-line region, the height difference of the second protection layer is lowered; the angle of gradient, on the edge of the second signal line, of the second protection layer is reduced; the problem of light leak caused by abnormal liquid crystal orientation at the position is solved; and consequently, the problem of bad display uniformity can be solved, and the display effect can be improved.
Description
Technical field
The present invention relates to Display Technique field, be specifically related to a kind of array base palte, display device and array base palte preparation side
Method.
Background technology
In cell touch (touch control manner being embedded in liquid crystal pixel by touch panel function) product is light with it at present
The effective advantage of thinning, touch-control is increasingly becoming the main flow in display field, enjoys the favor of consumer.
As it is shown in figure 1, existing In cell touch array base palte 10 includes: substrate the 1, first holding wire 3, first is protected
Sheath 41, secondary signal line 5 and the second protective layer 42, the first holding wire 3 is formed on the base 1, and the first protective layer 41 is formed at
In substrate 1 and the first holding wire 3, secondary signal line 5 is formed at the position that the first protective layer 41 is corresponding with the first holding wire 3
On, the second protective layer 42 is formed on the first protective layer 41 and secondary signal line 5.
Owing to being affected by technology maturity, there is a series of defect, such as in In cell touch product in display
Color Mura is bad.Macro manifestations is low GTG or not put screen state lower-side angle rubescent, is viewed as by red pixel under eyepiece
Limit (i.e. by TX holding wire) is shinny.Drawbacks described above Producing reason is, the first protective layer 41 and second above the first holding wire 3
The second protective layer 42 above holding wire 5 overlaps, and causes the second protective layer 42 in angle of gradient α of secondary signal line 5 marginal position
Relatively big (usually about 68 °), thus cause the liquid crystal 7 in angle of gradient α corner to be orientated exception, thus cause light leak to occur,
Cause picture quality bad.
Summary of the invention
The present invention is directed to above-mentioned deficiency present in prior art, it is provided that a kind of array base palte, display device and array base
Plate preparation method, in order at least partly to solve the protective layer excessive display effect brought of the angle of gradient at secondary signal line marginal position
The poorest problem.
The present invention solves above-mentioned technical problem, adopt the following technical scheme that
The present invention provides a kind of array base palte, including substrate, is formed at described suprabasil first holding wire, is formed at institute
State substrate and the first protective layer on the first holding wire, to be formed at described first protective layer corresponding with described first holding wire
Secondary signal line on position and the second protective layer being formed on described first protective layer and secondary signal line, being perpendicular to
Stating on the direction of substrate, on described first protective layer, the thickness in holding wire region is less than the thickness in non-signal line region, described letter
Number line region is the region that described first holding wire is corresponding.
Preferably, the holding wire region on described first protective layer is formed with depressed part, and described secondary signal line is arranged at
In described depressed part.
Preferably, the degree of depth of described depressed part is less than or equal to the thickness of described secondary signal line.
Preferably, the degree of depth of described depressed part is equal to the half of the thickness of described second protective layer.
Preferably, described first holding wire is data wire, and described secondary signal line is touch signal line.
The present invention also provides for a kind of display floater, including aforesaid array base palte.
The present invention also provides for a kind of array base palte preparation method, and described method includes:
In substrate, the figure including the first holding wire is formed by patterning processes；
Form the first protective layer, and reduce the thickness in holding wire region on the first protective layer, so that believing on the first protective layer
The thickness in number line region is less than the thickness in non-signal line region, and described holding wire region is that the figure of described first holding wire is corresponding
Region；
Included the figure of secondary signal line in the formation of the holding wire region of described first protective layer by patterning processes；
Form the second protective layer.
Preferably, described in substrate, formed the figure including the first holding wire by patterning processes, specifically include:
Substrate deposits the first metallic film, and on described first metallic film, coats positive photoresist；
Use mask plate to be exposed, develop, etch the substrate completing above-mentioned steps, formed and include the first holding wire
Figure.
Preferably, described formation the first protective layer, and reduce the thickness in holding wire region on the first protective layer, specifically wrap
Include:
The substrate being formed with described first holding wire deposits the first protective layer；
Included the figure of depressed part in the formation of the holding wire region of described first protective layer by patterning processes.
Preferably, the described figure being included depressed part by patterning processes in the formation of the holding wire region of described first protective layer
Shape, specifically includes:
Described first protective layer coats negative photoresist；
To complete above-mentioned steps substrate use described mask plate be exposed, develop, etch, with described first signal
The corresponding position of line forms the figure including depressed part.
Preferably, the degree of depth of described depressed part is less than or equal to the thickness of described secondary signal line.
Preferably, become to include the figure of secondary signal line by patterning processes on described depressed part, specifically include:
The substrate being formed with described depressed part deposits the second metallic film, and coats on described second metallic film
Positive photoresist；
To complete above-mentioned steps substrate use described mask plate be exposed, develop, etch, with described depressed part phase
Corresponding position forms the figure including secondary signal line.
Preferably, described first metallic film is identical with the material of described second metallic film.
The present invention is capable of following beneficial effect:
The present invention is by making the thickness in holding wire region corresponding with the first holding wire on the first protective layer less than non-signal
The thickness in line region, reduces the difference in height of the second protective layer, reduces second protective layer gradient at secondary signal line marginal position
Angle, solves the abnormal leakage problem brought of liquid crystal aligning of this position such that it is able to improve show uniformity bad, improve aobvious
Show effect.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing In cell touch array base palte；
Fig. 2 is the structural representation of the array base palte of the embodiment of the present invention；
Fig. 3 is the preparation flow figure of the array base palte of the embodiment of the present invention.
Marginal data:
1, substrate 2, gate insulator the 3, first holding wire
41, first protective layer the 42, second protective layer 5, secondary signal line
411, holding wire region 412, non-signal line region 413, depressed part
10, array base palte 20, color membrane substrates 7, liquid crystal
Detailed description of the invention
Below in conjunction with the accompanying drawing in the present invention, the technical scheme in the present invention is carried out clear, complete description, aobvious
So, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on the enforcement in the present invention
Example, the every other embodiment that those of ordinary skill in the art are obtained on the premise of not making creative work, all belong to
In the scope of protection of the invention.
Below in conjunction with Fig. 2, describe the structure of the array base palte of the present invention in detail.
As Fig. 2 shows, the present invention provides a kind of array base palte 10, including: substrate the 1, first holding wire the 3, first protective layer 41,
Secondary signal line 5 and the second protective layer 42, the first holding wire 3 is formed on the base 1, and the first protective layer 41 is formed at substrate 1 He
On first holding wire 3, secondary signal line 5 is formed on the position that the first protective layer 41 is corresponding with the first holding wire 3, and second protects
Sheath 42 is formed on the first protective layer 41 and secondary signal line 5.On first protective layer 41, the thickness in holding wire region 411 is less than
The thickness in non-signal line region 412, holding wire region 411 is the region of the first holding wire 3 correspondence.Wherein, substrate 1 is glass base
Plate, the first protective layer 41 and the second protective layer 42 are passivation layer (PVX).
It should be noted that described array base palte 10 can also include that gate insulator 2, gate insulator 2 are formed at base
, the first holding wire 3 is formed on gate insulator 2 at the end 1.
The present invention is by making the thickness in holding wire region corresponding with the first holding wire on the first protective layer less than non-signal
The thickness in line region, reduces the difference in height of the second protective layer, reduces second protective layer gradient at secondary signal line marginal position
Angle, the problem solving the abnormal light leak brought of liquid crystal aligning of this position such that it is able to improve show uniformity bad, improve
Display effect.
As in figure 2 it is shown, the holding wire region 411 on the first protective layer 41 is formed with depressed part 413, secondary signal line 5 sets
It is placed in depressed part 413.
Preferably, the degree of depth of depressed part 413 is less than or equal to the thickness of secondary signal line 5.The degree of depth etc. when depressed part 413
When the thickness of secondary signal line 5, the upper surface of secondary signal line 5 and the upper surface of the first protective layer 41 are concordant, in this feelings
Under condition, the angle of gradient of the second protective layer 42 is 0 °, and display effect is optimum.When the degree of depth of depressed part 413 is less than secondary signal line 5
During thickness, the upper surface of secondary signal line 5 is higher than the upper surface of the first protective layer 41, and the second protective layer 42 is on secondary signal line limit
The angle of gradient of edge position is less than 45 °.
Preferably, the degree of depth of depressed part 413 is equal to the half of the thickness of the second protective layer 42.In this case, can be by
Second protective layer 42 reduces about 30 ° in the angle of gradient of secondary signal line marginal position, and angle of gradient α of the i.e. second protective layer 42 can
Think about 38 °, significantly reduce relative to the angle of gradient of the second protective layer of existing array base palte, thus it is rubescent to solve side-looking angle
And the problem of light leak, improve display effect.
Preferably, the first holding wire 3 can be data wire (SD), and secondary signal line 5 can be touch signal line (TPM).
In the present invention, it is also possible to the holding wire region 411 on the first protective layer 41 does not arranges depressed part 413, but
By thinning for the thickness in holding wire region 411 on the first protective layer 41, so that the thickness in holding wire region 411 on the first protective layer 41
Thickness less than non-signal line region 412.Now, still above non-signal line region 412, holding wire region 411, i.e. first
On protective layer 41, holding wire region 411 arrives base to the height between substrate 1 more than non-signal line region on the first protective layer 41 412
Height at the end 1.
Although it should be noted that can also be one by the thickness in holding wire region 411 on thinning first protective layer 41
Determine the angle of gradient reducing the second protective layer 42 in degree at secondary signal line 5 marginal position, but, due to holding wire region 411
Height remain above the height in non-signal line region 412, the offset of the second protective layer 42 is the biggest, the gradient of corresponding position
Angle reduces DeGrain, therefore, in terms of the improvement effect of the abnormal leakage problem caused of liquid crystal aligning, and changing of this scheme
Kind effect is effective not over the improvement of the technical scheme arranging depressed part.
Another embodiment of the present invention also provides for a kind of display floater, as in figure 2 it is shown, described display floater includes such as front institute
The array base palte 10 stated, further, described display floater can also include color membrane substrates 20, array base palte 10 and color membrane substrates
Liquid crystal 7 it is provided with between 20.
By making the thickness in holding wire region corresponding with the first holding wire on the first protective layer less than non-signal line region
Thickness, reduce the difference in height of the second protective layer, reduce second protective layer angle of gradient at secondary signal line marginal position, solve
The abnormal leakage problem brought of the liquid crystal aligning of this position such that it is able to improve show uniformity bad, improve display effect.
Another embodiment of the present invention also provides for a kind of array base palte preparation method, below in conjunction with Fig. 2 and Fig. 3 to array base
The preparation method of plate is described in detail.As it is shown on figure 3, said method comprising the steps of:
Step 301, forms the figure including the first holding wire in substrate by patterning processes.
Concrete, deposit the first metallic film on the base 1, and on the first metallic film, coat positive photoresist.Right
The substrate 1 completing above-mentioned steps uses mask plate to be exposed, develops, etches, and forms the figure including the first holding wire 3.
Step 302, forms the first protective layer, and reduces the thickness in holding wire region on the first protective layer, so that first protects
On sheath, the thickness in holding wire region is less than the thickness in non-signal line region.
Holding wire region 411 is the region that the figure of the first holding wire 3 is corresponding.
Preferably, the substrate 1 being formed with the first holding wire 3 deposits the first protective layer 41, and is existed by patterning processes
The holding wire region 411 of the first protective layer 41 forms the figure including depressed part 413.
Wherein, the described figure being included depressed part by patterning processes in the formation of the holding wire region of the first protective layer, tool
Body includes: coats negative photoresist on the first protective layer 41, and uses described mask plate to enter the substrate 1 completing above-mentioned steps
Row exposes, develops, etches, and forms the figure including depressed part 413 in the position corresponding with the first holding wire 3.Protect first
After coating negative photoresist on sheath 41, owing to the described mask plate used is the mask forming the first holding wire in step 301
Plate, therefore on the first protective layer 41 photoresist of non-light part (the most just part to the first holding wire 3) change by
Development, the first protective layer 41 above the first holding wire 3 is etched away, thus forms depressed part 413, in order to slot milling is formed
Secondary signal line 5.
Preferably, the degree of depth of depressed part 413 is less than or equal to the thickness of secondary signal line 3, and the degree of depth of depressed part 413 is permissible
Half equal to the thickness of the second protective layer.
It should be noted that can be by controlling etch rate and the degree of depth of etch period control depressed part 413.
It can thus be seen that in step 301, during forming the figure including the first holding wire 3 on the base 1,
On the first metallic film, coating is positive photoresist, and in this step, in the holding wire region 411 of the first protective layer 41
During formation includes the figure of depressed part 413, the first protective layer 41 coats incompatible photoresist (i.e. negativity light
Photoresist), and when using the figure making the first holding wire 3, the mask plate that used is exposed, develops, etches, thus formed
Including the figure of depressed part 413, so, not only can save mask plate, reduce production cost, it can also be ensured that depressed part 413
The first holding wire 3 accurate contraposition with lower section.
Step 303, by patterning processes, in the holding wire region of described first protective layer, formation includes secondary signal line
Figure.
Concrete, the substrate 1 be formed with depressed part 413 deposits the second metallic film, and on the second metallic film
Coating positive photoresist.Use described mask plate to be exposed, develop, etch the substrate 1 completing above-mentioned steps, with depression
Corresponding position, portion 413 forms the figure including secondary signal line 5.
Preferably, the material of the first metallic film and the second metallic film is identical.
It can thus be seen that during forming the figure including secondary signal line 5, the second metallic film coats
Positive photoresist, and use the mask plate used in step 301 and step 302 to be exposed, develop, etch, thus form bag
Include the figure of secondary signal line 5, not only can make to include the depressed part 413 of the figure of secondary signal line 5 and lower section and the first letter
Number line 3 accurate contraposition, also saves mask plate, reduces production cost further.
Step 304, forms the second protective layer.
It should be noted that before performing step 301, it is also possible to perform following steps: by patterning processes in substrate 1
Upper formation gate insulator 2, accordingly, when performing step 301, is formed on gate insulator 2 by patterning processes and includes
The figure of the first holding wire 3, i.e. deposits the first metallic film on gate insulator 2, and just coats on the first metallic film
Property photoresist.The gate insulator 2 completing above-mentioned steps is used mask plate to be exposed, develops, etches, is formed and include first
The figure of holding wire 3.
By above-mentioned steps 301-304 it can be seen that include step (the i.e. step of the figure of the first holding wire in formation
301) step (i.e. step 302) and the formation that, reduce the thickness in holding wire region on the first protective layer include secondary signal line
Figure step (i.e. step 303) in, all use identical mask plate to be patterned technique, and in step 302, by being coated with
Cover incompatible photoresist, form the figure including depressed part 413 in the holding wire region 411 of the first protective layer 41, thus
Whole prepare array base palte during use same mask plate to complete, not only can ensure that the first holding wire 3, depressed part 413
With the accurate contraposition of secondary signal line 5, and save mask plate, reduce production cost.
It should be noted that in step 302, the substrate 1 being formed with the first holding wire 3 deposits the first protective layer 41
Afterwards, it is also possible to by by thinning for the thickness of position, holding wire region 411 on the first protective layer 41, i.e. by patterning processes the
The holding wire region 411 of one protective layer 41 is formed and includes that thickness is less than the figure of non-signal line area thickness, it is achieved the first protection
On layer 41, the thickness in holding wire region 411 is less than the thickness in non-signal line region 412, thus substitutes the letter at the first protective layer 41
Number line region 411 forms the step of the figure including depressed part 413.
It is understood that the principle that is intended to be merely illustrative of the present of embodiment of above and the exemplary enforcement that uses
Mode, but the invention is not limited in this.For those skilled in the art, in the essence without departing from the present invention
In the case of god and essence, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (13)
1. an array base palte, it is characterised in that include substrate, be formed at described suprabasil first holding wire, be formed at institute
State substrate and the first protective layer on the first holding wire, be formed on described first protective layer and relative with described first holding wire
Secondary signal line on the position answered and the second protective layer being formed on described first protective layer and secondary signal line, its feature
Being, on the direction being perpendicular to described substrate, on described first protective layer, the thickness in holding wire region is less than non-signal line district
The thickness in territory, described holding wire region is the region that described first holding wire is corresponding.
2. array base palte as claimed in claim 1, it is characterised in that the holding wire region on described first protective layer is formed
Depressed part, described secondary signal line is arranged in described depressed part.
3. array base palte as claimed in claim 2, it is characterised in that the degree of depth of described depressed part is less than or equal to described second
The thickness of holding wire.
4. array base palte as claimed in claim 2, it is characterised in that the degree of depth of described depressed part is equal to described second protective layer
The half of thickness.
5. array base palte as claimed in claim 1, it is characterised in that described first holding wire is data wire, described second letter
Number line is touch signal line.
6. a display floater, it is characterised in that include the array base palte as described in any one of claim 1-5.
7. an array base palte preparation method, it is characterised in that described method includes:
In substrate, the figure including the first holding wire is formed by patterning processes；
Form the first protective layer, and reduce the thickness in holding wire region on the first protective layer, so that holding wire on the first protective layer
The thickness in region is less than the thickness in non-signal line region, and described holding wire region is the district that the figure of described first holding wire is corresponding
Territory；
Included the figure of secondary signal line in the formation of the holding wire region of described first protective layer by patterning processes；
Form the second protective layer.
8. array base palte preparation method as claimed in claim 7, it is characterised in that described by patterning processes in substrate shape
Become to include the figure of the first holding wire, specifically include:
Substrate deposits the first metallic film, and on described first metallic film, coats positive photoresist；
Use mask plate to be exposed, develop, etch the substrate completing above-mentioned steps, form the figure including the first holding wire
Shape.
9. array base palte preparation method as claimed in claim 8, it is characterised in that described formation the first protective layer, and reduce
The thickness in holding wire region on first protective layer, specifically includes:
The substrate being formed with described first holding wire deposits the first protective layer；
Included the figure of depressed part in the formation of the holding wire region of described first protective layer by patterning processes.
10. array base palte preparation method as claimed in claim 9, it is characterised in that described by patterning processes described the
The holding wire region of one protective layer forms the figure including depressed part, specifically includes:
Described first protective layer coats negative photoresist；
To complete above-mentioned steps substrate use described mask plate be exposed, develop, etch, with described first holding wire phase
Corresponding position forms the figure including depressed part.
11. array base palte preparation methoies as claimed in claim 10, it is characterised in that the degree of depth of described depressed part less than or etc.
Thickness in described secondary signal line.
12. array base palte preparation methoies as claimed in claim 10, it is characterised in that by patterning processes at described depressed part
Upper one-tenth includes the figure of secondary signal line, specifically includes:
The substrate being formed with described depressed part deposits the second metallic film, and on described second metallic film, coats positivity
Photoresist；
Described mask plate is used to be exposed, develop, etch, corresponding with described depressed part the substrate completing above-mentioned steps
Position formed and include the figure of secondary signal line.
13. array base palte preparation methoies as claimed in claim 12, it is characterised in that described first metallic film and described the
The material of two metallic films is identical.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610497367.8A CN105957870A (en) | 2016-06-29 | 2016-06-29 | Array substrate, display apparatus and preparation method for array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610497367.8A CN105957870A (en) | 2016-06-29 | 2016-06-29 | Array substrate, display apparatus and preparation method for array substrate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113126370A (en) * | 2021-04-23 | 2021-07-16 | 成都天马微电子有限公司 | Transmission line structure and manufacturing method thereof, phase shifter and liquid crystal antenna |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102375277A (en) * | 2010-08-10 | 2012-03-14 | 乐金显示有限公司 | Liquid crystal display device and method of manufacturing the same |
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