CN105957487B - A kind of GOA circuits - Google Patents
A kind of GOA circuits Download PDFInfo
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- CN105957487B CN105957487B CN201610538312.7A CN201610538312A CN105957487B CN 105957487 B CN105957487 B CN 105957487B CN 201610538312 A CN201610538312 A CN 201610538312A CN 105957487 B CN105957487 B CN 105957487B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The present invention provides a kind of GOA circuits and liquid crystal display panel, including pull-up control module, pull-up module, lower transmission module, drop-down module, drop-down maintenance module, bootstrap capacitor and Voltage stabilizing module；The GOA circuits of the present invention are by setting a Voltage stabilizing module, one end of the output terminal of Voltage stabilizing module and bootstrap capacitor is connected, the voltage regulation signal of the output terminal output of Voltage stabilizing module is consistent with the scanning signal of this grade, current potential is promoted using the voltage regulation signal of Voltage stabilizing module output, play the effect as existing GOA circuits, and the parasitic capacitance on scanning signal output terminal is reduced, so as to improve the display quality of liquid crystal display panel.
Description
Technical field
The present invention relates to technical field of liquid crystal display more particularly to a kind of GOA circuits.
Background technology
Gate Driver On Array, abbreviation GOA, the i.e. array substrate in existing liquid crystal display panel of thin film transistor
Upper making scan drive circuit realizes the type of drive to scan line progressive scan.The structure diagram of existing GOA circuits is such as
Shown in Fig. 1, which includes pull-up control module 101, pull-up module 104, lower transmission module 105, drop-down module 106, bootstrapping
Capacitance 103 and drop-down maintenance module 102.
One end of bootstrap capacitor 103 is electrically electrically connected at the output terminal of pull-up control module 101, bootstrap capacitor 103
The other end is electrically connected at the output terminal of the scanning signal of this grade.When exporting the scanning signal of this grade, bootstrap capacitor 103 plays
The effect of lifting current potential, but on the other hand, due to output terminal of the one end directly with the scanning signal of this grade of bootstrap capacitor 103
Connection so that bootstrap capacitor 103 becomes a parasitic capacitance on the scanning signal output terminal of this grade, so easily causes liquid crystal
Pixel undercharge in display panel, so as to reduce the display quality of liquid crystal display panel.
Therefore, it is necessary to a kind of GOA circuits are provided, it is existing in the prior art to solve the problems, such as.
The content of the invention
It is straight to solve one end of existing GOA circuit becauses bootstrap capacitor it is an object of the invention to provide a kind of GOA circuits
It connects and is connected with the output terminal of the scanning signal of this grade, in turn result in liquid crystal display panel pixel undercharge, reduce liquid crystal display
The technical issues of display quality of panel.
To solve the above problems, technical solution provided by the invention is as follows：
The embodiment of the present invention provides a kind of GOA circuits, including：
Control module is pulled up, for being generated the scanning level signal of this grade by the control of the grade communication number of upper level；
Module is pulled up, the scanning letter of this grade is drawn high for the scanning level signal according to this grade and the clock signal of this grade
Number；
Lower transmission module generates the grade communication of this grade for the scanning level signal according to this grade and the clock signal of this grade
Number；
Module is pulled down, for the grade communication number according to next stage, drags down the scanning level signal of this grade；
Maintenance module is pulled down, for maintaining the low level of the scanning level signal of this grade；
Bootstrap capacitor, for generating the high level of the scanning signal of this grade；And
Voltage stabilizing module, for exporting the voltage regulation signal consistent with the scanning signal of this grade；Wherein, control module difference is pulled up
It is connected with pull-up module, lower transmission module, drop-down module, drop-down maintenance module, the output terminal of Voltage stabilizing module and the one of bootstrap capacitor
End connection, the other end of bootstrap capacitor are electrically connected at the output terminal of pull-up control module.
In the GOA circuits of the present invention, pull-up control module includes first film transistor, the grid of first film transistor
The grade communication number of upper level is accessed in pole, and the source electrode of first film transistor is electrically connected at constant pressure high level source, and the first film is brilliant
The drain electrode of body pipe is electrically connected at the output terminal of pull-up control module.
In the GOA circuits of the present invention, pull-up module includes the 6th thin film transistor (TFT), the grid electricity of the 6th thin film transistor (TFT)
Property be connected to the output terminal of pull-up control module, the source electrode of the 6th thin film transistor (TFT) accesses the clock signal of this grade, the 6th film
The drain electrode of transistor is electrically connected at the output terminal of the scanning signal of this grade.
In the GOA circuits of the present invention, lower transmission module includes the 5th thin film transistor (TFT), the grid electricity of the 5th thin film transistor (TFT)
Property be connected to the output terminal of pull-up control module, the source electrode of the 5th thin film transistor (TFT) accesses the clock signal of this grade, the 5th film
The drain electrode of transistor is electrically connected at the output terminal of the grade communication number of this grade.
In the GOA circuits of the present invention, drop-down module includes the 7th thin film transistor (TFT) and the 8th thin film transistor (TFT)；
The grade communication number of the grid access next stage of 7th thin film transistor (TFT), the source electrode of the 7th thin film transistor (TFT) are electrically connected
In constant pressure low level source, the drain electrode of the 7th thin film transistor (TFT) is electrically connected at the output terminal of pull-up control module；
The grade communication number of the grid access next stage of 8th thin film transistor (TFT), the source electrode of the 8th thin film transistor (TFT) are electrically connected
In constant pressure low level source, tell that the drain electrode of the 8th thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of this grade.
In the GOA circuits of the present invention, drop-down maintenance module includes the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the
11 thin film transistor (TFT)s, the 12nd thin film transistor (TFT), the 13rd thin film transistor (TFT) and the 14th thin film transistor (TFT)；
The grid and source electrode of 9th thin film transistor (TFT) access the clock signal of this grade, and the drain electrode of the 9th thin film transistor (TFT) is electrical
It is connected to the drain electrode of the grid and the tenth thin film transistor (TFT) of the 11st thin film transistor (TFT)；
The grid of tenth thin film transistor (TFT) is electrically connected at the output terminal of pull-up control module, the tenth thin film transistor (TFT) source electrode
It is electrically connected at constant pressure low level source；
The source electrode of 11st thin film transistor (TFT) accesses the clock signal of this grade, and the drain electrode of the 11st thin film transistor (TFT) electrically connects
Be connected to the grid of the 13rd thin film transistor (TFT), the 14th thin film transistor (TFT) grid and the 12nd thin film transistor (TFT) drain electrode；
The grid of 12nd thin film transistor (TFT) is electrically connected at the output terminal of pull-up control module, the 12nd thin film transistor (TFT)
Source electrode access constant pressure low level source；
The source electrode of 13rd thin film transistor (TFT) is electrically connected at constant pressure low level source, the drain electrode electricity of the 13rd thin film transistor (TFT)
Property be connected to pull-up control module output terminal；
The source electrode of 14th thin film transistor (TFT) is electrically connected at constant pressure low level source, the drain electrode electricity of the 14th thin film transistor (TFT)
Property is connected to the output terminal of the scanning signal of this grade.
In the GOA circuits of the present invention, Voltage stabilizing module includes the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin
Film transistor and the 5th thin film transistor (TFT)；
The grid and source electrode of second thin film transistor (TFT) are electrically connected at constant pressure high level source, the drain electrode of the second thin film transistor (TFT)
It is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) of the 4th thin film transistor (TFT)；
The grid of 3rd thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of this grade, the 3rd thin film transistor (TFT)
Source electrode is electrically connected at constant pressure high level source, and the drain electrode of the 3rd thin film transistor (TFT) is electrically connected at the output terminal of Voltage stabilizing module；
The source electrode of 4th thin film transistor (TFT) is electrically connected at constant pressure low level source, and the drain electrode of the 4th thin film transistor (TFT) electrically connects
It is connected to the output terminal of Voltage stabilizing module；
The source electrode of 17th thin film transistor (TFT) is electrically connected at constant pressure low level source, the grid of the 17th thin film transistor (TFT)
It is electrically connected at the output terminal of the scanning signal of this grade.
In the GOA circuits of the present invention, Voltage stabilizing module includes the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin
Film transistor and the 5th thin film transistor (TFT)；
The grid and source electrode of second thin film transistor (TFT) are electrically connected at constant pressure high level source, the drain electrode of the second thin film transistor (TFT)
It is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) of the 4th thin film transistor (TFT)；
The grid of 3rd thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of this grade, the 3rd thin film transistor (TFT)
Source electrode is electrically connected at constant pressure high level source, and the drain electrode of the 3rd thin film transistor (TFT) is electrically connected at the output terminal of Voltage stabilizing module；
The source electrode of 4th thin film transistor (TFT) is electrically connected at constant pressure low level source, and the drain electrode of the 4th thin film transistor (TFT) electrically connects
It is connected to the output terminal of Voltage stabilizing module；
The source electrode of 17th thin film transistor (TFT) is electrically connected at constant pressure low level source, the grid of the 17th thin film transistor (TFT)
It is electrically connected at the output terminal of the grade communication number of this grade.
In the GOA circuits of the present invention, Voltage stabilizing module includes the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin
Film transistor and the 5th thin film transistor (TFT)；
The grid and source electrode of second thin film transistor (TFT) are electrically connected at constant pressure high level source, the drain electrode of the second thin film transistor (TFT)
It is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) of the 4th thin film transistor (TFT)；
The grid of 3rd thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of this grade, the 3rd thin film transistor (TFT)
Source electrode is electrically connected at constant pressure high level source, and the drain electrode of the 3rd thin film transistor (TFT) is electrically connected at the output terminal of Voltage stabilizing module；
The source electrode of 4th thin film transistor (TFT) is electrically connected at constant pressure low level source, and the drain electrode of the 4th thin film transistor (TFT) electrically connects
It is connected to the output terminal of Voltage stabilizing module；
The source electrode of 17th thin film transistor (TFT) is electrically connected at constant pressure low level source, the grid of the 17th thin film transistor (TFT)
Access the clock signal of this grade.
In the GOA circuits of the present invention, the 15th thin film transistor (TFT) and the 16th thin film transistor (TFT) are further included；
The grid access second clock signal of 15th thin film transistor (TFT), the source electrode access upper one of the 15th thin film transistor (TFT)
The grade communication number of grade, the drain electrode of the 15th thin film transistor (TFT) are electrically connected at the output terminal of pull-up control module；
The grid access second clock signal of 16th thin film transistor (TFT), the source electrode of the 16th thin film transistor (TFT) are electrically connected
In constant pressure low level source, the drain electrode of the 16th thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of this grade；Wherein,
The phase of second clock signal is opposite with the clock signal phase of this grade.
Compared to existing GOA circuits, GOA circuits of the invention are by setting a Voltage stabilizing module, by the defeated of Voltage stabilizing module
One end of outlet and bootstrap capacitor connects, and the voltage regulation signal of the output terminal output of Voltage stabilizing module is consistent with the scanning signal of this grade,
Current potential is promoted using the voltage regulation signal of Voltage stabilizing module output, the effect as existing GOA circuits is played, and reduces scanning
Parasitic capacitance on signal output part, so as to improve the display quality of liquid crystal display panel.
The above to allow the present invention can be clearer and more comprehensible, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be made
Detailed description are as follows：
Description of the drawings
Below in conjunction with the accompanying drawings, it is described in detail by the specific embodiment to the present invention, technical scheme will be made
And other beneficial effects are apparent.
Fig. 1 is a kind of structure diagram of existing GOA circuits；
Fig. 2 is the structure diagram of the first preferred embodiment of the GOA circuits of the present invention；
Fig. 3 is the structure diagram of the second preferred embodiment of the GOA circuits of the present invention；
Fig. 4 is the structure diagram of the third preferred embodiment of the GOA circuits of the present invention；
Fig. 5 is the signal waveforms of the GOA circuits of the present invention.
Specific embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferably implemented for the present invention
Example and its attached drawing are described in detail.
Referring to Fig. 2, for the structure diagram of the first preferred embodiment of the GOA circuits of the present invention；
The GOA circuits of this preferred embodiment include pull-up control module 201, pull-up module 206, lower transmission module 203, drop-down
Module 205, drop-down maintenance module 202, bootstrap capacitor Cbt and Voltage stabilizing module 204.Control module 201 is pulled up, for by upper one
The control of the grade communication ST (n-1) of grade generates the scanning level signal of this grade；Module 206 is pulled up, for sweeping according to this grade
The clock signal CK (n) for retouching level signal and this grade draws high the scanning signal of this grade；Lower transmission module 203, for according to this grade
Scanning level signal and the clock signal CK (n) of this grade generate the grade communication ST (n) of this grade；Module 205 is pulled down, is used for
According to the grade communication ST (n+1) of next stage, the scanning level signal of this grade is dragged down；Maintenance module 202 is pulled down, for maintaining this
The low level of the scanning level signal of grade；Bootstrap capacitor Cbt is used to generate the high level of the scanning signal of this grade；And voltage stabilizing mould
Block, for exporting the voltage regulation signal consistent with the scanning signal G (n) of this grade；
Wherein, control module 201 is pulled up to tie up with pull-up module 206, lower transmission module 203, drop-down module 205, drop-down respectively
It holds module 202 to connect, the output terminal of Voltage stabilizing module 204 is connected with one end of bootstrap capacitor Cbt, the other end of bootstrap capacitor Cbt
It is electrically connected at the output terminal of pull-up control module 201.
Pulling up control module 201 includes first film transistor T1, the grid access upper level of first film transistor T1
Grade communication ST (n-1), the source electrode of first film transistor T1 is electrically connected at constant pressure high level source VDD, and the first film is brilliant
The drain electrode of body pipe T1 is electrically connected at the output terminal of pull-up control module 201.
Pulling up module 206 includes the 6th thin film transistor (TFT) T6, and the grid of the 6th thin film transistor (TFT) T6 is electrically connected at pull-up
The output terminal of control module 201, the source electrode of the 6th thin film transistor (TFT) T6 access the clock signal CK (n) of this grade, and the 6th film is brilliant
The drain electrode of body pipe T6 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
Lower transmission module 203 includes the 5th thin film transistor (TFT) T5, and the grid of the 5th thin film transistor (TFT) T5 is electrically connected at pull-up
The output terminal of control module 201, the source electrode of the 5th thin film transistor (TFT) T5 access the clock signal CK (n) of this grade, and the 5th film is brilliant
The drain electrode of body pipe T5 is electrically connected at the output terminal of the grade communication ST (n) of this grade.
Pulling down module includes the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8；
The grade communication ST (n+1) of the grid access next stage of 7th thin film transistor (TFT) T7, the 7th thin film transistor (TFT) T7's
Source electrode is electrically connected at constant pressure low level source Vss, the 7th thin film transistor (TFT) T7 drain electrode and is electrically connected at pull-up control module 201
Output terminal；
The grade communication ST (n+1) of the grid access next stage of 8th thin film transistor (TFT) T8, the 8th thin film transistor (TFT) T8's
Source electrode is electrically connected at constant pressure low level source Vss, and the drain electrode of the 8th thin film transistor (TFT) T8 is electrically connected at the scanning signal G of this grade
(n) output terminal.
Pulling down maintenance module 202 includes the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11st film crystal
Pipe T11, the 12nd thin film transistor (TFT) T12, the 13rd thin film transistor (TFT) T13 and the 14th thin film transistor (TFT) T14；
The grid and source electrode of 9th thin film transistor (TFT) T9 access the clock signal CK (n) of this grade, the 9th thin film transistor (TFT) T9
Drain electrode be electrically connected at the 11st thin film transistor (TFT) T11 grid and the tenth thin film transistor (TFT) T10 drain electrode；
The grid of tenth thin film transistor (TFT) T10 is electrically connected at the output terminal of pull-up control module 201, the tenth film crystal
Pipe T10 source electrodes are electrically connected at constant pressure low level source Vss；
The source electrode of 11st thin film transistor (TFT) T11 accesses the clock signal of this grade, the drain electrode of the 11st thin film transistor (TFT) T11
It is brilliant to be electrically connected at the grid of the 13rd thin film transistor (TFT) T13, the grid of the 14th thin film transistor (TFT) T14 and the 12nd film
The drain electrode of body pipe T12；
The grid of 12nd thin film transistor (TFT) T12 is electrically connected at the output terminal of pull-up control module 201, the 12nd film
The source electrode access constant pressure low level source Vss of transistor T12；
The source electrode of 13rd thin film transistor (TFT) T13 is electrically connected at constant pressure low level source Vss, the 13rd thin film transistor (TFT)
The drain electrode of T13 is electrically connected at the output terminal of pull-up control module 201；
The source electrode of 14th thin film transistor (TFT) T14 is electrically connected at constant pressure low level source Vss, the 14th thin film transistor (TFT)
The drain electrode of T14 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
Voltage stabilizing module includes the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 and the
17 thin film transistor (TFT) T17；
The grid and source electrode of second thin film transistor (TFT) T2 is electrically connected at constant pressure high level source VDD, the second thin film transistor (TFT)
The drain electrode of T2 is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) T17 of the 4th thin film transistor (TFT) T4；
The grid of 3rd thin film transistor (TFT) T3 is electrically connected at the output terminal of the scanning signal G (n) of this grade, and the 3rd film is brilliant
The source electrode of body pipe T3 is electrically connected at constant pressure high level source VDD, and the drain electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at voltage stabilizing mould
The output terminal of block 204；
The source electrode of 4th thin film transistor (TFT) T4 is electrically connected at constant pressure low level source Vss, the leakage of the 4th thin film transistor (TFT) T4
Pole is electrically connected at the output terminal of Voltage stabilizing module 204；
The source electrode of 17th thin film transistor (TFT) T17 is electrically connected at constant pressure low level source Vss, the 17th thin film transistor (TFT)
The grid of T17 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
The GOA circuits of this preferred embodiment further include the 15th thin film transistor (TFT) T15 and the 16th thin film transistor (TFT) T16；
The grid access second clock signal XCK (n) of 15th thin film transistor (TFT) T15, the 15th thin film transistor (TFT) T15's
Source electrode accesses the grade communication ST (n-1) of upper level, and the drain electrode of the 15th thin film transistor (TFT) T15 is electrically connected at pull-up control mould
The output terminal of block 201；
The grid access second clock signal XCK (n) of 16th thin film transistor (TFT) T16, the 16th thin film transistor (TFT) T16's
Source electrode be electrically connected at constant pressure low level source Vss, the 16th thin film transistor (TFT) T16 drain electrode be electrically connected at this grade scanning letter
The output terminal of number G (n)；Wherein,
The phase of second clock signal XCK (n) and clock signal CK (n) opposite in phase of this grade.
Referring to Fig. 5, for the signal waveforms of the GOA circuits of the present invention；
Referring to Fig. 2, Fig. 5, the GOA circuits of this preferred embodiment are in use, when the grade communication ST (n-1) of upper level is height
During level, first film transistor T1 conductings, the constant pressure high level that constant pressure high level source provides passes through first film transistor T1
It charges to bootstrap capacitor Cbt so that the first reference point Q (n) rises to a higher level.
The grade communication ST (n-1) of subsequent upper level switchs to low level, and first film transistor T1 is closed, the first reference point
Q (n) maintains a higher level by bootstrap capacitor Cbt.Meanwhile the clock signal CK (n) of this grade switchs to high level, this grade
Scanning signal G (n) and grade communication ST (n) also switch to high level.When the scanning signal G (n) of this grade is high level, the 3rd is thin
Film transistor T3 and the 17th thin film transistor (TFT) T17 is opened, and constant pressure low level source Vss is passed by the 17th thin film transistor (TFT) T17
To the grid of the 4th thin film transistor (TFT) T4 so that the 4th thin film transistor (TFT) is closed, and constant pressure high level source passes through the 3rd film crystal
Pipe T3 reaches the output terminal of voltage regulation signal P (n), and the output terminal of voltage regulation signal P (n) is connected with one end of bootstrap capacitor Cbt, i.e.,
The constant pressure high level that constant pressure high level source VDD is provided continues to charge to bootstrap capacitor Cbt.
When the grade communication ST (n+1) of next stage switchs to high level, the 7th thin film transistor (TFT) T7 and the 8th film crystal
Pipe T8 is opened, and the constant pressure low level that constant pressure low level source Vss is generated reaches the scanning signal G of the first reference point Q (n) and this grade
(n) output terminal, the voltage at the first reference point Q (n) places and the scanning signal G (n) of this grade are pulled low.
Since the first reference point Q (n) switchs to low level so that the tenth thin film transistor (TFT) T10 and the 12nd thin film transistor (TFT)
T12 is closed, meanwhile, the high level of the clock signal CK (n) of this grade at this time is brilliant through the 9th thin film transistor (TFT) T9 and the 11st film
Body pipe T11 reaches the grid of the 13rd thin film transistor (TFT) T13 and the grid of the 14th thin film transistor (TFT) T14 so that the 13rd is thin
Film transistor T13 and the 14th thin film transistor (TFT) T14 is opened, and the constant pressure low level that constant pressure low level source Vss is generated maintains first
The low level of reference point Q (n) and this grade of scanning signal G (n) output terminal.
It is specifically intended that when the scanning signal G (n) of this grade is low level, the 3rd thin film transistor (TFT) T3 and the 17th
Thin film transistor (TFT) is closed, and the constant pressure high level that constant pressure high level source provides reaches the 4th film crystalline substance by the second thin film transistor (TFT) T2
The grid of body pipe T4 so that the 4th thin film transistor (TFT) is opened, and then the constant pressure low level that constant pressure low level source provides reaches voltage stabilizing
The output terminal of module 204 so that voltage regulation signal P (n) is low level.
This preferred embodiment can also make circuit by the 15th thin film transistor (TFT) T15 and the 16th thin film transistor (TFT) T16
One smaller state of interior maintenance over any time period, will not cause the power consumption of circuit to increase, specifically, when the grade of upper level passes
Signal ST (n-1) is low level, and when second clock signal is high level, the 15th thin film transistor (TFT) T15 and the 16th film are brilliant
Body pipe T16 is opened, and the constant pressure low level that constant pressure low level source Vss is provided reaches the output terminal of the scanning signal G (n) of this grade.
The GOA circuits of this preferred embodiment are by setting a Voltage stabilizing module, by the output terminal and bootstrap capacitor of Voltage stabilizing module
One end connection, Voltage stabilizing module output terminal output voltage regulation signal it is consistent with the scanning signal of this grade, it is defeated using Voltage stabilizing module
The voltage regulation signal gone out promotes current potential, plays the effect as existing GOA circuits, and reduces on scanning signal output terminal
Parasitic capacitance, so as to improve the display quality of liquid crystal display panel.
Referring to Fig. 3, for the structure diagram of the second preferred embodiment of the GOA circuits of the present invention；
Difference lies in Voltage stabilizing modules 304 for the GOA circuits of this preferred embodiment and the GOA circuits of first preferred embodiment
On the 17th thin film transistor (TFT) T17 grid be electrically connected at this grade grade communication ST (n) output terminal, can be further
The parasitic capacitance on scanning signal G (n) output terminals of this grade is reduced, improves the display quality of liquid crystal display panel.
The GOA circuits of this preferred embodiment include pull-up control module 301, pull-up module 306, lower transmission module 303, drop-down
Module 305, drop-down maintenance module 302, bootstrap capacitor Cbt and Voltage stabilizing module 304.Control module 301 is pulled up, for by upper one
The control of the grade communication ST (n-1) of grade generates the scanning level signal of this grade；Module 306 is pulled up, for sweeping according to this grade
The clock signal CK (n) for retouching level signal and this grade draws high the scanning signal of this grade；Lower transmission module 303, for according to this grade
Scanning level signal and the clock signal CK (n) of this grade generate the grade communication ST (n) of this grade；Module 305 is pulled down, is used for
According to the grade communication ST (n+1) of next stage, the scanning level signal of this grade is dragged down；Maintenance module 302 is pulled down, for maintaining this
The low level of the scanning level signal of grade；Bootstrap capacitor Cbt is used to generate the high level of the scanning signal of this grade；And voltage stabilizing mould
Block, for exporting the voltage regulation signal consistent with the scanning signal G (n) of this grade；
Wherein, control module 301 is pulled up to tie up with pull-up module 306, lower transmission module 303, drop-down module 305, drop-down respectively
It holds module 302 to connect, the output terminal of Voltage stabilizing module 304 is connected with one end of bootstrap capacitor Cbt, the other end of bootstrap capacitor Cbt
It is electrically connected at the output terminal of pull-up control module 301.
Pulling up control module 301 includes first film transistor T1, the grid access upper level of first film transistor T1
Grade communication ST (n-1), the source electrode of first film transistor T1 is electrically connected at constant pressure high level source VDD, and the first film is brilliant
The drain electrode of body pipe T1 is electrically connected at the output terminal of pull-up control module 301.
Pulling up module 306 includes the 6th thin film transistor (TFT) T6, and the grid of the 6th thin film transistor (TFT) T6 is electrically connected at pull-up
The output terminal of control module 301, the source electrode of the 6th thin film transistor (TFT) T6 access the clock signal CK (n) of this grade, and the 6th film is brilliant
The drain electrode of body pipe T6 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
Lower transmission module 303 includes the 5th thin film transistor (TFT) T5, and the grid of the 5th thin film transistor (TFT) T5 is electrically connected at pull-up
The output terminal of control module 301, the source electrode of the 5th thin film transistor (TFT) T5 access the clock signal CK (n) of this grade, and the 5th film is brilliant
The drain electrode of body pipe T5 is electrically connected at the output terminal of the grade communication ST (n) of this grade.
Pulling down module includes the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8；
The grade communication ST (n+1) of the grid access next stage of 7th thin film transistor (TFT) T7, the 7th thin film transistor (TFT) T7's
Source electrode is electrically connected at constant pressure low level source Vss, the 7th thin film transistor (TFT) T7 drain electrode and is electrically connected at pull-up control module 301
Output terminal；
The grade communication ST (n+1) of the grid access next stage of 8th thin film transistor (TFT) T8, the 8th thin film transistor (TFT) T8's
Source electrode is electrically connected at constant pressure low level source Vss, and the drain electrode of the 8th thin film transistor (TFT) T8 is electrically connected at the scanning signal G of this grade
(n) output terminal.
Pulling down maintenance module 302 includes the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11st film crystal
Pipe T11, the 12nd thin film transistor (TFT) T12, the 13rd thin film transistor (TFT) T13 and the 14th thin film transistor (TFT) T14；
The grid and source electrode of 9th thin film transistor (TFT) T9 access the clock signal CK (n) of this grade, the 9th thin film transistor (TFT) T9
Drain electrode be electrically connected at the 11st thin film transistor (TFT) T11 grid and the tenth thin film transistor (TFT) T10 drain electrode；
The grid of tenth thin film transistor (TFT) T10 is electrically connected at the output terminal of pull-up control module 301, the tenth film crystal
Pipe T10 source electrodes are electrically connected at constant pressure low level source Vss；
The source electrode of 11st thin film transistor (TFT) T11 accesses the clock signal of this grade, the drain electrode of the 11st thin film transistor (TFT) T11
It is brilliant to be electrically connected at the grid of the 13rd thin film transistor (TFT) T13, the grid of the 14th thin film transistor (TFT) T14 and the 12nd film
The drain electrode of body pipe T12；
The grid of 12nd thin film transistor (TFT) T12 is electrically connected at the output terminal of pull-up control module 301, the 12nd film
The source electrode access constant pressure low level source Vss of transistor T12；
The source electrode of 13rd thin film transistor (TFT) T13 is electrically connected at constant pressure low level source Vss, the 13rd thin film transistor (TFT)
The drain electrode of T13 is electrically connected at the output terminal of pull-up control module 301；
The source electrode of 14th thin film transistor (TFT) T14 is electrically connected at constant pressure low level source Vss, the 14th thin film transistor (TFT)
The drain electrode of T14 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
Voltage stabilizing module includes the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 and the
17 thin film transistor (TFT) T17；
The grid and source electrode of second thin film transistor (TFT) T2 is electrically connected at constant pressure high level source VDD, the second thin film transistor (TFT)
The drain electrode of T2 is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) T17 of the 4th thin film transistor (TFT) T4；
The grid of 3rd thin film transistor (TFT) T3 is electrically connected at the output terminal of the scanning signal G (n) of this grade, and the 3rd film is brilliant
The source electrode of body pipe T3 is electrically connected at constant pressure high level source VDD, and the drain electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at voltage stabilizing mould
The output terminal of block 304；
The source electrode of 4th thin film transistor (TFT) T4 is electrically connected at constant pressure low level source Vss, the leakage of the 4th thin film transistor (TFT) T4
Pole is electrically connected the output terminal of cloud Voltage stabilizing module 304；
The source electrode of 17th thin film transistor (TFT) T17 is electrically connected at constant pressure low level source Vss, the 17th thin film transistor (TFT)
The grid of T17 is electrically connected at the output terminal of the ST (n) of the grade communication number of this grade.
The GOA circuits of this preferred embodiment further include the 15th thin film transistor (TFT) T15 and the 16th thin film transistor (TFT) T16；
The grid access second clock signal XCK (n) of 15th thin film transistor (TFT) T15, the 15th thin film transistor (TFT) T15's
Source electrode accesses the grade communication ST (n-1) of upper level, and the drain electrode of the 15th thin film transistor (TFT) T15 is electrically connected at pull-up control mould
The output terminal of block 301；
The grid access second clock signal XCK (n) of 16th thin film transistor (TFT) T16, the 16th thin film transistor (TFT) T16's
Source electrode be electrically connected at constant pressure low level source Vss, the 16th thin film transistor (TFT) T16 drain electrode be electrically connected at this grade scanning letter
The output terminal of number G (n)；Wherein,
The phase of second clock signal XCK (n) and clock signal CK (n) opposite in phase of this grade.
Referring to Fig. 3, Fig. 5, the GOA circuits of this preferred embodiment are in use, when the grade communication ST (n-1) of upper level is height
During level, first film transistor T1 conductings, the constant pressure high level that constant pressure high level source provides passes through first film transistor T1
It charges to bootstrap capacitor Cbt so that the first reference point Q (n) rises to a higher level.
The grade communication ST (n-1) of subsequent upper level switchs to low level, and first film transistor T1 is closed, the first reference point
Q (n) maintains a higher level by bootstrap capacitor Cbt.Meanwhile the clock signal CK (n) of this grade switchs to high level, this grade
Scanning signal G (n) and grade communication ST (n) also switch to high level.When the grade communication ST (n) of this grade is high level, the 3rd
Thin film transistor (TFT) T3 and the 17th thin film transistor (TFT) T17 is opened, and constant pressure low level source Vss passes through the 17th thin film transistor (TFT) T17
Reach the grid of the 4th thin film transistor (TFT) T4 so that the 4th thin film transistor (TFT) T4 is closed, and constant pressure high level source VDD is thin by the 3rd
Film transistor T3 reaches the output terminal of voltage regulation signal P (n), and one end of the output terminal of voltage regulation signal P (n) and bootstrap capacitor Cbt
Connection, i.e. the constant pressure high level that constant pressure high level source VDD is provided continue to charge to bootstrap capacitor Cbt.
When the grade communication ST (n+1) of next stage switchs to high level, the 7th thin film transistor (TFT) T7 and the 8th film crystal
Pipe T8 is opened, and the constant pressure low level that constant pressure low level source Vss is generated reaches the scanning signal G of the first reference point Q (n) and this grade
(n) output terminal, the voltage at the first reference point Q (n) places and the scanning signal G (n) of this grade are pulled low.
Since the first reference point Q (n) switchs to low level so that the tenth thin film transistor (TFT) T10 and the 12nd thin film transistor (TFT)
T12 is closed, meanwhile, the high level of the clock signal CK (n) of this grade at this time is brilliant through the 9th thin film transistor (TFT) T9 and the 11st film
Body pipe T11 reaches the grid of the 13rd thin film transistor (TFT) T13 and the grid of the 14th thin film transistor (TFT) T14 so that the 13rd is thin
Film transistor T13 and the 14th thin film transistor (TFT) T14 is opened, and the constant pressure low level that constant pressure low level source Vss is generated maintains first
The low level of reference point Q (n) and this grade of scanning signal G (n) output terminal.
It is specifically intended that when the scanning signal G (n) of this grade and the grade communication ST (n) of this grade are low level, the 3rd
Thin film transistor (TFT) T3 and the 17th thin film transistor (TFT) are closed, and the constant pressure high level that constant pressure high level source provides is brilliant by the second film
Body pipe T2 reaches the grid of the 4th thin film transistor (TFT) T4 so that the 4th thin film transistor (TFT) is opened, and then constant pressure low level source provides
Constant pressure low level reach the output terminal of Voltage stabilizing module 204 so that voltage regulation signal P (n) is low level.
This preferred embodiment can also make circuit by the 15th thin film transistor (TFT) T15 and the 16th thin film transistor (TFT) T16
One smaller state of interior maintenance over any time period, will not cause the power consumption of circuit to increase, specifically, when the grade of upper level passes
Signal ST (n-1) is low level, and when second clock signal is high level, the 15th thin film transistor (TFT) T15 and the 16th film are brilliant
Body pipe T16 is opened, and the constant pressure low level that constant pressure low level source Vss is provided reaches the output terminal of the scanning signal G (n) of this grade.
The GOA circuits of this preferred embodiment are by setting a Voltage stabilizing module, by the output terminal and bootstrap capacitor of Voltage stabilizing module
One end connection, Voltage stabilizing module output terminal output voltage regulation signal it is consistent with the scanning signal of this grade, it is defeated using Voltage stabilizing module
The voltage regulation signal gone out promotes current potential, plays the effect as existing GOA circuits, and reduces on scanning signal output terminal
Parasitic capacitance, so as to improve the display quality of liquid crystal display panel.
Referring to Fig. 4, for the structure diagram of the third preferred embodiment of the GOA circuits of the present invention；
The GOA circuits of this preferred embodiment and first preferred embodiment and the area of the GOA circuits of the second preferred embodiment
It is not, the grid of the 17th thin film transistor (TFT) T17 on Voltage stabilizing module 404 accesses the clock signal CK (n), Ke Yijin of this grade
One step reduces the parasitic capacitance on scanning signal G (n) output terminals of this grade, improves the display quality of liquid crystal display panel.
The GOA circuits of this preferred embodiment include pull-up control module 401, pull-up module 406, lower transmission module 403, drop-down
Module 405, drop-down maintenance module 402, bootstrap capacitor Cbt and Voltage stabilizing module 404.Control module 401 is pulled up, for by upper one
The control of the grade communication ST (n-1) of grade generates the scanning level signal of this grade；Module 406 is pulled up, for sweeping according to this grade
The clock signal CK (n) for retouching level signal and this grade draws high the scanning signal of this grade；Lower transmission module 403, for according to this grade
Scanning level signal and the clock signal CK (n) of this grade generate the grade communication ST (n) of this grade；Module 405 is pulled down, is used for
According to the grade communication ST (n+1) of next stage, the scanning level signal of this grade is dragged down；Maintenance module 402 is pulled down, for maintaining this
The low level of the scanning level signal of grade；Bootstrap capacitor Cbt is used to generate the high level of the scanning signal of this grade；And voltage stabilizing mould
Block, for exporting the voltage regulation signal consistent with the scanning signal of this grade；
Wherein, control module 401 is pulled up to tie up with pull-up module 406, lower transmission module 403, drop-down module 405, drop-down respectively
It holds module 402 to connect, the output terminal of Voltage stabilizing module 404 is connected with one end of bootstrap capacitor Cbt, the other end of bootstrap capacitor Cbt
It is electrically connected at the output terminal of pull-up control module 401.
Pulling up control module 401 includes first film transistor T1, the grid access upper level of first film transistor T1
Grade communication ST (n-1), the source electrode of first film transistor T1 is electrically connected at constant pressure high level source VDD, and the first film is brilliant
The drain electrode of body pipe T1 is electrically connected at the output terminal of pull-up control module 401.
Pulling up module 406 includes the 6th thin film transistor (TFT) T6, and the grid of the 6th thin film transistor (TFT) T6 is electrically connected at pull-up
The output terminal of control module 401, the source electrode of the 6th thin film transistor (TFT) T6 access the clock signal CK (n) of this grade, and the 6th film is brilliant
The drain electrode of body pipe T6 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
Lower transmission module 403 includes the 5th thin film transistor (TFT) T5, and the grid of the 5th thin film transistor (TFT) T5 is electrically connected at pull-up
The output terminal of control module 401, the source electrode of the 5th thin film transistor (TFT) T5 access the clock signal CK (n) of this grade, and the 5th film is brilliant
The drain electrode of body pipe T5 is electrically connected at the output terminal of the grade communication ST (n) of this grade.
Pulling down module includes the 7th thin film transistor (TFT) T7 and the 8th thin film transistor (TFT) T8；
The grade communication ST (n+1) of the grid access next stage of 7th thin film transistor (TFT) T7, the 7th thin film transistor (TFT) T7's
Source electrode is electrically connected at constant pressure low level source Vss, the 7th thin film transistor (TFT) T7 drain electrode and is electrically connected at pull-up control module 401
Output terminal；
The grade communication ST (n+1) of the grid access next stage of 8th thin film transistor (TFT) T8, the 8th thin film transistor (TFT) T8's
Source electrode is electrically connected at constant pressure low level source Vss, and the drain electrode of the 8th thin film transistor (TFT) T8 is electrically connected at the scanning signal G of this grade
(n) output terminal.
Pulling down maintenance module 402 includes the 9th thin film transistor (TFT) T9, the tenth thin film transistor (TFT) T10, the 11st film crystal
Pipe T11, the 12nd thin film transistor (TFT) T12, the 13rd thin film transistor (TFT) T13 and the 14th thin film transistor (TFT) T14；
The grid and source electrode of 9th thin film transistor (TFT) T9 access the clock signal CK (n) of this grade, the 9th thin film transistor (TFT) T9
Drain electrode be electrically connected at the 11st thin film transistor (TFT) T11 grid and the tenth thin film transistor (TFT) T10 drain electrode；
The grid of tenth thin film transistor (TFT) T10 is electrically connected at the output terminal of pull-up control module 401, the tenth film crystal
Pipe T10 source electrodes are electrically connected at constant pressure low level source Vss；
The source electrode of 11st thin film transistor (TFT) T11 accesses the clock signal of this grade, the drain electrode of the 11st thin film transistor (TFT) T11
It is brilliant to be electrically connected at the grid of the 13rd thin film transistor (TFT) T13, the grid of the 14th thin film transistor (TFT) T14 and the 12nd film
The drain electrode of body pipe T12；
The grid of 12nd thin film transistor (TFT) T12 is electrically connected at the output terminal of pull-up control module 401, the 12nd film
The source electrode access constant pressure low level source Vss of transistor T12；
The source electrode of 13rd thin film transistor (TFT) T13 is electrically connected at constant pressure low level source Vss, the 13rd thin film transistor (TFT)
The drain electrode of T13 is electrically connected at the output terminal of pull-up control module 401；
The source electrode of 14th thin film transistor (TFT) T14 is electrically connected at constant pressure low level source Vss, the 14th thin film transistor (TFT)
The drain electrode of T14 is electrically connected at the output terminal of the scanning signal G (n) of this grade.
Voltage stabilizing module 404 include the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3, the 4th thin film transistor (TFT) T4 and
17th thin film transistor (TFT) T17；
The grid and source electrode of second thin film transistor (TFT) T2 is electrically connected at constant pressure high level source VDD, the second thin film transistor (TFT)
The drain electrode of T2 is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) T17 of the 4th thin film transistor (TFT) T4；
The grid of 3rd thin film transistor (TFT) T3 is electrically connected at the output terminal of the scanning signal G (n) of this grade, and the 3rd film is brilliant
The source electrode of body pipe T3 is electrically connected at constant pressure high level source VDD, and the drain electrode of the 3rd thin film transistor (TFT) T3 is electrically connected at voltage stabilizing mould
The output terminal of block 404；
The source electrode of 4th thin film transistor (TFT) T4 is electrically connected at constant pressure low level source Vss, the leakage of the 4th thin film transistor (TFT) T4
Pole is electrically connected the output terminal of cloud Voltage stabilizing module 404；
The source electrode of 17th thin film transistor (TFT) T17 is electrically connected at constant pressure low level source Vss, the 17th thin film transistor (TFT)
The grid of T17 accesses the clock signal CK (n) of this grade.
The GOA circuits of this preferred embodiment further include the 15th thin film transistor (TFT) T15 and the 16th thin film transistor (TFT) T16；
The grid access second clock signal XCK (n) of 15th thin film transistor (TFT) T15, the 15th thin film transistor (TFT) T15's
Source electrode accesses the grade communication ST (n-1) of upper level, and the drain electrode of the 15th thin film transistor (TFT) T15 is electrically connected at pull-up control mould
The output terminal of block 401；
The grid access second clock signal XCK (n) of 16th thin film transistor (TFT) T16, the 16th thin film transistor (TFT) T16's
Source electrode be electrically connected at constant pressure low level source Vss, the 16th thin film transistor (TFT) T16 drain electrode be electrically connected at this grade scanning letter
The output terminal of number G (n)；Wherein,
The phase of second clock signal XCK (n) and clock signal CK (n) opposite in phase of this grade.
Referring to Fig. 4, Fig. 5, the GOA circuits of this preferred embodiment are in use, when the grade communication ST (n-1) of upper level is height
During level, first film transistor T1 conductings, the constant pressure high level that constant pressure high level source provides passes through first film transistor T1
It charges to bootstrap capacitor Cbt so that the first reference point Q (n) rises to a higher level.
The grade communication ST (n-1) of subsequent upper level switchs to low level, and first film transistor T1 is closed, the first reference point
Q (n) maintains a higher level by bootstrap capacitor Cbt.Meanwhile the clock signal CK (n) of this grade switchs to high level, this grade
Scanning signal G (n) and grade communication ST (n) also switch to high level.When the clock signal CK (n) of this grade is high level, the 3rd
Thin film transistor (TFT) T3 and the 17th thin film transistor (TFT) T17 is opened, and constant pressure low level source Vss passes through the 17th thin film transistor (TFT) T17
Reach the grid of the 4th thin film transistor (TFT) T4 so that the 4th thin film transistor (TFT) T4 is closed, and constant pressure high level source VDD is thin by the 3rd
Film transistor T3 reaches the output terminal of voltage regulation signal P (n), and one end of the output terminal of voltage regulation signal P (n) and bootstrap capacitor Cbt
Connection, i.e. the constant pressure high level that constant pressure high level source VDD is provided continue to charge to bootstrap capacitor Cbt.
When the grade communication ST (n+1) of next stage switchs to high level, the 7th thin film transistor (TFT) T7 and the 8th film crystal
Pipe T8 is opened, and the constant pressure low level that constant pressure low level source Vss is generated reaches the scanning signal G of the first reference point Q (n) and this grade
(n) output terminal, the voltage at the first reference point Q (n) places and the scanning signal G (n) of this grade are pulled low.
Since the first reference point Q (n) switchs to low level so that the tenth thin film transistor (TFT) T10 and the 12nd thin film transistor (TFT)
T12 is closed, meanwhile, the high level of the clock signal CK (n) of this grade at this time is brilliant through the 9th thin film transistor (TFT) T9 and the 11st film
Body pipe T11 reaches the grid of the 13rd thin film transistor (TFT) T13 and the grid of the 14th thin film transistor (TFT) T14 so that the 13rd is thin
Film transistor T13 and the 14th thin film transistor (TFT) T14 is opened, and the constant pressure low level that constant pressure low level source Vss is generated maintains first
The low level of reference point Q (n) and this grade of scanning signal G (n) output terminal.
It is specifically intended that when the scanning signal G (n) of this grade and the clock signal CK (n) of this grade are low level, the 3rd
Thin film transistor (TFT) T3 and the 17th thin film transistor (TFT) are closed, and the constant pressure high level that constant pressure high level source provides is brilliant by the second film
Body pipe T2 reaches the grid of the 4th thin film transistor (TFT) T4 so that the 4th thin film transistor (TFT) is opened, and then constant pressure low level source provides
Constant pressure low level reach the output terminal of Voltage stabilizing module 204 so that voltage regulation signal P (n) is low level.
This preferred embodiment can also make circuit by the 15th thin film transistor (TFT) T15 and the 16th thin film transistor (TFT) T16
One smaller state of interior maintenance over any time period, will not cause the power consumption of circuit to increase, specifically, when the grade of upper level passes
Signal ST (n-1) is low level, and when second clock signal is high level, the 15th thin film transistor (TFT) T15 and the 16th film are brilliant
Body pipe T16 is opened, and the constant pressure low level that constant pressure low level source Vss is provided reaches the output terminal of the scanning signal G (n) of this grade.
The GOA circuits of this preferred embodiment are by setting a Voltage stabilizing module, by the output terminal and bootstrap capacitor of Voltage stabilizing module
One end connection, Voltage stabilizing module output terminal output voltage regulation signal it is consistent with the scanning signal of this grade, it is defeated using Voltage stabilizing module
The voltage regulation signal gone out promotes current potential, plays the effect as existing GOA circuits, and reduces on scanning signal output terminal
Parasitic capacitance, so as to improve the display quality of liquid crystal display panel.
To sum up, although the present invention is disclosed above with preferred embodiment, above preferred embodiment is not to limit this
Invention, those of ordinary skill in the art, without departing from the spirit and scope of the present invention, can make it is various change and retouch,
Therefore protection scope of the present invention is subject to the scope that claim defines.
Claims (9)
1. a kind of GOA circuits, which is characterized in that including：
Control module is pulled up, for being generated the scanning level signal of this grade by the control of the grade communication number of upper level；
Module is pulled up, the scanning letter of this grade is drawn high for the scanning level signal according to described grade and the clock signal of this grade
Number；
Lower transmission module generates the grade communication of this grade for the scanning level signal according to described grade and the clock signal of this grade
Number；
Module is pulled down, for the grade communication number according to next stage, drags down the scanning level signal of described grade；
Maintenance module is pulled down, for maintaining the low level of the scanning level signal of described grade；
Bootstrap capacitor, for generating the high level of the scanning signal of described grade；And Voltage stabilizing module, for export with it is described
The consistent voltage regulation signal of this grade of scanning signal；Wherein, it is described pull-up control module respectively with it is described pull-up module, it is described under pass
Module, the drop-down module, the drop-down maintenance module connection, the output terminal of the Voltage stabilizing module and the one of the bootstrap capacitor
End connection, the other end of the bootstrap capacitor are electrically connected at the output terminal of the pull-up control module；
The drop-down maintenance module includes the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd
Thin film transistor (TFT), the 13rd thin film transistor (TFT) and the 14th thin film transistor (TFT)；
The grid and source electrode of 9th thin film transistor (TFT) access the clock signal of described grade, the 9th thin film transistor (TFT)
Drain electrode is electrically connected at the drain electrode of the grid and the tenth thin film transistor (TFT) of the 11st thin film transistor (TFT)；
The grid of tenth thin film transistor (TFT) is electrically connected at the output terminal of the pull-up control module, and the tenth film is brilliant
Body pipe source electrode is electrically connected at constant pressure low level source；
The source electrode of 11st thin film transistor (TFT) accesses the clock signal of described grade, the leakage of the 11st thin film transistor (TFT)
Pole is electrically connected at the grid of the 13rd thin film transistor (TFT), the grid and the described tenth of the 14th thin film transistor (TFT)
The drain electrode of two thin film transistor (TFT)s；
The grid of 12nd thin film transistor (TFT) is electrically connected at the output terminal of the pull-up control module, and the described 12nd is thin
The source electrode of film transistor accesses the constant pressure low level source；
The source electrode of 13rd thin film transistor (TFT) is electrically connected at the constant pressure low level source, the 13rd thin film transistor (TFT)
Drain electrode be electrically connected at it is described pull-up control module output terminal；
The source electrode of 14th thin film transistor (TFT) is electrically connected at the constant pressure low level source, the 14th thin film transistor (TFT)
Drain electrode be electrically connected at described grade scanning signal output terminal.
2. GOA circuits according to claim 1, which is characterized in that the pull-up control module includes the first film crystal
Pipe, the grid of the first film transistor access the grade communication number of the upper level, the source electrode of the first film transistor
Constant pressure high level source is electrically connected at, the drain electrode of the first film transistor is electrically connected at the defeated of the pull-up control module
Outlet.
3. GOA circuits according to claim 1, which is characterized in that the pull-up module includes the 6th thin film transistor (TFT), institute
The grid for stating the 6th thin film transistor (TFT) is electrically connected at the output terminal of the pull-up control module, the 6th thin film transistor (TFT)
Source electrode accesses the clock signal of described grade, and the drain electrode of the 6th thin film transistor (TFT) is electrically connected at the scanning letter of described grade
Number output terminal.
4. GOA circuits according to claim 1, which is characterized in that the lower transmission module includes the 5th thin film transistor (TFT), institute
The grid for stating the 5th thin film transistor (TFT) is electrically connected at the output terminal of the pull-up control module, the 5th thin film transistor (TFT)
Source electrode accesses the clock signal of described grade, and the drain electrode of the 5th thin film transistor (TFT) is electrically connected at the grade communication of described grade
Number output terminal.
5. GOA circuits according to claim 1, the drop-down module includes the 7th thin film transistor (TFT) and the 8th film crystal
Pipe；
The grade communication number of the grid access next stage of 7th thin film transistor (TFT), the source electrode of the 7th thin film transistor (TFT) are electrical
Constant pressure low level source is connected to, the 7th thin film transistor (TFT) drain electrode is electrically connected at the output terminal of the pull-up control module；
The grade communication number of the grid access next stage of 8th thin film transistor (TFT), the source electrode of the 8th thin film transistor (TFT) are electrical
The constant pressure low level source is connected to, tells that the drain electrode of the 8th thin film transistor (TFT) is electrically connected at the scanning signal of described grade
Output terminal.
6. GOA circuits according to claim 1, which is characterized in that the Voltage stabilizing module includes the second thin film transistor (TFT), the
Three thin film transistor (TFT)s, the 4th thin film transistor (TFT) and the 17th thin film transistor (TFT)；
The grid and source electrode of second thin film transistor (TFT) are electrically connected at constant pressure high level source, second thin film transistor (TFT)
Drain electrode is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) of the 4th thin film transistor (TFT)；
The grid of 3rd thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of described grade, the 3rd film
The source electrode of transistor is electrically connected at the constant pressure high level source, and the drain electrode of the 3rd thin film transistor (TFT) is electrically connected at described
The output terminal of Voltage stabilizing module；
The source electrode of 4th thin film transistor (TFT) is electrically connected at constant pressure low level source, the drain electrode electricity of the 4th thin film transistor (TFT)
Property is connected to the output terminal of the Voltage stabilizing module；
The source electrode of 17th thin film transistor (TFT) is electrically connected at the constant pressure low level source, the 17th film crystal
The grid of pipe is electrically connected at the output terminal of the scanning signal of described grade.
7. GOA circuits according to claim 1, which is characterized in that the Voltage stabilizing module includes the second thin film transistor (TFT), the
Three thin film transistor (TFT)s, the 4th thin film transistor (TFT) and the 17th thin film transistor (TFT)；
The grid and source electrode of second thin film transistor (TFT) are electrically connected at constant pressure high level source, second thin film transistor (TFT)
Drain electrode is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) of the 4th thin film transistor (TFT)；
The grid of 3rd thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of described grade, the 3rd film
The source electrode of transistor is electrically connected at the constant pressure high level source, and the drain electrode of the 3rd thin film transistor (TFT) is electrically connected at described
The output terminal of Voltage stabilizing module；
The source electrode of 4th thin film transistor (TFT) is electrically connected at constant pressure low level source, the drain electrode electricity of the 4th thin film transistor (TFT)
Property is connected to the output terminal of the Voltage stabilizing module；
The source electrode of 17th thin film transistor (TFT) is electrically connected at the constant pressure low level source, the 17th film crystal
The grid of pipe is electrically connected at the output terminal of the grade communication number of described grade.
8. GOA circuits according to claim 1, which is characterized in that the Voltage stabilizing module includes the second thin film transistor (TFT), the
Three thin film transistor (TFT)s, the 4th thin film transistor (TFT) and the 17th thin film transistor (TFT)；
The grid and source electrode of second thin film transistor (TFT) are electrically connected at constant pressure high level source, second thin film transistor (TFT)
Drain electrode is electrically connected at the drain electrode of the grid and the 17th thin film transistor (TFT) of the 4th thin film transistor (TFT)；
The grid of 3rd thin film transistor (TFT) is electrically connected at the output terminal of the scanning signal of described grade, the 3rd film
The source electrode of transistor is electrically connected at the constant pressure high level source, and the drain electrode of the 3rd thin film transistor (TFT) is electrically connected at described
The output terminal of Voltage stabilizing module；
The source electrode of 4th thin film transistor (TFT) is electrically connected at constant pressure low level source, the drain electrode electricity of the 4th thin film transistor (TFT)
Property is connected to the output terminal of the Voltage stabilizing module；
The source electrode of 17th thin film transistor (TFT) is electrically connected at the constant pressure low level source, the 17th film crystal
The grid of pipe accesses the clock signal of described grade.
9. GOA circuits according to claim 1, which is characterized in that further include the 15th thin film transistor (TFT) and the 16th thin
Film transistor；
The grid access second clock signal of 15th thin film transistor (TFT), the source electrode access of the 15th thin film transistor (TFT)
The grade communication number of the upper level, the drain electrode of the 15th thin film transistor (TFT) are electrically connected at the defeated of the pull-up control module
Outlet；
The grid of 16th thin film transistor (TFT) accesses the second clock signal, the source electrode of the 16th thin film transistor (TFT)
Constant pressure low level source is electrically connected at, the drain electrode of the 16th thin film transistor (TFT) is electrically connected at the scanning signal of described grade
Output terminal；Wherein,
The phase of the second clock signal is opposite with the clock signal phase of described grade.
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| CN107016973A (en) * | 2017-05-05 | 2017-08-04 | 惠科股份有限公司 | Shift scratch circuit and its display panel of application |
| CN107146590B (en) * | 2017-07-06 | 2020-03-27 | 深圳市华星光电技术有限公司 | Driving method of GOA circuit |
| CN110148382B (en) * | 2019-05-08 | 2020-08-04 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit, display panel and display device |
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| CN104167192A (en) * | 2014-07-22 | 2014-11-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN104882107A (en) * | 2015-06-03 | 2015-09-02 | 深圳市华星光电技术有限公司 | Gate drive circuit |
| CN105047158A (en) * | 2015-08-21 | 2015-11-11 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display |
| CN105321491A (en) * | 2015-11-18 | 2016-02-10 | 武汉华星光电技术有限公司 | Gate driver on array drive circuit and liquid crystal display using gate driver on array drive circuit |
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| KR101908508B1 (en) * | 2012-03-29 | 2018-10-18 | 엘지디스플레이 주식회사 | Shift register |
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| CN104167192A (en) * | 2014-07-22 | 2014-11-26 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN104882107A (en) * | 2015-06-03 | 2015-09-02 | 深圳市华星光电技术有限公司 | Gate drive circuit |
| CN105047158A (en) * | 2015-08-21 | 2015-11-11 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display |
| CN105321491A (en) * | 2015-11-18 | 2016-02-10 | 武汉华星光电技术有限公司 | Gate driver on array drive circuit and liquid crystal display using gate driver on array drive circuit |
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