CN105932021B - Method for preventing the antenna effect of semiconductor chip domain - Google Patents
Method for preventing the antenna effect of semiconductor chip domain Download PDFInfo
- Publication number
- CN105932021B CN105932021B CN201610320945.0A CN201610320945A CN105932021B CN 105932021 B CN105932021 B CN 105932021B CN 201610320945 A CN201610320945 A CN 201610320945A CN 105932021 B CN105932021 B CN 105932021B
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- Prior art keywords
- semiconductor chip
- preventing
- antenna effect
- chip domain
- grid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of for preventing the method for the antenna effect of semiconductor chip domain, comprising: using the first device being mutually matched and the second device composition differential pair tube；P-type heavily doped region is added in the metal layer closest to substrate near the grid of the first device and the second device, the N trap of the p-type heavily doped region and periphery that make addition forms a parasitic diode, and the gate terminal of the first device and the second device is connected to the metal layer closest to substrate by polysilicon via p-type heavily doped region, so that charge is released from parasitic diode.
Description
Technical field
The present invention relates to semiconductor design and manufacturing fields, it is more particularly related to a kind of for preventing partly to lead
The method of the antenna effect of body chip layout.
Background technique
Currently, there are two ways to preventing antenna effect on common domain.
One is " jumper wirings ", and there are the metal layers of antenna effect for wire jumper i.e. disconnection, are connected to other layers by through-hole, most
After return current layer.This method solves antenna effect by changing the level of metal line, but increases simultaneously logical
Hole.Moreover, since the resistance of through-hole is very big, will have a direct impact on the timing and cross-interference issue of chip in " jumper wiring ", so
The quantity of strict control wiring layer variability and through-hole is wanted when using the method.Specifically, antenna effect is exactly single in etching
Layer polysilicon or metal when, since length is too long or area is excessive, ion etching bring charge accumulated and may cause
Gate oxide breakdown.As for the first metal layer, i.e., closest to (condition does not have certainly after the completion of the metal layer of substrate (metal1)
Antenna effect, length is not enough or area is smaller), it is subsequent to be walked through outgrowth insulating layer, the first metal layer through-hole (via1) etc.
Suddenly, during this, on the first metal layer due to ion etching accumulation charge also can in the production process of factory different journeys
Degree is led.At this time come ion etching second metal layer (metal2) again, since second metal layer is farther apart from gate oxide,
The electric field action of gate oxide will be reduced.But wire jumper is the possibility for reducing breakdown gate oxide, it cannot be fundamentally
Solve technique bring charge.
Another kind is " addition antenna device ".When " antenna effect " occurs in top metal, usually using " addition
The method of antenna device ".Back biased diode is added to " antenna ".By to be directly connected to grid there are the metals of antenna effect
Layer connects back biased diode, as soon as forming a charge discharging resisting circuit, stored charge does not constitute threat to grid oxygen, to eliminate day
Line effect.When there is sufficient space in metal layer position, diode can be directly added, wiring hinders or metal layer is located at taboo if encountering
Only when region, it is necessary to metal wire be extended to the place for nearby having sufficient space by through-hole, be inserted into diode.As it can be seen that inserting
Enough areas will be had by entering diode, while diode is added in domain, in order to by consistency check inspection (LVS,
Layout Versus schematic), diode component must be added in circuit, it is total although not influencing the performance of circuit
Return is to be added to device more.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can be saved
The method that area can effectively prevent the antenna effect for preventing semiconductor chip domain of antenna effect again.
In order to achieve the above technical purposes, according to the present invention, it provides a kind of for preventing the day of semiconductor chip domain
The method of line effect, comprising: using the first device being mutually matched and the second device composition differential pair tube；In the first device and
P-type heavily doped region is added in the metal layer closest to substrate near the grid of two devices, makes the p-type heavily doped region of addition
A parasitic diode is formed with the N trap of periphery, and by the gate terminal of the first device and the second device via p-type heavily doped region
Domain is connected to the metal layer closest to substrate by polysilicon.
Preferably, described for preventing the method for the antenna effect of semiconductor chip domain further include: in the first device and
Respective two dummy elements are respectively configured in second device.
Preferably, the drain terminal of the drain terminal of the first device and the second device connects different sites, the source of the first device M1 respectively
The source of end and the second device is connected to same site.
Preferably, the grid of the first device is connected to grid reference voltage, and the grid of the second device is connected to network-feedback voltage.
Preferably, second in the relative proximity of the first dummy elements and the second device of the relative proximity of the first device is empty
If the drain terminal of element is coupled with the source of the first device and the second device.
Preferably, another two piece void of the grid and source electrode of the first dummy elements and the second dummy elements together with the first device
If three ends of another two dummy elements of element and the second device are connected to the supply voltage of periphery.
Preferably, the first device and the second device are kept apart by isolation ring.
Preferably, the method for preventing the antenna effect of semiconductor chip domain is set for semiconductor chip domain
Meter.
Preferably, the first device and the second device are P-type device.
In the present invention, addition antenna device diode is not needed, does not need metal wire to be jumped to top go yet.And
Heavily doped region is added herein, not at all waste area.Similarly avoid the generation of antenna effect.The present invention mentions as a result,
It is simple to have gone out a kind of structure, area can be saved but also has effectively prevented antenna effect, the present invention only passes through is imitated using prevention antenna
The basic principle answered solves the problems, such as antenna effect, while breaking previous consistent way, compared with previous way, the method
It does not need not only to add diode on circuit, does not need to occupy extra area yet, do not need more to get on wire jumper in domain.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 schematically shows the antenna effect according to the preferred embodiment of the invention for preventing semiconductor chip domain
The schematic diagram for the method answered.
The antenna effect that Fig. 2 schematically shows according to the preferred embodiment of the invention for preventing semiconductor chip domain
The partial schematic diagram for the method answered.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
The invention belongs to prevent a kind of new method of antenna effect in layout design, the present invention makes full use of antenna effect
The mechanism of generation goes to solve the problems, such as by the mechanism of generation, while considering the area of domain and the convenience of cabling, final
To a kind of antenna effect for preventing semiconductor chip domain that can be saved area but also effectively prevent antenna effect
Method.
Specifically, in the production process of chip, the conductors such as exposed metal wire or polysilicon are like day one by one
Line, can collect charge causes current potential to increase.Antenna is longer, and the charge of collection is also more, and voltage is higher.If this piece conductor touches
The grid for ingeniously having met MOS make circuit malfunction then high voltage may puncture thin gate oxide, and here it is antenna effects.With
A possibility that size of the development of technology, grid is smaller and smaller, and the number of plies of metal is more and more, and antenna effect occurs is also more next
It is bigger.The damage that the biggish grid of area ratio obtain is smaller.
Specifically, Fig. 1 schematically shows according to the preferred embodiment of the invention for preventing semiconductor chip domain
Antenna effect method schematic diagram.For example, in specific application, use according to the preferred embodiment of the invention shown in FIG. 1
Semiconductor chip layout design is advantageously used in the method for the antenna effect of prevention semiconductor chip domain.
As shown in Figure 1, according to the preferred embodiment of the invention for preventing the side of the antenna effect of semiconductor chip domain
Method includes:
First step S1: differential pair tube is formed using the device that the first device M1 and the second device M2 two are mutually matched
(preferably, the first device M1 and the second device M2 is P-type device)；
Second step S2: add in the metal layer closest to substrate near the grid of the first device M1 and the second device M2
Add p-type heavily doped region 10, the N trap 20 of the p-type heavily doped region and periphery that make addition forms a parasitic diode, and will
The gate terminal of first device M1 and the second device M2 are connected to by polysilicon closest to substrate via p-type heavily doped region 10
Metal layer, so that charge is released from parasitic diode (as shown in Figure 2)；
Third step S3: respective two dummy elements are respectively configured in the first device M1 and the second device M2.
Wherein, the drain terminal of the drain terminal of the first device M1 and the second device M2 connect different sites respectively, the first device M1's
Source and the source of the second device M2 are connected to same site；The grid of first device M1 is connected to grid reference voltage, the second device
The grid of part M2 is connected to network-feedback voltage.
Second in the relative proximity of the first dummy elements and the second device M2 of the relative proximity of the first device M1 is illusory
The drain terminal of element is coupled with the source of the first device M1 and the second device M2, the grid of the first dummy elements and the second dummy elements
Three ends of pole and source electrode together with another two dummy elements of the first device M1 and another two dummy elements of the second device M2
It is connected on the supply voltage (VDD) of periphery.
First device M1 and the second device M2 cannot by any external world signal it is dry scratch, therefore with isolation ring by the first device
M1 and the second device M2 individually keep apart.
The gate terminal of first device M1 and the second device M2 are connected to most via p-type heavily doped region 10 by polysilicon
Close to the metal layer of substrate.This it is, in principle, that be exactly to generate parasitic diode in fact.To which antenna effect will not be caused.
In the method for the antenna effect according to the preferred embodiment of the invention for preventing semiconductor chip domain, first
Device M1 and the second both sides device M2 add illusory device and play protective effect, in order to avoid in etching to the first device M1 and the
This of two device M2 composition generates different influences to difference pipe and matching effect is deteriorated, and uses the purpose of illusory device
It is in order to by the design rule check of small technique.
In the method for the antenna effect according to the preferred embodiment of the invention for preventing semiconductor chip domain, it is not required to
Antenna device diode is added, does not also need metal wire to be jumped to top go.And the heavily doped region added here is not
Waste area.Moreover, similarly avoiding the generation of antenna effect.
The present invention has than the prior art " jumper wiring " to be advantageous in that, if wire jumper, when wire jumper will have time certainly
Between remove wire jumper, if encountering more complicated domain, cabling is relatively more, at all just can not near grid wire jumper, and it is of the invention
As long as directly hole is got on heavily doped region.However compared with " the addition antenna device method " of the prior art, day is added
Line device part needs individually specially to put diode with one piece of empty place, it is well known that and domain saves area and is very important, and this
Invention does not need individual place then and goes to put diode, and area saves, and does not need to add additional device yet.
As a result, the invention proposes a kind of structure is simple, area can be saved but also effectively prevent antenna effect, the present invention
Antenna effect is only solved the problems, such as by the basic principle using prevention antenna effect, while breaking previous consistent way,
Compared with previous way, the method does not need not only to add diode on circuit, does not need to occupy extra area yet, more be not required to
To get on wire jumper in domain.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
Claims (9)
1. a kind of for preventing the method for the antenna effect of semiconductor chip domain, characterized by comprising: use and be mutually matched
The first device and the second device form differential pair tube；Near the grid of the first device and the second device closest to substrate
P-type heavily doped region is added in metal layer, the N trap of the p-type heavily doped region and periphery that make addition forms a parasitic diode,
And the gate terminal of the first device and the second device is connected to by polysilicon closest to substrate via p-type heavily doped region
Metal layer.
2. according to claim 1 for preventing the method for the antenna effect of semiconductor chip domain, it is characterised in that also
It include: that respective two dummy elements are respectively configured in the first device and the second device.
3. according to claim 1 or 2 for preventing the method for the antenna effect of semiconductor chip domain, feature exists
In the drain terminal of the drain terminal of the first device and the second device connects different sites, the source and the second device of the first device M1 respectively
Source be connected to same site.
4. according to claim 1 or 2 for preventing the method for the antenna effect of semiconductor chip domain, feature exists
In the grid of the first device is connected to grid reference voltage, and the grid of the second device is connected to network-feedback voltage.
5. according to claim 2 for preventing the method for the antenna effect of semiconductor chip domain, which is characterized in that
The drain terminal of second dummy elements of the relative proximity of the first dummy elements and the second device of the relative proximity of the first device is distinguished
It is connected to the source of the first device and the second device.
6. according to claim 5 for preventing the method for the antenna effect of semiconductor chip domain, which is characterized in that the
The grid and source electrode of one dummy elements and the second dummy elements together with the first device another dummy elements and the second device it is another
Three ends of one dummy elements are connected to the supply voltage of periphery.
7. according to claim 1 or 2 for preventing the method for the antenna effect of semiconductor chip domain, feature exists
In the first device and the second device are kept apart by isolation ring.
8. according to claim 1 or 2 for preventing the method for the antenna effect of semiconductor chip domain, feature exists
In the method for preventing the antenna effect of semiconductor chip domain is for semiconductor chip layout design.
9. according to claim 1 or 2 for preventing the method for the antenna effect of semiconductor chip domain, feature exists
In the first device and the second device are P-type device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610320945.0A CN105932021B (en) | 2016-05-13 | 2016-05-13 | Method for preventing the antenna effect of semiconductor chip domain |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610320945.0A CN105932021B (en) | 2016-05-13 | 2016-05-13 | Method for preventing the antenna effect of semiconductor chip domain |
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| CN105932021A CN105932021A (en) | 2016-09-07 |
| CN105932021B true CN105932021B (en) | 2019-02-01 |
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| CN113095036B (en) * | 2021-03-30 | 2024-03-22 | 上海华力微电子有限公司 | Method for judging antenna effect of three-dimensional structure |
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| CN101499471A (en) * | 2008-01-29 | 2009-08-05 | 中芯国际集成电路制造(上海)有限公司 | Anti-electrostatic discharge input resistance and its production method |
| CN102034807A (en) * | 2009-09-27 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Method and device for protecting grid electrode |
| CN102569400A (en) * | 2011-12-13 | 2012-07-11 | 钜泉光电科技(上海)股份有限公司 | Metal-oxide-semiconductor device |
| CN103928457A (en) * | 2012-12-07 | 2014-07-16 | 阿尔特拉公司 | Antenna Diode Circuitry And Method Of Manufacture |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101068569B1 (en) * | 2010-05-28 | 2011-09-30 | 주식회사 하이닉스반도체 | Protection circuit of semiconductor device |
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- 2016-05-13 CN CN201610320945.0A patent/CN105932021B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083264A (en) * | 2006-06-02 | 2007-12-05 | 中芯国际集成电路制造(上海)有限公司 | Proctive circuit of metal-oxide-semiconductor transistor and its producing method |
| CN101499471A (en) * | 2008-01-29 | 2009-08-05 | 中芯国际集成电路制造(上海)有限公司 | Anti-electrostatic discharge input resistance and its production method |
| CN102034807A (en) * | 2009-09-27 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Method and device for protecting grid electrode |
| CN102569400A (en) * | 2011-12-13 | 2012-07-11 | 钜泉光电科技(上海)股份有限公司 | Metal-oxide-semiconductor device |
| CN103928457A (en) * | 2012-12-07 | 2014-07-16 | 阿尔特拉公司 | Antenna Diode Circuitry And Method Of Manufacture |
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| CN105932021A (en) | 2016-09-07 |
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