CN105931594B - Pixel circuit, driving method, array substrate, display panel and display device - Google Patents
Pixel circuit, driving method, array substrate, display panel and display device Download PDFInfo
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- CN105931594B CN105931594B CN201610538486.3A CN201610538486A CN105931594B CN 105931594 B CN105931594 B CN 105931594B CN 201610538486 A CN201610538486 A CN 201610538486A CN 105931594 B CN105931594 B CN 105931594B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The present invention provides a kind of pixel circuit, driving method, array substrate, display panel and display device.Pixel circuit includes thin film transistor (TFT) TFT and capacitor；The grid of the TFT is connect with grid line, and the first pole of the TFT is connect with one end of the capacitor；The other end of the capacitor is connect with power supply line；The pixel circuit further include: data voltage control unit, for by bias voltage and data voltage output to the second pole of the TFT.The present invention can be compensated since there are parasitic capacitance Cgs between the grid of TFT and the source electrode of TFT to the fluctuation voltage △ Vp when grid line opens and closes on actual pixels, and can be improved in the prior art due to public electrode voltages are coupled and are generated display bad phenomenon.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of pixel circuit, driving method, array substrate, display surfaces
Plate and display device.
Background technique
As shown in Figure 1A, existing pixel circuit includes thin film transistor (TFT) TFT and capacitor C, due to the grid and TFT of TFT
Source electrode between there are parasitic capacitance Cgs, therefore grid line open and close when actual pixels on voltage exist fluctuation (fluctuation
Voltage, that is, △ Vp), the prior art offsets the influence of △ Vp by the way that public electrode voltages VCOM is arranged in one end of capacitor C.But
Since the voltage driving capability of the public electrode wire of output public electrode voltages VCOM is limited, easily by data under heavily loaded picture
Voltage coupling, is fluctuated, so that deviation occurs in the voltage being actually loaded in pixel, the bad phenomenons such as greening occur.In Fig. 1
In, Data unlabeled data line, Gate indicates grid line.
Summary of the invention
The main purpose of the present invention is to provide a kind of pixel circuit, driving method, array substrate, display panel and displays
Device, to solve in the prior art in compensation since there are parasitic capacitances between the grid of TFT and the source electrode of TFT in grid line
Public electrode when fluctuation voltage when opening and closing on actual pixels due to public electrode wire driving capability difference to generate
Voltage is easy to be coupled by data voltage and led to the problem of display bad phenomenon.
In order to achieve the above object, the present invention provides a kind of pixel circuits, including thin film transistor (TFT) TFT and capacitor (C)；
The grid of the TFT is connect with grid line, and the first pole of the TFT is connect with one end of the capacitor (C)；
The other end of the capacitor (C) is connect with power supply line；
The pixel circuit further include:
Data voltage control unit, for by bias voltage and data voltage output to the second pole of the TFT.
When implementation, the data voltage control unit respectively with the data line, biasing voltage signal line and the TFT
The connection of second pole, the data voltage that bias voltage and data line for providing biasing voltage signal line provide are exported to described
The second pole of TFT.
When implementation, the data voltage control unit includes loading capacitance and loading resistor；
The both ends of the loading capacitance are connect with the second pole of the data line and the TFT respectively；
The both ends of the loading resistor are connect with the second pole of the biasing voltage signal line and the TFT respectively.
When implementation, the power supply line is ground wire.
The present invention also provides a kind of driving methods of pixel circuit, applied to above-mentioned pixel circuit, the driving side
Method includes:
Data voltage control unit is by bias voltage and data voltage output to the second pole of TFT.
When implementation, the driving method is specifically included: the data voltage control unit provides biasing voltage signal line
Bias voltage and data line provide data voltage export to the second pole of the TFT.
The present invention also provides a kind of array substrates, including above-mentioned pixel circuit.
The present invention also provides a kind of display panels, including above-mentioned array substrate.
The present invention also provides a kind of display devices, including above-mentioned display panel.
Compared with prior art, pixel circuit of the present invention, driving method, array substrate, display panel and display
Then device passes through data voltage control unit by the way that the second end of capacitor C to be changed to connect with the power supply line that driving capability is strong
Change the voltage for being input to the drain electrode of the thin film transistor (TFT) (TFT), so as to compensate the source of grid and TFT due to TFT
There are parasitic capacitance Cgs between pole to the fluctuation voltage △ Vp when grid line opens and closes on actual pixels, and can improve
In the prior art due to public electrode voltages are coupled and are generated display bad phenomenon.
Detailed description of the invention
Figure 1A is the structure chart of existing pixel circuit；
Figure 1B is the structure chart of pixel circuit described in the embodiment of the present invention；
Fig. 2 is the structure chart of pixel circuit described in another embodiment of the present invention；
Fig. 3 is the structure chart of pixel circuit described in further embodiment of this invention；
Fig. 4 is the structure chart of pixel circuit described in yet another embodiment of the invention；
Fig. 5 A is the circuit diagram of a specific embodiment of pixel circuit of the present invention；
Fig. 5 B is the structural schematic diagram of pixel circuit described in multiple embodiment of the present invention；
Fig. 6 is the circuit diagram for biasing gamma electric voltage loading module.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1B, pixel circuit described in the embodiment of the present invention, including (Thin Film Transistor is thin by TFT
Film transistor) and capacitor C；
The grid of the TFT is connect with grid line Gate, and the first pole of the TFT is connect with the first end of the capacitor C；
The second end of the capacitor C is connect with power supply line VL；
The pixel circuit further include:
Data voltage control unit 11, the data electricity for providing bias voltage Vb and data line (being not shown in Figure 1B)
Pressure Vdata is exported to the second pole of the TFT.
Pixel circuit described in the embodiment of the present invention at work, when the capacitor C is connect with ground wire, the biased electrical
Pressure can compensate for generating on pixel capacitance due to the parasitic capacitance between the grid of the TFT and the second pole of the TFT
Fluctuation voltage；When the capacitor C is connect with other power supply lines other than ground wire, the bias voltage and the power supply
The voltage difference of supply voltage on line can compensate for the fluctuation voltage.
In fig. ib, when the TFT is n-type transistor, the described first extremely source electrode, described second extremely drains, still
In practical operation, the TFT also may alternatively be p-type transistor, and the embodiment of the present invention does not make the type of the TFT
It limits.
In practical operation, since the second end of the capacitor C is usually to connect with public electrode wire in the prior art
, however the driving capability of public electrode wire is poor, to will lead to due to the public electrode voltages VCOM coupling on public electrode wire
Close relevant bad phenomenon.The second end of the capacitor C is changed to and voltage by pixel-driving circuit described in the embodiment of the present invention
The strong power supply line connection of driving capability, is then input to the thin film transistor (TFT) (TFT) by the change of data voltage control unit
Drain electrode voltage, so as to compensate since there are parasitic capacitance Cgs between the grid of TFT and the source electrode of TFT in grid
Fluctuation voltage △ Vp when line opens and closes on actual pixels, and can improve in the prior art since public electrode voltages are by coupling
The display bad phenomenon closed and generated.
Pixel circuit described in the embodiment of the present invention by data voltage control unit by data line data voltage and
Bias voltage Vb superposition, the positive/negative-pressure progress of data voltage is integrally-regulated up and down, it is again that the data voltage after biasing is defeated later
One end of capacitor C is arrived out, and the other end of capacitor C is grounded, the data voltage after biasing in this way is carried out directly as pixel voltage
Driving.
Pixel circuit described in the embodiment of the present invention drives pixel to light by power supply line and data line, data line and electricity
The ability of source line all far better than public electrode wire, will not cause the fluctuation of pixel voltage easily, effectively prevent greening etc. bad
Phenomenon, and at the same time, FLK (flicker degree) is adjusted, public electrode voltages write-in and pixel voltage adjusting are also very convenient.
In practice, as shown in Fig. 2, the capacitor C includes storage capacitance Cst and liquid crystal capacitance Clc parallel with one another, mark
It number is the parasitic capacitance between the grid that Cgs is TFT and the source electrode of TFT.
Specifically, as shown in figure 3, the data voltage control unit 11 respectively with data line Data, biasing voltage signal
Line PL is connected with the second pole of the TFT, the bias voltage Vb and data line Data for providing biasing voltage signal line PL
The data voltage Vdata of offer is exported to the second pole of the TFT.
Specifically, as shown in figure 4, the data voltage control unit 11 includes loading capacitance CL and loading resistor RL；
The both ends of the loading capacitance CL are connect with the second pole of the data line Data and TFT respectively；
The both ends of the loading resistor CR are connect with the second pole of the biasing voltage signal line PL and TFT respectively.
Data voltage control unit as shown in Figure 4 is before powering on, and the both ends of CL are not by access voltage signal；When data electricity
When voltage-controlled cell operation processed, the bias voltage of biasing voltage signal line PL output is exported by RL to the second pole of TFT, Vdata
The left end of CL is written, due to the boot strap of loading capacitance CL, the voltage difference at the both ends of capacitor cannot be mutated, the right end voltage of CL
Also rise Vdata, therefore the voltage exported at this time to the second pole of the TFT is Vb+Vdata.
In practical operation, the superposition of the data voltage and bias voltage Vb of data line Data output can pass through other
What possible method is realized, it is not limited to the stacking method of resistance capacitance.
Preferably, the power supply line can be ground wire.
The voltage driving capability of ground wire is strong, when the capacitor C is connect with ground wire, the bias voltage can compensate for due to
Parasitic capacitance between the grid of the TFT and the second pole of the TFT and the fluctuation voltage generated on pixel capacitance, thus
Enhance driving capability, to solve the bad phenomenons such as flashing relevant to public electrode coupling and direct current residual in the prior art.
As shown in Figure 5A, GND indicates ground wire, and solid line mark is to export when not being biased adjusting to TFT in Fig. 5 A
The voltage of second pole, dotted line mark is voltage of the output after having carried out bias-adjusted to the second pole of TFT.It can be straight by Fig. 5 A
That sees learns, the voltage of the second pole of the output after bias-adjusted to TFT and not being biased when adjusting is exported to the second of TFT
The voltage of pole has carried out the downward shift that amplitude is bias voltage Vb, offsets the unevenness of positive/negative-pressure caused by fluctuation voltage △ Vp with this
Weighing apparatus.
In figure 5B, marked as S1 ', S2 ', SN-1 ', SN ' be respectively the first data line output the first data voltage,
Second data voltage of the second data line output, the N-1 data voltage of N-1 data line output, the output of Nth data line the
N data voltage；What it is marked as OP1, OP2, OPN-1, OPN is respectively the first operational amplifier, second operational amplifier, N-1
Operational amplifier, N operational amplifier；It is the first data voltage control unit marked as 51, is the second number marked as 52
It is N-1 data voltage control unit marked as 5N-1 according to voltage control unit, is Nth data voltage control marked as 5N
Unit processed；
Label S1 is the first biased data voltage, and label S2 is the second biased data voltage, and label SN-1 is
N-1 biased data voltage, label SN are N biased data voltage；
It is the first grid line marked as Gate1, is N grid line marked as GateN；
First data voltage control unit 51 includes the first loading capacitance CL1 and the first loading resistor RL1；
Second data voltage control unit 52 includes the first loading capacitance CL2 and the first loading resistor RL2；
N-1 data voltage control unit 5N-1 includes the first loading capacitance CLN-1 and the first loading resistor RLN-1；
Nth data voltage control unit 5N includes the first loading capacitance CLN and the first loading resistor RLN；
It is the first TFT marked as T1, is the 2nd TFT marked as T2, is N-1TFT marked as TN-1, marked as
TN is NTFT；
It is storage capacitance marked as Cst, is liquid crystal capacitance marked as Clc, is ground wire marked as GND, marked as
Cgs is parasitic capacitance；Vb is bias voltage.
In figure 5B, T1 and TN is n-type transistor.
In the specific implementation, the first data voltage control unit 51 control bias voltage Vb and the first data voltage S1 ' is defeated
Out to the drain electrode of T1；
Second data voltage control unit 52 controls bias voltage Vb and the second data voltage S2 ' output to the 2nd TFT (figure
Be not shown in 5B) drain electrode；
N-1 data voltage control unit 5N-1 controls bias voltage Vb and the first data voltage SN-1 ' output to N-
The drain electrode of 1TFT；
Nth data voltage control unit 5N controls the drain electrode of bias voltage Vb and the second data voltage SN ' output to TN.
In addition, in practice, can also be compensated by adjusting the voltage value of gamma reference voltage due to TFT grid and
There are parasitic capacitance Cgs between the source electrode of TFT to the fluctuation voltage △ Vp when grid line opens and closes on actual pixels, tool
Body is as follows:
In practical operation, the gamma reference voltage generation circuit can be produced by biasing gamma voltage loading unit
Raw each original gamma reference voltage is all superimposed with corresponding biasing gamma reference voltage, obtains exporting gamma reference accordingly
Voltage, and according to the output gamma reference voltage, gray scale voltage is generated according to the output gamma reference voltage later.
For example, the number for the original gamma reference voltage that the gamma reference voltage generation circuit generates can be N number of；N
For the integer greater than 1；The biasing gamma voltage load subelement includes N number of biasing gamma voltage loading module；N-th biasing gal
Ma voltage-drop loading module connect with the n-th original gamma reference voltage output end of the gamma reference voltage generation circuit, is used for
N-th original gamma reference voltage is superimposed with the n-th biasing gamma reference voltage, obtains the n-th output gamma reference voltage, and by institute
It states the n-th output gamma reference voltage and is sent to the digital analog converter that the data drive circuit includes；N is less than or equal to N's
Positive integer.
Specifically, as shown in fig. 6, the biasing gamma electric voltage loading module may include first switch K1, second switch
K2, third switch K3, loading capacitance CL and ON-OFF control circuit (being not shown in Fig. 6)；
The first switch K1 is connected to the of the described n-th original gamma reference voltage output end and the loading capacitance CL
Between one end；The n-th original gamma reference voltage output end exports the n-th original gamma reference voltage V '；
The second switch K2 is connected to the first end connection of the loading capacitance CL and the n-th biasing gamma electric voltage adds
It carries between the n-th output gamma reference voltage output end Outn of module；The n-th output gamma reference voltage output end Outn is defeated
N-th output gamma reference voltage V out；
The third switch K3 biases Gamma reference with the second end of the loading capacitance CL, ground terminal GND and n-th respectively
Voltage input end connection；By the n-th biasing of the n-th biasing gamma reference voltage input terminal input gamma reference voltage Vb；
The ON-OFF control circuit (being not shown in Fig. 6) is opened with the control terminal of the first switch K1, described second respectively
The control terminal for closing K2 is connected with the control terminal of the third switch K3, for controlling the first switch K1 conducting in the charging stage
And the second switch K2 is disconnected, and control the third switch conduction ground terminal GND and loading capacitance CL second end it
Between connection, thus control charged by the described n-th original gamma reference voltage V ' to the loading capacitance CL, charging
After control that the first switch K1 is disconnected and the second switch K2 is connected, and control described in the third switch K3 is connected
Connection between n-th biasing gamma reference voltage input terminal and the second end of the loading capacitance CL.
As shown in fig. 6, biasing gamma electric voltage loading module is at work, first switch K1 closure, second switch K2 are realized
It disconnects, the connection of the second end of GND and CL is connected in third switch K3, and V ' charges to CL；
After charging, first switch K1 is disconnected, second switch K2 closure, and third switch K3 controls the second of Vb access CL
End, due to the bootstrapping principle of capacitor, final V=V '+Vb completes the biasing of gamma reference voltage.
In this way, the bias-adjusted more than all gamma reference voltages are carried out, according to the Gamma reference after bias-adjusted
The data voltage signal corresponding to each grayscale that voltage generates can be offset under different grayscale caused by fluctuation voltage △ Vp just
Negative pressure is unbalanced.In this case the data voltage signal Jing Guo bias-adjusted directly inputs the source electrode of pixel circuit TFT, and
Due to one end ground connection of the capacitor C of pixel circuit, the driving capability of ground wire is stronger than public electrode wire, therefore is passing through bias-adjusted
Data voltage signal can compensate for due to the parasitic capacitance between the grid of the TFT and the second pole of the TFT and in picture
While the fluctuation voltage generated on plain capacitor, it can solve in the prior art and generated since public electrode voltages are coupled
Display bad phenomenon.
The driving method of pixel circuit described in the embodiment of the present invention, applied to above-mentioned pixel circuit, the driving side
Method includes:
Data voltage control unit is by bias voltage and data voltage output to the second pole of TFT.
Pixel circuit described in the embodiment of the present invention to the second pole of TFT, will count bias voltage and data voltage output
It is integrally-regulated up and down according to the positive/negative-pressure progress of voltage, it is posted so as to compensate due to existing between the grid of TFT and the source electrode of TFT
Raw capacitor Cgs is to the fluctuation voltage △ Vp when grid line opens and closes on actual pixels.
Specifically, the driving method may include: that the data voltage control unit provides biasing voltage signal line
Bias voltage and data line provide data voltage export to the second pole of the TFT.
Array substrate described in the embodiment of the present invention includes above-mentioned pixel circuit.
Display panel described in the embodiment of the present invention includes above-mentioned array substrate.
Display device described in the embodiment of the present invention includes above-mentioned display panel.
The above is a preferred embodiment of the present invention, it is noted that for those skilled in the art
For, without departing from the principles of the present invention, it can also make several improvements and retouch, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of pixel circuit, including thin film transistor (TFT) TFT and capacitor (C)；The grid of the TFT is connect with grid line, the TFT
The first pole connect with one end of the capacitor (C)；It is characterized in that,
The other end of the capacitor (C) is connect with power supply line；
The pixel circuit further include:
Data voltage control unit, for by bias voltage and data voltage output to the second pole of the TFT；
The data voltage control unit is connect with the second pole of data line, biasing voltage signal line and the TFT respectively, is used for
The bias voltage that biasing voltage signal line provides and the data voltage that data line provides are exported to the second pole of the TFT；
The data voltage control unit includes loading capacitance and loading resistor；
The both ends of the loading capacitance are connect with the second pole of the data line and the TFT respectively；
The both ends of the loading resistor are connect with the second pole of the biasing voltage signal line and the TFT respectively.
2. pixel circuit as described in claim 1, which is characterized in that the power supply line is ground wire.
3. a kind of driving method of pixel circuit is applied to pixel circuit as claimed in claim 1 or 2, which is characterized in that institute
Stating driving method includes:
Data voltage control unit is by bias voltage and data voltage output to the second pole of TFT.
4. the driving method of pixel circuit as claimed in claim 3, which is characterized in that the driving method specifically includes: institute
State data voltage control unit by the bias voltage that biasing voltage signal line provides and the data voltage that data line provides export to
The second pole of the TFT.
5. a kind of array substrate, which is characterized in that including pixel circuit as claimed in claim 1 or 2.
6. a kind of display panel, which is characterized in that including array substrate as claimed in claim 5.
7. a kind of display device, which is characterized in that including display panel as claimed in claim 6.
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| CN201610538486.3A CN105931594B (en) | 2016-07-08 | 2016-07-08 | Pixel circuit, driving method, array substrate, display panel and display device |
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| CN201610538486.3A CN105931594B (en) | 2016-07-08 | 2016-07-08 | Pixel circuit, driving method, array substrate, display panel and display device |
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| CN105931594B true CN105931594B (en) | 2018-12-14 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI652815B (en) * | 2017-12-18 | 2019-03-01 | 友達光電股份有限公司 | Display panel |
| CN108492785B (en) * | 2018-03-30 | 2019-12-03 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit and its driving method, display device |
| CN109192163A (en) * | 2018-10-10 | 2019-01-11 | 惠科股份有限公司 | Display device and its method for eliminating shutdown ghosting image |
| CN110176214B (en) * | 2019-05-29 | 2020-11-03 | 昆山龙腾光电股份有限公司 | Pixel driving circuit and organic electroluminescent display |
| CN113345366B (en) * | 2021-06-10 | 2022-09-23 | 成都辰显光电有限公司 | Pixel driving circuit, driving method thereof and display panel |
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