CN105897253B - A kind of implementation method of non-volatile look-up table circuit - Google Patents
A kind of implementation method of non-volatile look-up table circuit Download PDFInfo
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- CN105897253B CN105897253B CN201610201319.XA CN201610201319A CN105897253B CN 105897253 B CN105897253 B CN 105897253B CN 201610201319 A CN201610201319 A CN 201610201319A CN 105897253 B CN105897253 B CN 105897253B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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Abstract
The present invention relates to a kind of implementation method of programmable gate array more particularly to a kind of implementation methods of non-volatile look-up table circuit.The output end of wordline selection control is connected to each wordline of non-volatile memory array, certain output end all the way for controlling the wordline selection control is low level, and the storage unit in the wordline of the roads Ze Yugai output end connection can be all strobed；The selection signal of multi-channel data selector is controlled by the input terminal of non-volatile look-up table circuit, and reading induction amplifier is output to the bit line and antiposition line of selection；The storage content of storage unit on the bit line chosen and antiposition line is finally read by reading induction amplifier.The present invention proposes a kind of non-volatile look-up table circuit implementing method, using the Nonvolatile storage array that programmable resistance and diode are in series, compared to tradition SRAM programmings, storage density is high, leakage current is small, and have it is non-volatile, be highly suitable for multi-context FPGA application.
Description
Technical field
The present invention relates to a kind of implementation method of programmable gate array more particularly to a kind of realizations of lut circuits
Method.
Background technology
Look-up table (Look-up table, LUT) be field programmable gate array (FPGA) main logic device it
One.N look-up tables can realize that its selection line is the defeated of LUT using multiplexer (being also multi-channel data selector)
Enter, truth table is modeled as by boolean logic function so as to encode arbitrary n-bit data.Look-up table is substantially one random
Access memory (Random Access Memory, RAM).When user describes one by schematic diagram or hardware description language
After a logical function, FPGA exploitation software can automatic calculation logic circuit it is all possible as a result, and write the result into RAM,
In this way, often inputting a signal carries out logical operation, it is equivalent to one address of input and tables look-up, find out corresponding content then
Output.What FPGA was mostly used at present is that static RAM (SRAM) carrys out storage configuration logic.Such as Fig. 1-1 institute
What is shown is a lut circuits structure having there are two input terminal, and the look-up table is in advance by all logical calculated results of A and B
It stores in sram cell, then whenever the value for inputting one group of A and B, so that it may corresponding to be selected by multi-channel data selector
Output is as a result, to realize programmable logic.The circuit structure of SRAM is as shown in Figs. 1-2, is made of six transistors, area is big
And electric leakage is severe, and SRAM is volatile memory, once power down, FPGA just needs to reprogram, very trouble and peace
Full poor performance.Multi-context (multi-context) FPGA device has more set configuration informations, and more set configuration informations can be very short
Switching is completed in time.Multi-context FPGA device of the tradition based on SRAM needs more set SRAM to program point, thus can bring more
Big area overhead and leakage power consumption.
Invention content
For the problem that leaking electricity existing for current look-up table, volatibility, the present invention provides a kind of non-volatile look-up table electricity
Road implementation method.
The technical proposal for solving the technical problem of the invention is：
A kind of implementation method of non-volatile look-up table circuit, the non-volatile look-up table circuit include：
First multi-channel data selector and the second multi-channel data selector, the input terminal for providing look-up table input,
Wordline selection control is made of multiple transistors, has multiple control terminals and corresponding with the control terminal defeated
Outlet；
Nonvolatile storage array, including wordline that multichannel is connected with the output end of the wordline selection control, with
And the storage unit being in series by programmable resistance and diode being connected with the wordline；Described in the storage unit connection
Multiple multi-channel data selectors；Wherein, the programmable resistance in the storage unit being connected with first multi-channel data selector
It is in opposite situation with the programmable resistance in the storage unit being connected with second multi-channel data selector；
Induction amplifier is read, the multi-channel data selector is connected；
The implementation method of the non-volatile look-up table circuit includes：
It is low level that the wordline selection control, which controls its first wordline, gates the storage list in first wordline
Member；
To the input terminal input signal of the multi-channel data selector, makes to choose bit line and antiposition line is chosen to be respectively communicated with institute
State a pair of of storage unit that resistance in the first wordline is in inverse state；
The reading induction amplifier by choosing bit line to described and antiposition line being chosen to provide a voltage or electric current, due to
The difference for choosing bit line and choose resistance state in coconnected a pair of of the storage unit of antiposition line, it is described to choose bit line
Different variation tendencies is also presented with the voltage or electric current chosen on antiposition line, then is read out by the induction amplifier and defeated
Go out.
Preferably, bit line and the voltage on antiposition line is chosen to be compared described choose by voltage comparator, obtained
The logical value of the output signal of the lut circuits.
Preferably, when the lut circuits are standby, the control terminal of the wordline selection control is set as low level, then
Wordline corresponding with the control terminal exports high level.
Preferably, the programmable resistance is resistance variable memory or magnetic memory or phase transition storage.
Preferably, the wordline control selections device passes through a NMOS transistor and a PMOS transistor and control terminal
To control the current potential of wordline.
A kind of implementation method of non-volatile look-up table circuit, the non-volatile look-up table circuit include：
Multi-channel data selector, the input terminal for providing look-up table input,
Match logic circuitry is realized and is delayed with the comparable RC of the multi-channel data selector；
Wordline selection control is made of multiple transistors, has multiple control terminals and corresponding with the control terminal defeated
Outlet；
Nonvolatile storage array, including wordline that multichannel is connected with the output end of the wordline selection control, with
And the multiple storage units being in series by programmable resistance and diode being connected with the wordline, the storage unit connection
The multi-channel data selector；And the ginseng being made of first resistor and Diode series being connect with the match logic circuitry
Examine storage unit, wherein the first resistor is fixed resistance, and its resistance value is between the high-impedance state of the programmable resistance and low
Between resistance state；
Induction amplifier is read, the multi-channel data selector and match logic circuitry are connected；
The implementation method of the non-volatile look-up table circuit includes：
The wordline selection control controls its second wordline and reference word line is low level, gates in second wordline
Storage unit and reference memory unit；
To the input terminal input signal of the data selector, make to choose one in the second wordline described in digit line communication to deposit
Storage unit, reference bit lines are connected to reference memory unit；
The reading induction amplifier to described by choosing bit line and reference bit lines to provide a voltage or electric current, by institute
State the difference for choosing resistance state in bit line and the coconnected storage unit of reference bit lines and reference memory unit, the choosing
Different variation tendencies is also presented in voltage or electric current on neutrality line and reference bit lines, then is read out by the induction amplifier
And it exports.
Preferably, the resistance value of the reference resistance is the resistance value of the resistance value and low resistance state of the high-impedance state of the programmable resistance
Product square root.
Preferably, the voltage on the bit line and reference bit lines is compared by voltage comparator, obtains described look into
Look for the logical value of the output signal of watch circuit.
Preferably, the reference memory unit passes through a NMOS transistor connected to it and a PMOS transistor control
Make the current potential of the reference word line.
Beneficial effects of the present invention：The present invention proposes a kind of non-volatile look-up table circuit implementing method, using
The Nonvolatile storage array that programmable resistance and diode are in series, for tradition SRAM programmings, storage density is high, leakage
Electric current is small, and have it is non-volatile, be highly suitable for multi-context FPGA application.
Description of the drawings
Fig. 1-1 is that there are two the structural schematic diagrams of the lut circuits structure of input terminal for tool；
Fig. 1-2 is the SRAM structural schematic diagrams being made of transistor；
Fig. 2 is a kind of schematic diagram of the implementation method of non-volatile look-up table circuit of the first embodiment；
Fig. 3 is a kind of schematic diagram of the implementation method of non-volatile look-up table circuit of second of embodiment.
Fig. 4 is the lut circuits structural schematic diagram of the first embodiment；
Fig. 5 is the lut circuits structural schematic diagram of second of embodiment.
Specific implementation mode
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
The present invention proposes a kind of non-volatile look-up table circuit implementing method, as shown in Figure 2.The non-volatile lookup
Watch circuit mainly comprises the following steps：Nonvolatile storage array, wordline selection control, multiple multi-channel data selectors
And read induction amplifier.Nonvolatile storage array includes multiple storage lists being in series by programmable resistance and diode
Member, and the wordline drawn from the output end of wordline selection control.Programmable resistance can be resistance-variable storing device
(ReRAM), magnetic memory (MRAM) or phase transition storage (PCRAM or PCM), they the characteristics of be by different programming sides
Method can be at high-impedance state or low resistance state.For example, phase transition storage utilizes phase-change material between crystalline state and amorphous state
Resistance value difference store data, whether magnetic memory identical by the magnetic direction between free layer and fixed bed and present high
Low resistance preserves data, and resistance variable memory stores data using variable resistor element.Programmable resistance is provided with non-
Volatibility, i.e., information is not lost after power down.
A kind of non-volatile look-up table circuit implementing method proposed by the present invention, look-up table are input to multichannel data selection
Device, by controlling a certain specific bit line and antiposition line to select the storage unit in a certain particular word line；To choosing bit line
Apply identical voltage or electric current on antiposition line with choosing, thus by the high-impedance state or low-resistance of the programmable resistance in storage unit
State is converted into logic level values.
Specifically, in lut circuits as shown in Figure 2, input signal A0 to An-1 is input to multichannel data selection
Device.Nonvolatile storage array includes multiple wordline (WL0, WL1 ... ...), and the cathode of each wordline and diode is connected to one
It rises.Storage unit in each wordline is exactly a set of configuration information.Which set configuration controlled by controlling the current potential of wordline
Information exports.Wordline number is more, and configuration information is also more.In same wordline, (BL0 to BLm-1) is connected on bit line
Programmable resistance and antiposition line on (BLb0 to BLbm-1) connection resistance be in opposite state, and pass through read induction amplification
Device converts this pair of of resistance states to logic level values.That is, 2D2R (2 diodes and 2 respectively with diode string
Connection and programmable resistance that resistance value state is opposite) unit is used for storing 1bit (bit) data.It is of the present invention non-volatile to look into
Look for table if there is n input terminal, then just needing 2n 2D2R unit, i.e. m=2n.A plurality of wordline just constitutes more sets and matches confidence
Breath, i.e. multi-context.The switching of different contexts selects control to realize by wordline.When the non-volatile look-up table electricity
When road is in standby mode, the multiple wordline (WL0, WL1 ... ...) should be at high level, and the non-volatile is made to store
Diode in array is in reverse blocking state, to make leakage power be preferably minimized.When needing to select some wordline
(certain a set of configuration information) just makes the wordline be reduced to low level, and to make the diode forward in wordline be connected, remaining wordline is still
Corresponding bit line (BL0 to BLm-1) and antiposition line (BLb0 to BLbm-1) are poured into high level state, then by program current,
It is high-impedance state or low resistance state to make programmable resistance, to realize the programming to the programmable resistance.In addition, being shown in Fig. 2
A kind of implementation method for having shown the wordline selection control module, that is, pass through NMOS and PMOS transistor and control
(CEN_0, CEN_1 ... ...) is held to control word line potential.
Further, in order to improve storage density, 2D2R storage units can be improved to 1D1R arrays, as shown in Figure 3
Second of embodiment, the non-volatile memory array include the storage unit of half and a reference memory unit in only Fig. 2.Ginseng
The resistance value for examining resistance in storage unit is fixed and a resistance value between programmable resistance high-impedance state and low resistance state.Pass through ginseng
Bit line is examined with the difference of voltage or electric current on bit line to read correct logical value.The effect of matching logic is for match bit
The RC retardation ratio brought by multi-channel data selector on line, under the action of matching logic, the RC retardation ratio in reference bit lines and bit line
On RC retardation ratio can it is roughly the same, to improve read data accuracy.Remaining of non-volatile look-up table shown in Fig. 3
Control and reading method are similar to the above, and details are not described herein again.
Specific embodiment one：
For a further understanding of the implementation method of this non-volatile look-up table circuit of the present invention, specific embodiment is named
One is further elaborated, as shown in Figure 4.It is shown in Fig. 4 be first embodiment two input lut circuits, input terminal it is defeated
It is that input signal A's and input signal B negate signal that enter signal, which be A and B, wherein A and B,.Signal CLK and signal CLK_D is to read
Go out the clock control signal of induction amplifier.Assuming that the storage unit in selection WL1 wordline is exported, then control word is arranged
The CEN_0 control terminals of line options controller are low level, and CEN_1 control terminals are high level.Then WL0 wordline is clamped at high electricity
It is flat, therefore the storage unit being connect with WL0 wordline can be all not selected because of the reversed cut-off of diode；And WL1 wordline quilts
It is pulled down to low level, the storage unit being connected with WL1 wordline can be selected because of the forward conduction of diode.Assuming that a certain
Moment, input signal A=" 1 ", input signal B=" 0 ", then the current path such as the dotted line in Fig. 4 of multi-channel data selector
Shown in arrow, electric current passes through storage unit C1 and storage unit C2 respectively.Induction amplifier is read first to save SA nodes and SB
Point carries out charging to identical level, then discharges.Wherein, SA nodes are equivalent to the bit line of choosing in Fig. 2, SB node phases
When in choosing antiposition line.Since the resistance value of storage unit C1 and storage unit C2 are in opposite configuration so that in discharge process
Different trend is presented in SA nodes and the variation of SB node voltages, then by voltage comparator to choosing on bit line and reference bit lines
Voltage is compared, and can read the storage content in storage unit C1 and storage unit C2, and from output port out and output
Port outb is exported.In this example, if resistance is high-impedance state in storage unit C1, resistance is low-resistance in storage unit C2
State, then the voltage of SA nodes is higher than the voltage of SB nodes in discharge process, then the output port out of voltage comparator is patrolled
It is " 0 " to collect value, and the logical value of output port outb is " 1 "；If the resistance in storage unit C1 is low resistance state, storage unit C2
Middle resistance is high-impedance state, then the node voltage in discharge process interior joint SA is less than the voltage of node SB, then voltage comparator
The logical value of output port out is " 1 ", and the logical value of output port outb is " 0 ".
Specific embodiment two：
The lut circuits structural schematic diagram of second embodiment as shown in Fig. 5, this circuit structure storage density is more
Height, difference lies in the storage unit that the non-volatile memory array only has half in Fig. 4 adds a reference storage single again with Fig. 4
First Cref.The resistance value of resistance is fixed and one between programmable resistance high-impedance state and low resistance state in reference memory unit Cref
A resistance value.Such as the high value of programmable resistance is RH, the low resistance of programmable resistance is RL, then reference resistance RrefResistance value one
As may be set to RHAnd RLLong-pending square root.Match logic circuitry is realized to be delayed with the roughly the same RC of multi-channel data selector.
Assuming that a certain moment, input terminal input signal A=" 1 ", input signal B=" 1 ", then bit line is chosen to pass through storage unit C3,
And the reference bit lines chosen pass through reference memory unit Cref, in current path such as Fig. 5 shown in dotted arrow.Read induction amplification
Device is equally first to carry out charging to identical level to SA nodes and SB nodes, is then discharged, due to storage unit C3 and
The difference of reference memory unit Cref resistance values so that the voltage change of SA nodes and SB nodes is presented different in discharge process
Trend, then the content stored in a certain storage unit in storage unit C3 can be read by voltage comparator, and from output end
Mouth out and output port outb is exported.In this example, if the resistance of a certain storage unit is high resistant in storage unit C3
State, then SA node voltages are higher than SB nodes in discharge process, then the logical value of voltage comparator output port out is " 0 ",
The logical value of output port outb is " 1 "；If resistance is low resistance state, the SA nodes in discharge process in storage unit C3
Voltage is less than SB nodes, and the logical value of voltage comparator output port out is " 1 ", and the logical value of output port outb is " 0 ".
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that and all be made with description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (9)
1. a kind of implementation method of non-volatile look-up table circuit, which is characterized in that the non-volatile look-up table circuit includes：
First multi-channel data selector and the second multi-channel data selector, for providing an input terminal to lut circuits；
Wordline selection control is made of multiple transistors, has multiple control terminals and output end corresponding with the control terminal；
Nonvolatile storage array, including wordline that multichannel is connected with the output end of the wordline selection control, Yi Jiyu
The storage unit being in series by programmable resistance and diode that the wordline is connected；The storage unit connection is the multiple
Multi-channel data selector；Wherein, programmable resistance in the storage unit being connected with first multi-channel data selector with
Programmable resistance in the connected storage unit of second multi-channel data selector is in opposite situation；
Induction amplifier is read, the multi-channel data selector is connected；
The implementation method of the non-volatile look-up table circuit includes：
It is low level that the wordline selection control, which controls its first wordline, gates the storage unit in first wordline；
To the input terminal input signal of the multi-channel data selector, makes to choose bit line and antiposition line is chosen to be respectively communicated with described the
Resistance is in a pair of of storage unit of inverse state in one wordline；
The reading induction amplifier to described by choosing bit line and antiposition line being chosen to provide a voltage or electric current, due to described
It chooses bit line and chooses the difference of resistance state in coconnected a pair of of the storage unit of antiposition line, it is described to choose bit line and choosing
Different variation tendencies is also presented in voltage or electric current on middle antiposition line, then is read out and is exported by the induction amplifier.
2. the implementation method of non-volatile look-up table circuit according to claim 1, which is characterized in that compared by voltage
Device bit line and chooses the voltage on antiposition line to be compared described choose, and obtains patrolling for the output signal of the lut circuits
Collect value.
3. the implementation method of non-volatile look-up table circuit according to claim 1, which is characterized in that the look-up table electricity
When road is standby, the control terminal of the wordline selection control is set as low level, then wordline output corresponding with the control terminal
High level.
4. the implementation method of non-volatile look-up table circuit according to claim 1, which is characterized in that the programmable electricity
Resistance is resistance variable memory or magnetic memory or phase transition storage.
5. the implementation method of non-volatile look-up table circuit according to claim 1, which is characterized in that the wordline control
Selector controls the current potential of wordline by a NMOS transistor and a PMOS transistor and control terminal.
6. a kind of implementation method of non-volatile look-up table circuit, which is characterized in that the non-volatile look-up table circuit includes：
Multi-channel data selector, for providing an input terminal to lut circuits；
Match logic circuitry is realized and is delayed with the comparable RC of the multi-channel data selector；
Nonvolatile storage array, including wordline that multichannel is connected with the output end of wordline selection control, and with it is described
Multiple storage units being in series by programmable resistance and diode that wordline is connected, the storage unit connect the multichannel
Data selector；And the reference storage being made of first resistor and Diode series being connect with the match logic circuitry is single
Member, wherein the first resistor be fixed resistance, and its resistance value between the programmable resistance high-impedance state and low resistance state it
Between；
Induction amplifier is read, the multi-channel data selector and match logic circuitry are connected；
The wordline selection control controls its second wordline and reference word line is low level, gates depositing in second wordline
Storage unit and reference memory unit；
To the input terminal input signal of the multi-channel data selector, make to choose one in the second wordline described in digit line communication to deposit
Storage unit, reference bit lines are connected to reference memory unit；
The reading induction amplifier to described by choosing bit line and reference bit lines to provide a voltage or electric current, due to the choosing
The difference of resistance state, the selected bit in neutrality line and the coconnected storage unit of reference bit lines and reference memory unit
Different variation tendencies is also presented in voltage or electric current on line and reference bit lines, then is read out by the induction amplifier and defeated
Go out.
7. the implementation method of non-volatile look-up table circuit according to claim 6, which is characterized in that the reference resistance
Resistance value be the programmable resistance high-impedance state resistance value and low resistance state resistance value product square root.
8. the implementation method of non-volatile look-up table circuit according to claim 6, which is characterized in that compared by voltage
Device is compared the voltage in the bit line and reference bit lines, obtains the logical value of the output signal of the lut circuits.
9. the implementation method of non-volatile look-up table circuit according to claim 6, which is characterized in that described with reference to storage
Unit controls the current potential of the reference word line by a NMOS transistor connected to it and a PMOS transistor.
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| CN108898216A (en) * | 2018-05-04 | 2018-11-27 | 中国科学院计算技术研究所 | Activation processing unit applied to neural network |
| CN112597733B (en) * | 2020-12-30 | 2022-07-15 | 北京华大九天科技股份有限公司 | Storage unit identification method and device and computer readable storage medium |
| CN112543022A (en) * | 2021-01-26 | 2021-03-23 | 兰州大学 | Basic logic operation unit circuit |
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|---|---|---|---|---|
| CN101042933A (en) * | 2007-04-12 | 2007-09-26 | 复旦大学 | Non-volatilization SRAM with metallic oxide as storage medium and uses thereof |
| CN101097778A (en) * | 2007-06-21 | 2008-01-02 | 复旦大学 | Metallic oxide storage medium based programming unit multiplexed FPGA device |
| CN103247342A (en) * | 2013-04-17 | 2013-08-14 | 上海新储集成电路有限公司 | Non-volatilization lookup table circuit based on phase-changing storage unit and working method circuit |
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| US8917534B2 (en) * | 2011-09-09 | 2014-12-23 | Intel Corporation | Path isolation in a memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101042933A (en) * | 2007-04-12 | 2007-09-26 | 复旦大学 | Non-volatilization SRAM with metallic oxide as storage medium and uses thereof |
| CN101097778A (en) * | 2007-06-21 | 2008-01-02 | 复旦大学 | Metallic oxide storage medium based programming unit multiplexed FPGA device |
| CN103247342A (en) * | 2013-04-17 | 2013-08-14 | 上海新储集成电路有限公司 | Non-volatilization lookup table circuit based on phase-changing storage unit and working method circuit |
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