CN103247342A - Non-volatilization lookup table circuit based on phase-changing storage unit and working method circuit - Google Patents
Non-volatilization lookup table circuit based on phase-changing storage unit and working method circuit Download PDFInfo
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- CN103247342A CN103247342A CN2013101339193A CN201310133919A CN103247342A CN 103247342 A CN103247342 A CN 103247342A CN 2013101339193 A CN2013101339193 A CN 2013101339193A CN 201310133919 A CN201310133919 A CN 201310133919A CN 103247342 A CN103247342 A CN 103247342A
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Abstract
The invention discloses a non-volatilization lookup table circuit based on a phase-changing storage unit. The non-volatilization lookup table circuit comprises a non-volatilization storage unit array as well as a programming unit, a decoding unit and an output unit, which are respectively connected with the non-volatilization storage unit array; the non-volatilization storage unit array comprises a phase-changing storage unit, and the programming unit changes the impedance state of the phase-changing storage unit in the non-volatilization storage unit array to write the data; and the decoding unit selects and conducts the phase-changing storage unit to be looked up in the non-volatilization storage unit array, the conducted current generates different voltage signals according to the impedance state of the phase-changing storage unit and outputs the different voltage signals through the output unit, so that the data in the non-volatilization storage unit array is read. The invention also discloses a working method of the non-volatilization lookup table circuit based on the phase-changing storage unit. The non-volatilization lookup table circuit has a power failure protection function, and the data of the lookup table can be configured without an additional chip.
Description
Technical field
The present invention relates to a kind of integrated circuit, especially relate to a kind of non-volatile lut circuits and method of work thereof based on phase-change memory cell.
Background technology
Non-volatile look-up table (Look-Up-Table) abbreviates the critical piece that LUT is programmable logic device (PLD) (PLD) and field programmable gate array (FPGA) as.Mainly finish following function: the combination function of 1, carrying out an input.2, how complicated no matter import, one four input LUT always carries out input less than 4 or equals 4 function performance.3, the logical function in the address input select storage unit.4, the complexity of LUT increases greatly with the change of input quantity.The essence of LUT is exactly a RAM, after it writes RAM to data in advance, tables look-up whenever signal of input just equals to import an address, finds out the content of address correspondence, then output.Each LUT uses the LUT of four inputs at present among the FPGA, so can regard a RAM that the 16xl of four bit address lines is arranged as more.When the user by schematic diagram or HDL language description after logical circuit, PLD/FPGA develops software and understands all possible result of automatic calculation logic circuit, and the result write RAM in advance, like this, signal of every input carries out logical operation and just equals to import an address and table look-up, find out the content of address correspondence, export corresponding logic operation result then.Because LUT mainly is fit to the SRAM explained hereafter, so present most of FPGA is based on SRAM technology, and the chip of SRAM technology information after power down will be lost, so must add a slice specialized configuration chip, when powering on, by this specialized configuration chip data are loaded among the FPGA.
Summary of the invention
The present invention has overcome in the prior art information dropout after the power down, configuring chip need additionally be set, chip area is big, be difficult to realize the defective such as extensive integrated of lut circuits and configuring chip, has proposed a kind of non-volatile lut circuits and method of work thereof based on phase-change memory cell.
A kind of non-volatile lut circuits based on phase-change memory cell that the present invention proposes comprises:
The nonvolatile memory cell array, and
Programming unit, decoding unit and the output unit that is connected with described nonvolatile memory cell array respectively;
Wherein, comprise an above phase-change memory cell in the described nonvolatile memory cell array,
The resistance state that described programming unit changes phase-change memory cell in the described nonvolatile memory cell array realizes writing data; Phase-change memory cell in the described nonvolatile memory cell array that described decoding unit is selected and conducting is to be found, the electric current of conducting generates the signal of different voltages and by described output unit output, realizes reading the data in the described nonvolatile memory cell array according to the resistance state of described phase-change memory cell.
Wherein, described nonvolatile memory cell array further comprises the gate transistor array; Described phase-change memory cell is connected with described decoding unit by described gate transistor array; Described decoding unit select with the described gate transistor array of conducting in different transistor realize selecting and the described phase-change memory cell of conducting.
Wherein, described programming unit transmits program current to the phase-change memory cell in the described nonvolatile memory cell, and described phase-change memory cell is made as high-impedance state or low resistance state, realizes the programming to described phase-change memory cell.
The method of work of a kind of non-volatile lut circuits based on phase-change memory cell that the present invention also proposes comprises programming phases and fetch phase; Described programming phases realizes writing data to described nonvolatile memory cell array, and described fetch phase is realized reading data from described nonvolatile memory cell array.
Wherein, described programming phases may further comprise the steps:
Steps A 1: described decoding unit is selected phase-change memory cell to be programmed by described gate transistor array;
Steps A 2: described programming unit is made as high-impedance state or low resistance state to described phase-change memory cell to be programmed transmission program current with described phase-change memory cell to be programmed.
Wherein, further comprise:
Steps A 3: repeat described steps A 1 to steps A 2, stop after all phase-change memory cells are programmed in to described nonvolatile memory cell array.
Wherein, described fetch phase may further comprise the steps:
Step B1: described decoding unit is selected phase-change memory cell to be read by described gate transistor array;
Step B2: described output unit reads data and output from described phase-change memory cell to be read.
Wherein, further comprise:
Step B3: repeat described step B1 to step B2, the data of all phase-change memory cells and output back stop in reading described nonvolatile memory cell array.
The non-volatile power transformation road of searching based on phase-change memory cell of the present invention, both can realize the function based on the non-volatile lut circuits of SRAM, but also have the power down hold facility, and need not to place again flash chip or onboard flash memory storer, finish the data initialization to SRAM.
Utilize that the present invention proposes to search programmable logic device (PLD) or field programmable gate array chip area that the power transformation road constitutes littler, structure is simpler, and with standard logic CMOS process compatible, be easy to realize integrated on a large scale.
Description of drawings
Fig. 1 is based on the synoptic diagram of the non-volatile lut circuits of phase-change memory cell.
Fig. 2 imports non-volatile lut circuits figure based on two of phase-change memory cell among one embodiment.
Fig. 3 is the process flow diagram of programming phases.
Fig. 4 is the process flow diagram of fetch phase.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail.Implement process of the present invention, condition, experimental technique etc., except the following content of mentioning specially, be universal knowledege and the common practise of this area, the present invention is not particularly limited content.
The synoptic diagram of the non-volatile lut circuits that is based on phase-change memory cell that Fig. 1 shows.Non-volatile lut circuits based on phase-change memory cell of the present invention comprises: nonvolatile memory cell array 3, programming unit, decoding unit 1 and output unit 2.Comprise a plurality of phase-change memory cells in the nonvolatile memory cell array 3, phase-change memory cell has power-down protection, can keep data under the situation of power down.Programming unit is connected with nonvolatile memory cell array 3, programming unit is carried program current to phase-change memory cell wherein, phase-change memory cell changes its state under the influence of program current be high-impedance state or low resistance state, finish that data are write preservation in the nonvolatile memory cell array 3, realize the programming operation to nonvolatile memory cell array 3.Output unit 2 is connected with nonvolatile memory cell array 3, and output unit 2 reads the data of phase-change memory cell from nonvolatile memory cell array 3, and the data that read are exported.Decoding unit 1 is connected with nonvolatile memory cell array 3, realizes selecting wherein different phase-change memory cells.Particularly, also comprise the gate transistor array in the nonvolatile memory cell array 3, decoding unit 1 is connected with transistor in the gate transistor array, decoding unit 1 is according to the different transistor of signal conduction of input, thereby gating and the circuit that different phase-change memory cell connects realize selecting different phase-change memory cells.
What Fig. 2 showed is to import non-volatile lut circuits figure based on two of phase-change memory cell among the embodiment.Comprise non-volatile phase-change memory cell GSTO-GST3 in the nonvolatile memory cell array 3, and the gate transistor array that is connected with phase-change memory cell.Comprise NMOS gate tube NAO-NA3 and NMOS gate tube NBO-NB3 in the gate transistor array.Wherein, NMOS gate tube NAO and NMOS gate tube NBO and phase-change memory cell GSTO are connected in series.Similarly, other phase-change memory cells are connected in series with corresponding NMOS gate tube respectively.Comprise input end A and input end B in the decoding unit 1, and two phase inverter INVA, INVB.Input end A and input end B are divided into two paths of signals and transmit.The road signal of input end A is connected with NMOS gate tube NA1 and NMOS gate tube NA3 respectively, and another road signal is connected with NMOS gate tube NAO and NMOS gate tube NA2 respectively by phase inverter INVA.Similarly, the road signal of input end B is connected with NMOS gate tube NB2 and NMOS gate tube NB3 respectively, and another road signal is connected with NMOS gate tube NBO and NMOS gate tube NB1 respectively by phase inverter INVB.
Present embodiment is by the function of circuit realization programming unit, and for example an end of nonvolatile memory cell array 3 is connected with programming power supply I by PMOS pipe P1, and by NMOS pipe N1 ground connection.The other end of nonvolatile memory cell array 3 is connected with programming power supply II by PMOS pipe P2, and by NMOS pipe N2 ground connection.Input end D is connected with Sheffer stroke gate 4, and is connected with Sheffer stroke gate 5 by not gate.Input Enable Pin WE is connected with Sheffer stroke gate 4 and Sheffer stroke gate 5 respectively.Sheffer stroke gate 4 is connected with PMOS pipe P1 and NMOS pipe N1, and is connected with NMOS pipe N2 by phase inverter INV1.Sheffer stroke gate 5 is connected with PMOS pipe P2.It is effective that input end D and input Enable Pin WE are high level.
Draw PMOS transistor P3 and output terminal Y on a little less than output unit 2 comprises.Output terminal Y is connected with the other end of nonvolatile memory cell array 3 by phase inverter INV2.Draw PMOS transistor P3 to be connected with the input end of reading power supply, read Enable Pin RDB and phase inverter INV2 respectively on weak.
Method of work based on the non-volatile lut circuits of phase-change memory cell comprises two stages: programming phases and fetch phase.
What Fig. 3 showed is the process flow diagram of programming phases.Programming phases is preserved by phase-change memory cell by writing data to nonvolatile memory cell array 3.Because phase-change memory cell can keep data under the situation of power down, so do not need the chip of additional configuration special use that data are loaded among the FPGA.In programming phases, at first select phase-change memory cell to be programmed in the nonvolatile memory cell array 3 by decoding unit 1, the circuit that connects by its this phase-change memory cell of gate transistor array gating.Transmit program current by programming unit to this phase-change memory cell again, phase-change memory cell is set to high-impedance state or low resistance state under the influence of program current, thereby reach the purpose to the phase-change memory cell programming, also can keep high-impedance state or low resistance state even this phase-change memory cell is programmed power down afterwards.Programme for each phase-change memory cell in the nonvolatile memory cell array 3, finish the data configuration of non-volatile look-up table.
For example, according to the non-volatile lut circuits among Fig. 2, make input Enable Pin WE and read Enable Pin RDB and put high level, be i.e. WE=1, RDB=1.When input end D=1, Sheffer stroke gate 4 is output as 0, PMOS pipe P1 conducting, and NMOS pipe N1 closes, NMOS pipe N2 conducting; Sheffer stroke gate 5 is output as 1, PMOS pipe P2 and closes, and draws PMOS pipe P3 to close on weak.As if the input end A=0 of decoding unit 1 this moment, input end B=0, transmission NMOS pipe NAO and NBO conducting, phase-change memory cell GSTO is selected, and program current I manages P1 successively through phase-change memory cell GSTO by PMOS, NMOS gate tube NAO, NMOS gate tube NBO, NMOS pipe N2 is to ground.By voltage waveform or the NAO of control programming power supply I, the grid voltage waveform of NBO makes the GSTO phase-change memory cell be programmed to low resistance state " 1 ".
When input end D=0, Sheffer stroke gate 4 is output as 1, PMOS pipe P1 and closes, NMOS pipe N1 conducting, and NMOS pipe N2 closes.Sheffer stroke gate 5 is output as 0, PMOS pipe P2 conducting.Draw PMOS pipe P3 to close on weak.
As if A=0 this moment, B=0, transmission NMOS pipe NAO and NBO conducting, phase-change memory cell GSTO is selected, and program current II manages P2 through NBO by PMOS, NAO, GSTO, N1 arrives ground.By voltage waveform or the NAO of control programming power supply II, the grid voltage waveform of NBO makes the GSTO phase-change memory cell be programmed to high-impedance state " 0 ".
With four combinations " 00 " of B, two inputs of A, " 01 ", " 10 ", " 11 " write data " 1 " respectively, and " 0 ", " 0 ", " 1 " they are example, the state after each key control signal state and four phase-change memory cells are programmed is as shown in table 1.Because the data that the characteristic of phase-change memory cell is written into still can be saved under the situation of power down.
Table 1 control signal state and phase-change memory cell state
| RDN | WE | D | B | A | GST0 | GST1 | GST2 | |
| 1 | 1 | 1 | 0 | 0 | Low-resistance | ? | ? | ? |
| 1 | 1 | 0 | 0 | 1 | ? | High resistant | ? | ? |
| 1 | 1 | 0 | 1 | 0 | ? | ? | High resistant | ? |
| 1 | 1 | 1 | 1 | 1 | ? | ? | ? | Low-resistance |
What Fig. 4 showed is the process flow diagram of fetch phase.Fetch phase is by reading data to output unit 2 from nonvolatile memory cell array 3.In fetch phase, at first select phase-change memory cell to be read in the nonvolatile memory cell array 3 by decoding unit 1, the circuit that connects by its this phase-change memory cell of gate transistor array gating.Read data by output unit 2 from this phase-change memory cell again, and reach the purpose of the data of preserving in the output phase-change memory cell.
For example, according to the non-volatile lut circuits among Fig. 2, make input Enable Pin WE and read Enable Pin RDB and put low level, be i.e. WE=0, RDB=0.No matter what value D gets, Sheffer stroke gate 4 and Sheffer stroke gate 5 are 1.This moment, PMOS pipe P1 and P2 closed, and NMOS pipe N1 opens, and N2 closes, and drew PMOS pipe P3 to open on weak.
Work as A=0, during B=0, transmission NMOS pipe NAO and NBO open, described when as above LUT writes data among the embodiment, if this moment, GSTO was low resistance state " 1 ", owing to draw ability very weak on the PMOS pipe P3, phase inverter INV2 output this moment high level " 1 " is so the data that are kept among the GSTO are read.Sense data is with to write data in full accord.
With four combinations " 00 " of B, two inputs of A, " 01 ", " 10 ", " 11 " sense data respectively are example, and the state of each key control signal state, four phase-change memory cells and the result of sense data are as shown in table 2.As seen the data that write before this (seeing Table 1) " 1 ", " 0 ", " 0 ", (seeing Table 2) can normally be read and be exported in " 1 ".
Each key control signal state of table 2, the state of four phase-change memory cells and the result of sense data
| RDN | WE | B | A | GST0 | GST1 | GST2 | GST3 | Y |
| 0 | 0 | 0 | 0 | Low-resistance | ? | ? | ? | 1 |
| 0 | 0 | 0 | 1 | ? | High resistant | ? | ? | 0 |
| 0 | 0 | 1 | 0 | ? | ? | High resistant | ? | 0 |
| 0 | 0 | 1 | 1 | ? | ? | ? | Low- |
1 |
In sum, the non-volatile power transformation road of searching based on phase-change memory cell by specific embodiment the present invention proposition, both can realize the function based on the non-volatile lut circuits of SRAM, but also has the power down hold facility, need not to place again flash chip or onboard flash memory storer, finish the data initialization to SRAM.Programmable logic device (PLD) or the field programmable gate array chip area of the searching power transformation road formation that utilize the present invention to propose are littler, and structure is simpler.
Protection content of the present invention is not limited to above embodiment.Under the spirit and scope that do not deviate from inventive concept, variation and advantage that those skilled in the art can expect all are included in the present invention, and are protection domain with the appending claims.
Claims (8)
1. the non-volatile lut circuits based on phase-change memory cell is characterized in that, comprising:
The nonvolatile memory cell array, and
Programming unit, decoding unit and the output unit that is connected with described nonvolatile memory cell array respectively;
Wherein, comprise an above phase-change memory cell in the described nonvolatile memory cell array,
The resistance state that described programming unit changes phase-change memory cell in the described nonvolatile memory cell array realizes writing data; Phase-change memory cell in the described nonvolatile memory cell array that described decoding unit is selected and conducting is to be found, the electric current of conducting generates the signal of different voltages and by described output unit output, realizes reading the data in the described nonvolatile memory cell array according to the resistance state of described phase-change memory cell.
2. the non-volatile lut circuits based on phase-change memory cell as claimed in claim 1 is characterized in that, described nonvolatile memory cell array further comprises the gate transistor array; Described phase-change memory cell is connected with described decoding unit by described gate transistor array; Described decoding unit select with the described gate transistor array of conducting in different transistor realize selecting and the described phase-change memory cell of conducting.
3. the non-volatile lut circuits based on phase-change memory cell as claimed in claim 1, it is characterized in that, described programming unit transmits program current to the phase-change memory cell in the described nonvolatile memory cell, described phase-change memory cell is made as high-impedance state or low resistance state, realizes the programming to described phase-change memory cell.
4. the method for work based on the non-volatile lut circuits of phase-change memory cell is characterized in that, comprises programming phases and fetch phase; Described programming phases realizes writing data to described nonvolatile memory cell array, and described fetch phase is realized reading data from described nonvolatile memory cell array.
5. the method for work of the non-volatile lut circuits based on phase-change memory cell as claimed in claim 4 is characterized in that described programming phases may further comprise the steps:
Steps A 1: described decoding unit is selected phase-change memory cell to be programmed by described gate transistor array;
Steps A 2: described programming unit is made as high-impedance state or low resistance state to described phase-change memory cell to be programmed transmission program current with described phase-change memory cell to be programmed.
6. the method for work of the non-volatile lut circuits based on phase-change memory cell as claimed in claim 5, it is characterized in that, described programming phases further comprises steps A 3: repeat described steps A 1 to steps A 2, stop after all phase-change memory cells are programmed in to described nonvolatile memory cell array.
7. the method for work of the non-volatile lut circuits based on phase-change memory cell as claimed in claim 4 is characterized in that described fetch phase may further comprise the steps:
Step B1: described decoding unit is selected phase-change memory cell to be read by described gate transistor array;
Step B2: described output unit reads data and output from described phase-change memory cell to be read.
8. the method for work of the non-volatile lut circuits based on phase-change memory cell as claimed in claim 7 is characterized in that described fetch phase further comprises:
Step B3: repeat described step B1 to step B2, the data of all phase-change memory cells and output back stop in reading described nonvolatile memory cell array.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105845174A (en) * | 2015-01-12 | 2016-08-10 | 上海新储集成电路有限公司 | Nonvolatile look-up table memory cell composition and implementation method of look-up table circuit |
| CN105897253A (en) * | 2016-04-01 | 2016-08-24 | 上海新储集成电路有限公司 | Realization method of nonvolatile look-up table circuit |
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| US20070146012A1 (en) * | 2005-11-03 | 2007-06-28 | Cswitch Corp. A California Corporation | Reconfigurable logic structures |
| CN101042933A (en) * | 2007-04-12 | 2007-09-26 | 复旦大学 | Non-volatilization SRAM with metallic oxide as storage medium and uses thereof |
| WO2013036244A1 (en) * | 2011-09-09 | 2013-03-14 | Intel Corporation | Path isolation in a memory device |
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| US20070146012A1 (en) * | 2005-11-03 | 2007-06-28 | Cswitch Corp. A California Corporation | Reconfigurable logic structures |
| CN101042933A (en) * | 2007-04-12 | 2007-09-26 | 复旦大学 | Non-volatilization SRAM with metallic oxide as storage medium and uses thereof |
| WO2013036244A1 (en) * | 2011-09-09 | 2013-03-14 | Intel Corporation | Path isolation in a memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105845174A (en) * | 2015-01-12 | 2016-08-10 | 上海新储集成电路有限公司 | Nonvolatile look-up table memory cell composition and implementation method of look-up table circuit |
| CN105897253A (en) * | 2016-04-01 | 2016-08-24 | 上海新储集成电路有限公司 | Realization method of nonvolatile look-up table circuit |
| CN105897253B (en) * | 2016-04-01 | 2018-10-23 | 上海新储集成电路有限公司 | A kind of implementation method of non-volatile look-up table circuit |
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Application publication date: 20130814 |