CN105893328A - Cooley-Tukey-based fast Fourier transform (FFT) algorithm - Google Patents

Abstract

The invention discloses a Cooley-Tukey-based fast Fourier transform (FFT) algorithm. The Cooley-Tukey-based FFT algorithm utilizes a field programmable gate array (FPGA) chip and adopts Radix-4 dish operation to decompose N-point FFT into one or more short sequence FFTs. The Cooley-Tukey-based FFT algorithm decomposes the N-point FFT into the several short sequence FFTs, thus greatly reducing times of complex multiplication; by adopting the Radix-4 dish operation, the Cooley-Tukey-based FFT algorithm solves the problems of long computation delay and slow dynamic response speed; furthermore, the Cooley-Tukey-based FFT algorithm is realized by utilizing the rich logical resources of FPGA, thus solving the problem of occupying a large space of a random-access memory (RAM).

Description

A kind of fft algorithm based on Cooley-Tukey

Technical field

The present invention relates to Measurement of Harmonics in Power System field, especially with fpga chip realize based on Cooley- The fft algorithm of Tukey.

Background technology

Fft algorithm is widely used in Harmonious Waves in Power Systems current detecting field, and conventional harmonic current detecting method is profit Use traditional FFT algorithm detection harmonic current with dsp chip, but traditional method exists computation delay length, dynamic responding speed Slowly the problem that, computational accuracy is the highest, take a large amount of ram space.

Summary of the invention

The technical problem to be solved in the present invention is existing fft algorithm computation delay length, dynamic responding speed is slow, calculate essence Spend the highest, take a large amount of ram space.

For solving above-mentioned technical problem, the technical solution used in the present invention is: a kind of FFT based on Cooley-Tukey calculates Method, utilizes fpga chip, uses the dish-shaped computing of Radix-4, N point FFT is resolved into the FFT, N=of more than one short sequence R1*r2, comprises the following steps: step 1: x (n) is rewritten into x (n1, n0), utilizes x (n)=x (r₂n₁+n₀)=x (n₁,n₀),Step 2: be the FFT of r2 r1 point, obtains X1 (k0, n0)； k₀=0,1 ..., r₁-1；Step 3: N number of X1 (k0, n0) is multiplied by corresponding twiddle factorComposition X1 ' (k0, n0)；Step 4: be r1 r2 point FFT, obtain X2 (k0, k1)； k₁=0,1 ..., r₂-1；Step 5: carry out whole sequence, obtains X (k1, k0)=X (k), wherein k=r1*k1+k0；X(k₁,k₀)=X₂ (k₀,k₁)。

Traditional FFT method, answering of N point FFT takes advantage of number of times to be equal to N², amount of calculation is the hugest, computation delay length, dynamic response Speed is slow；Use the fft algorithm of Cooley-Tukey, the FFT that N point FFT is resolved into several shorter sequence, can make to take advantage of number of times again Greatly reduce；Fft algorithm based on Cooley-Tukey uses the dish-shaped computing of Radix-4 to be achieved in the design, phase Traditional Radix-2 dish computing is greatly reduced at operation times and having had on operation time.

Further, in step 4, twiddle factorWith vector e^jθThe form performance of=cos θ+jsin θ, with look-up table side Formula realizes vector rotation operation；This vector real part and imaginary part store in a register, and be only stored in 1/8 circle in, i.e.Between twiddle factor；According to periodicity and the symmetry of twiddle factor, by exchange real part imaginary part and change sign Obtain other twiddle factor.In the design, twiddle factor is only stored in 1/8 circle, greatly reduces the memory space of RAM.

The advantage that the present invention carries is: use the fft algorithm of Cooley-Tukey, N point FFT is resolved into several shorter sequence FFT, greatly reduce and take advantage of number of times again；Use the dish-shaped computing of Radix-4, solve computation delay length, dynamic responding speed slow Problem, and utilize FPGA to enrich logical resource to realize, solve the problem taking a large amount of ram space.

Accompanying drawing explanation

Fig. 1 is the dish-shaped computing schematic diagram of Radix-4.

Fig. 2 is complex adder structural representation.

Fig. 3 is complex subtraction device structural representation.

Fig. 4 is complex multiplier structural representation.

Fig. 5 be twiddle factor choose schematic diagram.

Fig. 6 be the inventive method realize block diagram.

Fig. 7 is the design diagram of butterfly unit of the present invention.

Detailed description of the invention

The present invention is further illustrated below in conjunction with the accompanying drawings.

Traditional FFT method, answering of N point FFT takes advantage of number of times to be equal to N², amount of calculation is the hugest, computation delay length, dynamic response Speed is slow；Use the fft algorithm of Cooley-Tukey, the FFT that N point FFT is resolved into several shorter sequence, can make to take advantage of number of times again Greatly reduce, such as, N point FFT is resolved into twoPoint FFT, takes advantage of number of times to be reduced to the most again

Here with assuming to carry out the dimensional Co oley-Tukey fast algorithm of N=r1*r2, Cooley-Tukey is explained Fast algorithm, point five steps:

A. x (n) is rewritten into x (n1, n0), utilizes

X (n)=x (r₂n₁+n₀)=x (n₁,n₀),

B. it is the FFT of r2 r1 point, obtains X1 (k0, n0).

$X_1(k_0,n_0)=\underset{n_1=0}{\overset{r_1-1}{\Σ}}x(n_1,n_0)W_{r_1}^{n_1{k}_0},k_0=0,1,...,r_1-1$

C. N number of X1 (k0, n0) is multiplied by corresponding twiddle factorComposition X1 ' (k0, n0).

${X_1}^{\′}(k_0,n_0)=X_1(k_0,n_0)W_N^{n_0{k}_0}$

D. it is r1 r2 point FFT, obtains X2 (k0, k1).

$X_2(k_0,k_1)=\underset{n_0=0}{\overset{r_2-1}{\Σ}}{X_1}^{\′}(k_0,n_0)W_{r_2}^{n_0{k}_1},k_1=0,1,...,r_2-1$

E. carry out whole sequence, obtain X (k1, k0)=X (k), wherein k=r1*k1+k0.

X(k₁,k₀)=X₂(k₀,k₁)

Fft algorithm based on Cooley-Tukey uses the dish-shaped computing of Radix-4 to be achieved, relatively in the design It is greatly reduced at operation times and having had on operation time in traditional Radix-2 dish computing；From five above-mentioned steps Can draw in Zhou, fft algorithm based on Cooley-Tukey includes plural number addition and subtraction, complex multiplication and twiddle factor's Access.

As it is shown in figure 1, be the dish-shaped computing calculation of Radix-4.

Computing formula is:

X (K)=A+BW^P+CW^2P+DW^3P

X (K+N/4)=A-jBW^P-CW^2P+jDW^3P

X (K+2N/4)=A-jBW^P+CW^2P-jDW^3P

X (K+3N/4)=A+jBW^P-CW^2P-jDW^3P

Computing formula can be divided into following complex operation:

X'[n]=[(x [n]+x [n+N/2])]+[(x [n+N/4]+x [n+3N/4])]

X'[n+N/2]=[(x [n]+x [n+N/2])]-[(x [n+N/4]+x [n+3N/4])]

X'[n+N/4]=[(x [n]-x [n+N/2])]-j* [(x [n+N/4]-x [n+3N/4])]

X'[n+3N/4]=[(x [n]-x [n+N/2])]+j* [(x [n+N/4]-x [n+3N/4])]

Formula 2

As Figure 2-3, from formula 2, plus-minus calculating can be summarized as a+b, tetra-kinds of forms of a-b, a+jb, a-jb.Adopt This computing can be completed with complex adder and complex subtraction device.

As shown in Figure 4, from formula 2, multiplying can be to be summarized as following form:

Y=A × B=(a+jb) × (c+jd)=(ac-bd)+j (ad+bc)=y_re+jy_im

For for result Y that A, B are multiplied, its real part and imaginary part can be done such as down conversion:

y_re=(ac-bd)=ac-ad+ad-bd=(c-d) a+ (a-b) d

y_im=(ad+bc)=ad-bd+bd+bc=(c+d) b+ (a-b) d

As it is shown in fig. 7, be the butterfly unit according to the design of above-mentioned plus-minus multiplication method.

As it is shown in figure 5, twiddle factorVector e can be expressed as^jθ=cos θ+jsin θ, this vector real part and Imaginary part stores in a register, utilizes look-up table mode to realize vector rotation operation.In the design, in order to reduce depositing of RAM Storage space, is only stored in 1/8 circle, i.e.Between twiddle factor.Other twiddle factor is all this 1/8 circumferential area The conversion of interior twiddle factor.According to periodicity and the symmetry of twiddle factor, the twiddle factor in other regions, by exchange real part Imaginary part and change sign obtain.

Such as: the A that sets up an office is for whereinA twiddle factor, it is assumed that it is write as vector form is A=cosx+j* sinx。

Other 7 projections being then mapped in 4 quadrants are:

sin x+j*cos x；-cos x+j*sin x；-sin x+j*cos x；-cos x+j*(-sin x)；

-sin x+j*(-cos x)；sin x+j*(-cos x)；cos x+j*(-sin x).

Add up and come to 8 data.

Have only to the numerical value of the real part by such a data and imaginary part, do not include that symbol is respectively stored in register same In the data storage cell of one address, it is possible to after taking out these data, by conversion, arrange its real part and void properly Portion, assigns its sign again, obtains other other 7 twiddle factors required in this grade of computing.

As shown in Figure 6, computing module (including plus and minus calculation and multiplying) is Radix-4 computing module, control module Produce all of control signal, the read/write address of memory 1 and 2, write the enabling signal twiddle factor table of enable, computing module The signals such as read/write address.

Claims (2)

1. a fft algorithm based on Cooley-Tukey, is characterized in that: utilize fpga chip, uses the dish fortune of Radix-4 Calculate, FFT, the N=r1*r2 that N point FFT is resolved into more than one short sequence, comprise the following steps:

Step 1: x (n) is rewritten into x (n1, n0), utilizes

$x\left(n\right)=x(r_2{n}_1+n_0)=x(n_1,n_0),\left\{\begin{array}{c}{n}_1=0,1,2,...,r_1-1\\ n_0=0,1,2,...,r_2-1\end{array}\right.;$

Step 2: be the FFT of r2 r1 point, obtains X1 (k0, n0)；

$X_1(k_0,n_0)=\underset{n_1=0}{\overset{r_1-1}{\Σ}}x(n_1,n_0)W_{r_1}^{n_1{k}_0},k_0=0,1,...,r_1-1;$

Step 3: N number of X1 (k0, n0) is multiplied by corresponding twiddle factorComposition X1 ' (k0, n0)；

${X_1}^{\′}(k_0,n_0)=X_1(k_0,n_0)W_N^{n_0{k}_0}$

Step 4: be r1 r2 point FFT, obtain X2 (k0, k1)；

$X_2(k_0,k_1)=\underset{n_0=0}{\overset{r_2-1}{\Σ}}{X_1}^{\′}(k_0,n_0)W_{r_2}^{n_0{k}_1},k_1=0,1,...,r_2-1;$

Step 5: carry out whole sequence, obtains X (k1, k0)=X (k), wherein k=r1*k1+k0；

X(k₁,k₀)=X₂(k₀,k₁)。

A kind of fft algorithm based on Cooley-Tukey the most according to claim 1, is characterized in that: in step 4, rotates The factorWith vector e^jθThe form performance of=cos θ+jsin θ, realizes vector rotation operation in look-up table mode；This vector Real part and imaginary part store in a register, and be only stored in 1/8 circle in, i.e.Between twiddle factor；According to rotate because of The periodicity of son and symmetry, obtain other twiddle factor by exchange real part imaginary part and change sign.